diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:09:54 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:09:54 -0400 |
| commit | 54227f9e57f625a66e3fd1d0d67fbd53b5408bf2 (patch) | |
| tree | 77faeed4436765032a90ede56ba9d231f1c717aa /tests/long/se/70.twolf/ref/alpha/tru64 | |
| parent | 1c321b88473d65ff4bd9a7b65a91351781fd31d8 (diff) | |
| download | gem5-54227f9e57f625a66e3fd1d0d67fbd53b5408bf2.tar.xz | |
Stats: Update stats for new default L1-to-L2 bus clock and width
This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.
Diffstat (limited to 'tests/long/se/70.twolf/ref/alpha/tru64')
3 files changed, 857 insertions, 857 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index c057cfc04..aad21c6d0 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.042012 # Number of seconds simulated -sim_ticks 42012413000 # Number of ticks simulated -final_tick 42012413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.042001 # Number of seconds simulated +sim_ticks 42001440000 # Number of ticks simulated +final_tick 42001440000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 107145 # Simulator instruction rate (inst/s) -host_op_rate 107145 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48980163 # Simulator tick rate (ticks/s) -host_mem_usage 222716 # Number of bytes of host memory used -host_seconds 857.74 # Real time elapsed on the host +host_inst_rate 75192 # Simulator instruction rate (inst/s) +host_op_rate 75192 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34364250 # Simulator tick rate (ticks/s) +host_mem_usage 223172 # Number of bytes of host memory used +host_seconds 1222.24 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 178816 # Nu system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 4256266 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3266082 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7522348 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4256266 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4256266 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4256266 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3266082 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7522348 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 4257378 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3266936 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7524313 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4257378 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4257378 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4257378 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3266936 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7524313 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -43,10 +43,10 @@ system.cpu.dtb.data_hits 26498122 # DT system.cpu.dtb.data_misses 33 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 26498155 # DTB accesses -system.cpu.itb.fetch_hits 10034924 # ITB hits +system.cpu.itb.fetch_hits 10035828 # ITB hits system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 10034973 # ITB accesses +system.cpu.itb.fetch_accesses 10035877 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,42 +60,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 84024827 # number of cpu cycles simulated +system.cpu.numCycles 84002881 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 13564834 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 9782438 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 4497092 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 7991226 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 3849853 # Number of BTB hits +system.cpu.branch_predictor.lookups 13564877 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 9782208 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 4497797 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 7992443 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 3850454 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target. -system.cpu.branch_predictor.RASInCorrect 121 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 48.176000 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 5999065 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 7565769 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 73744929 # Number of Reads from Int. Register File +system.cpu.branch_predictor.RASInCorrect 122 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 48.176183 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 5999677 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 7565200 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 73745294 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 136320401 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 136320766 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 2206799 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 8058687 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 38529057 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 26768938 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 3519911 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 976323 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4496234 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 5744468 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 43.905525 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 57470438 # Number of Instructions Executed. +system.cpu.regfile_manager.regForwards 38528678 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 26769096 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 3520460 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 976479 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4496939 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 5743763 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 43.912410 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 57470351 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 458258 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 83640241 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 83639631 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 11659 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7743859 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 76280968 # Number of cycles cpu stages are processed. -system.cpu.activity 90.783844 # Percentage of cycles cpu is active +system.cpu.timesIdled 11378 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7720370 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 76282511 # Number of cycles cpu stages are processed. +system.cpu.activity 90.809399 # Percentage of cycles cpu is active system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed @@ -107,144 +107,144 @@ system.cpu.committedInsts 91903056 # Nu system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) -system.cpu.cpi 0.914277 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.914038 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.914277 # CPI: Total CPI of All Threads -system.cpu.ipc 1.093761 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.914038 # CPI: Total CPI of All Threads +system.cpu.ipc 1.094046 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.093761 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 27805541 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 56219286 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 66.907946 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 34577681 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 49447146 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 58.848257 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 34047365 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 49977462 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 59.479399 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65995198 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 18029629 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.457502 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 30080947 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 53943880 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.199930 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 8128 # number of replacements -system.cpu.icache.tagsinuse 1492.257079 # Cycle average of tags in use -system.cpu.icache.total_refs 10023168 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 10013 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1001.015480 # Average number of references to valid blocks. +system.cpu.ipc_total 1.094046 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 27781439 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 56221442 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 66.927993 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 34555420 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 49447461 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 58.864006 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 34024816 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 49978065 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 59.495656 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65973303 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 18029578 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.463047 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 30058791 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 53944090 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.216952 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 8127 # number of replacements +system.cpu.icache.tagsinuse 1492.293343 # Cycle average of tags in use +system.cpu.icache.total_refs 10024070 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 10012 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1001.205553 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1492.257079 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.728641 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.728641 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10023168 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10023168 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10023168 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10023168 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10023168 # number of overall hits -system.cpu.icache.overall_hits::total 10023168 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11752 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11752 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11752 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11752 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11752 # number of overall misses -system.cpu.icache.overall_misses::total 11752 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 302404500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 302404500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 302404500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 302404500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 302404500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 302404500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 10034920 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 10034920 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 10034920 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 10034920 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 10034920 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 10034920 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1492.293343 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.728659 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.728659 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 10024070 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10024070 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10024070 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10024070 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10024070 # number of overall hits +system.cpu.icache.overall_hits::total 10024070 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11754 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11754 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11754 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11754 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11754 # number of overall misses +system.cpu.icache.overall_misses::total 11754 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 284626500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 284626500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 284626500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 284626500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 284626500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 284626500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 10035824 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 10035824 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 10035824 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 10035824 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 10035824 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 10035824 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001171 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001171 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001171 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.001171 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001171 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001171 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25732.173247 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25732.173247 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25732.173247 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25732.173247 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25732.173247 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25732.173247 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24215.288412 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 24215.288412 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 24215.288412 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 24215.288412 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 24215.288412 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 24215.288412 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 91000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 92000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 15166.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 15333.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1739 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1739 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1739 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1739 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1739 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1739 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10013 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 10013 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 10013 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 10013 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 10013 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 10013 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 234933000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 234933000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 234933000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 234933000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 234933000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 234933000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1742 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1742 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1742 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1742 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1742 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1742 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10012 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 10012 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 10012 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 10012 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 10012 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 10012 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 231904000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 231904000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 231904000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 231904000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 231904000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 231904000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000998 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000998 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000998 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23462.798362 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23462.798362 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23462.798362 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 23462.798362 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23462.798362 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 23462.798362 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23162.604874 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23162.604874 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23162.604874 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 23162.604874 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23162.604874 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 23162.604874 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1441.425760 # Cycle average of tags in use -system.cpu.dcache.total_refs 26491190 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1441.465399 # Cycle average of tags in use +system.cpu.dcache.total_refs 26491189 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11916.864597 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11916.864148 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1441.425760 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.351911 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.351911 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 19995640 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 19995640 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 1441.465399 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.351920 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.351920 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 19995639 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 19995639 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 6495550 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 6495550 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26491190 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26491190 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26491190 # number of overall hits -system.cpu.dcache.overall_hits::total 26491190 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 558 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 558 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 26491189 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26491189 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26491189 # number of overall hits +system.cpu.dcache.overall_hits::total 26491189 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 559 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 559 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 5553 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 5553 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 6111 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 6111 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 6111 # number of overall misses -system.cpu.dcache.overall_misses::total 6111 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29911500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29911500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 335932500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 335932500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 365844000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 365844000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 365844000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 365844000 # number of overall miss cycles +system.cpu.dcache.demand_misses::cpu.data 6112 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 6112 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 6112 # number of overall misses +system.cpu.dcache.overall_misses::total 6112 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 28955000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 28955000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 305088500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 305088500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 334043500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 334043500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 334043500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 334043500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -261,32 +261,32 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000231 system.cpu.dcache.demand_miss_rate::total 0.000231 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000231 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000231 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53604.838710 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 53604.838710 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60495.678012 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60495.678012 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59866.470299 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59866.470299 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59866.470299 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59866.470299 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51797.853309 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51797.853309 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54941.202953 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54941.202953 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54653.714005 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54653.714005 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54653.714005 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54653.714005 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 41291000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 41228500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 827 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 49928.657799 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 49853.083434 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 107 # number of writebacks system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 84 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3805 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 3805 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3888 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3888 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3888 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3888 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3889 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3889 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3889 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3889 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses @@ -295,14 +295,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24206500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24206500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 96919000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 96919000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 121125500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 121125500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 121125500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 121125500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24156000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24156000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 96637000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 96637000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 120793000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 120793000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 120793000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 120793000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -311,41 +311,41 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50961.052632 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50961.052632 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55445.652174 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55445.652174 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54487.404408 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 54487.404408 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54487.404408 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 54487.404408 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50854.736842 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50854.736842 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55284.324943 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55284.324943 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54337.831759 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 54337.831759 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54337.831759 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 54337.831759 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2189.621103 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7286 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2189.683531 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7285 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.219988 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.219683 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.844366 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1820.786741 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 350.989996 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 17.845444 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1820.840268 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 350.997820 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.055566 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.010711 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.066822 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 7219 # number of ReadReq hits +system.cpu.l2cache.occ_percent::cpu.inst 0.055568 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.010712 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.066824 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 7218 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 7272 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 7271 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 7219 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 7218 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7298 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 7219 # number of overall hits +system.cpu.l2cache.demand_hits::total 7297 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 7218 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits -system.cpu.l2cache.overall_hits::total 7298 # number of overall hits +system.cpu.l2cache.overall_hits::total 7297 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 2794 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 3216 # number of ReadReq misses @@ -357,52 +357,52 @@ system.cpu.l2cache.demand_misses::total 4938 # nu system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4938 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 149287500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 23083500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 172371000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 94426500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 94426500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 149287500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 117510000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 266797500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 149287500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 117510000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 266797500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 10013 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 149399500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 23132500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 172532000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 94615000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 94615000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 149399500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 117747500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 267147000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 149399500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 117747500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 267147000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 10012 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 10488 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 10487 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 10013 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 10012 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 12236 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 10013 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 12235 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 10012 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 12236 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.279037 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 12235 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.279065 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.306636 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.306665 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.985126 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.279037 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.279065 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.403563 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.279037 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.403596 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.279065 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.403563 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53431.460272 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54700.236967 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 53597.947761 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54835.365854 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54835.365854 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53431.460272 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54808.768657 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 54029.465371 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53431.460272 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54808.768657 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 54029.465371 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.403596 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53471.546170 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54816.350711 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 53648.009950 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54944.831591 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54944.831591 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53471.546170 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54919.542910 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 54100.243013 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53471.546170 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54919.542910 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 54100.243013 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -422,39 +422,39 @@ system.cpu.l2cache.demand_mshr_misses::total 4938 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115196500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17936000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 133132500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 73235000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 73235000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115196500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 91171000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 206367500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115196500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 91171000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 206367500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.279037 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115312500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17984000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 133296500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 73481500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 73481500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115312500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 91465500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 206778000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115312500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 91465500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 206778000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.306636 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.306665 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.279037 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.403563 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.279037 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.403596 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.403563 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41229.957051 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42502.369668 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41396.921642 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42529.036005 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42529.036005 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41229.957051 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42523.787313 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41791.717294 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41229.957051 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42523.787313 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41791.717294 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.403596 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41271.474588 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42616.113744 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41447.916667 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42672.183508 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42672.183508 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41271.474588 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42661.147388 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41874.848117 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41271.474588 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42661.147388 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41874.848117 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 79c8453b1..4339a22dc 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023661 # Number of seconds simulated -sim_ticks 23661066000 # Number of ticks simulated -final_tick 23661066000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023660 # Number of seconds simulated +sim_ticks 23659827000 # Number of ticks simulated +final_tick 23659827000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 163409 # Simulator instruction rate (inst/s) -host_op_rate 163409 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45930776 # Simulator tick rate (ticks/s) -host_mem_usage 223740 # Number of bytes of host memory used -host_seconds 515.15 # Real time elapsed on the host +host_inst_rate 114539 # Simulator instruction rate (inst/s) +host_op_rate 114539 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32192844 # Simulator tick rate (ticks/s) +host_mem_usage 224192 # Number of bytes of host memory used +host_seconds 734.94 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 197312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 197632 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 138432 # Number of bytes read from this memory -system.physmem.bytes_read::total 335744 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 197312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 197312 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3083 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 336064 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 197632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 197632 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3088 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2163 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5246 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8339100 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5850624 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14189724 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8339100 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8339100 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8339100 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5850624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 14189724 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 5251 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8353062 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5850930 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14203992 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8353062 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8353062 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8353062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5850930 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 14203992 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 23226472 # DTB read hits -system.cpu.dtb.read_misses 199471 # DTB read misses -system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 23425943 # DTB read accesses -system.cpu.dtb.write_hits 7079215 # DTB write hits -system.cpu.dtb.write_misses 1341 # DTB write misses -system.cpu.dtb.write_acv 3 # DTB write access violations -system.cpu.dtb.write_accesses 7080556 # DTB write accesses -system.cpu.dtb.data_hits 30305687 # DTB hits -system.cpu.dtb.data_misses 200812 # DTB misses -system.cpu.dtb.data_acv 5 # DTB access violations -system.cpu.dtb.data_accesses 30506499 # DTB accesses -system.cpu.itb.fetch_hits 14950241 # ITB hits -system.cpu.itb.fetch_misses 107 # ITB misses +system.cpu.dtb.read_hits 23229098 # DTB read hits +system.cpu.dtb.read_misses 198676 # DTB read misses +system.cpu.dtb.read_acv 4 # DTB read access violations +system.cpu.dtb.read_accesses 23427774 # DTB read accesses +system.cpu.dtb.write_hits 7078776 # DTB write hits +system.cpu.dtb.write_misses 1365 # DTB write misses +system.cpu.dtb.write_acv 4 # DTB write access violations +system.cpu.dtb.write_accesses 7080141 # DTB write accesses +system.cpu.dtb.data_hits 30307874 # DTB hits +system.cpu.dtb.data_misses 200041 # DTB misses +system.cpu.dtb.data_acv 8 # DTB access violations +system.cpu.dtb.data_accesses 30507915 # DTB accesses +system.cpu.itb.fetch_hits 14959914 # ITB hits +system.cpu.itb.fetch_misses 83 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14950348 # ITB accesses +system.cpu.itb.fetch_accesses 14959997 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,146 +60,146 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 47322133 # number of cpu cycles simulated +system.cpu.numCycles 47319655 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15026940 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 10894124 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 964629 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 8768677 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7072325 # Number of BTB hits +system.cpu.BPredUnit.lookups 15036576 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10900203 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 965407 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 8822625 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7081383 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1489344 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 3225 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 15650036 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 128237375 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15026940 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 8561669 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22385381 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4637420 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5548184 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2165 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14950241 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 337394 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 47225069 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.715451 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.372476 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1488044 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 3227 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15623244 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 128299344 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15036576 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 8569427 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22397875 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4641617 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5564099 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1980 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14959914 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 337946 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 47229880 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.716487 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.372485 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24839688 52.60% 52.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2391446 5.06% 57.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1209126 2.56% 60.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1776446 3.76% 63.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2802962 5.94% 69.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1171165 2.48% 72.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1227887 2.60% 75.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 787448 1.67% 76.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11018901 23.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24832005 52.58% 52.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2392801 5.07% 57.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1209799 2.56% 60.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1776867 3.76% 63.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2804961 5.94% 69.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1173464 2.48% 72.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1230763 2.61% 75.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 789158 1.67% 76.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11020062 23.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 47225069 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.317546 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.709882 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17490874 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4250840 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20765641 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1090220 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3627494 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2542741 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12176 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 125152088 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 32110 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3627494 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18655906 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 966254 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8182 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20668416 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3298817 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 122169743 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 401900 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2424267 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 89702215 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 158657740 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 148914395 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9743345 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 47229880 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.317766 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.711333 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17466031 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4264969 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20777128 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1090965 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3630787 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2547167 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12222 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 125218187 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 32252 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3630787 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18637244 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 968362 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8091 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20675127 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3310269 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 122217574 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 404537 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2431302 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 89737060 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 158727741 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 148984302 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9743439 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 21274854 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1091 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1100 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8739612 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 25558040 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8300974 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2604808 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 921406 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 106164029 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2236 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 96990974 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 187003 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21520200 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16153199 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1847 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 47225069 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.053803 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.875376 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 21309699 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1072 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1080 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8762996 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 25566964 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8306109 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2633900 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 924738 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 106206807 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2480 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 97009064 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 188398 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21564802 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16193043 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2091 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 47229880 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.053977 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.874944 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12469931 26.41% 26.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 9437048 19.98% 46.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8469534 17.93% 64.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6320288 13.38% 77.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4943441 10.47% 88.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2849790 6.03% 94.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1723941 3.65% 97.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 801134 1.70% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 209962 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12465875 26.39% 26.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9434862 19.98% 46.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8477387 17.95% 64.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6321383 13.38% 77.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4949351 10.48% 88.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2846830 6.03% 94.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1724266 3.65% 97.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 801279 1.70% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 208647 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 47225069 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 47229880 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 187127 11.94% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 172 0.01% 11.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 7127 0.45% 12.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 5609 0.36% 12.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 843370 53.79% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 445220 28.40% 94.95% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 79228 5.05% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 189791 12.08% 12.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 12.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 12.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 221 0.01% 12.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 7127 0.45% 12.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 5711 0.36% 12.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 843066 53.68% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 445505 28.36% 94.95% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 79246 5.05% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58991306 60.82% 60.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 480706 0.50% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 59007350 60.83% 60.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 480907 0.50% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2802495 2.89% 64.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115483 0.12% 64.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2386219 2.46% 66.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 311493 0.32% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 759735 0.78% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2801835 2.89% 64.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115568 0.12% 64.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2386144 2.46% 66.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 311424 0.32% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 759643 0.78% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.89% # Type of FU issued @@ -221,84 +221,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.89% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23972181 24.72% 92.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7171030 7.39% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23975074 24.71% 92.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7170793 7.39% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 96990974 # Type of FU issued -system.cpu.iq.rate 2.049590 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1567853 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016165 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 227829224 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 118898019 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87368354 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15132649 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 8823096 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7068677 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90563080 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7995740 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1518780 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 97009064 # Type of FU issued +system.cpu.iq.rate 2.050080 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1570667 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016191 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 227877046 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 118983933 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87385352 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15130027 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 8824854 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7067767 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90585387 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7994337 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1520935 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5561842 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 19579 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34790 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1799871 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5570766 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 20063 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34811 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1805006 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10514 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10523 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3627494 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 132338 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17118 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 116467170 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 392102 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 25558040 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8300974 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2236 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2929 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 49 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34790 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 570155 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 508194 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1078349 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 95694648 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23426609 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1296326 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3630787 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 133855 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17474 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 116506957 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 391259 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 25566964 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8306109 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2480 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3139 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 46 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 34811 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 570809 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 508196 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1079005 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 95710462 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23428475 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1298602 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10300905 # number of nop insts executed -system.cpu.iew.exec_refs 30507339 # number of memory reference insts executed -system.cpu.iew.exec_branches 12077728 # Number of branches executed -system.cpu.iew.exec_stores 7080730 # Number of stores executed -system.cpu.iew.exec_rate 2.022196 # Inst execution rate -system.cpu.iew.wb_sent 94980194 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 94437031 # cumulative count of insts written-back -system.cpu.iew.wb_producers 64621172 # num instructions producing a value -system.cpu.iew.wb_consumers 90003030 # num instructions consuming a value +system.cpu.iew.exec_nop 10297670 # number of nop insts executed +system.cpu.iew.exec_refs 30508815 # number of memory reference insts executed +system.cpu.iew.exec_branches 12080088 # Number of branches executed +system.cpu.iew.exec_stores 7080340 # Number of stores executed +system.cpu.iew.exec_rate 2.022637 # Inst execution rate +system.cpu.iew.wb_sent 94996847 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 94453119 # cumulative count of insts written-back +system.cpu.iew.wb_producers 64630172 # num instructions producing a value +system.cpu.iew.wb_consumers 90018458 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.995621 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717989 # average fanout of values written-back +system.cpu.iew.wb_rate 1.996065 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717966 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24565165 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 24605076 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 952869 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43597575 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.107985 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.734489 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 953560 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43599093 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.107912 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.734433 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 17052737 39.11% 39.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9973933 22.88% 61.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4509329 10.34% 72.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2295130 5.26% 77.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1618190 3.71% 81.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1123694 2.58% 83.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 722585 1.66% 85.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 817482 1.88% 87.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5484495 12.58% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 17053308 39.11% 39.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9978024 22.89% 62.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4508053 10.34% 72.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2287531 5.25% 77.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1622514 3.72% 81.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1125878 2.58% 83.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 721380 1.65% 85.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 820634 1.88% 87.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5481771 12.57% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43597575 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43599093 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -309,70 +309,70 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5484495 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5481771 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 154580260 # The number of ROB reads -system.cpu.rob.rob_writes 236588154 # The number of ROB writes -system.cpu.timesIdled 2240 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 97064 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 154624413 # The number of ROB reads +system.cpu.rob.rob_writes 236671244 # The number of ROB writes +system.cpu.timesIdled 1995 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 89775 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.562156 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.562156 # CPI: Total CPI of All Threads -system.cpu.ipc 1.778865 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.778865 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 129472042 # number of integer regfile reads -system.cpu.int_regfile_writes 70778136 # number of integer regfile writes -system.cpu.fp_regfile_reads 6192217 # number of floating regfile reads -system.cpu.fp_regfile_writes 6050128 # number of floating regfile writes -system.cpu.misc_regfile_reads 714420 # number of misc regfile reads +system.cpu.cpi 0.562127 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.562127 # CPI: Total CPI of All Threads +system.cpu.ipc 1.778959 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.778959 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 129495815 # number of integer regfile reads +system.cpu.int_regfile_writes 70794338 # number of integer regfile writes +system.cpu.fp_regfile_reads 6191717 # number of floating regfile reads +system.cpu.fp_regfile_writes 6049387 # number of floating regfile writes +system.cpu.misc_regfile_reads 714327 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 10236 # number of replacements -system.cpu.icache.tagsinuse 1604.355346 # Cycle average of tags in use -system.cpu.icache.total_refs 14936697 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 12175 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1226.833429 # Average number of references to valid blocks. +system.cpu.icache.replacements 10388 # number of replacements +system.cpu.icache.tagsinuse 1605.369069 # Cycle average of tags in use +system.cpu.icache.total_refs 14946221 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 12326 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1212.576748 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1604.355346 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.783377 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.783377 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14936697 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14936697 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14936697 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14936697 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14936697 # number of overall hits -system.cpu.icache.overall_hits::total 14936697 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13544 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 13544 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 13544 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13544 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13544 # number of overall misses -system.cpu.icache.overall_misses::total 13544 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 214516500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 214516500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 214516500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 214516500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 214516500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 214516500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14950241 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14950241 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14950241 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14950241 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14950241 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14950241 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000906 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000906 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000906 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000906 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000906 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000906 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15838.489368 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15838.489368 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15838.489368 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15838.489368 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15838.489368 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15838.489368 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1605.369069 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.783872 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.783872 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14946221 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14946221 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14946221 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14946221 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14946221 # number of overall hits +system.cpu.icache.overall_hits::total 14946221 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 13693 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 13693 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 13693 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 13693 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 13693 # number of overall misses +system.cpu.icache.overall_misses::total 13693 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 189030000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 189030000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 189030000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 189030000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 189030000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 189030000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14959914 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14959914 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14959914 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14959914 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14959914 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14959914 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000915 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000915 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000915 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000915 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000915 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000915 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13804.863799 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13804.863799 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13804.863799 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13804.863799 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13804.863799 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13804.863799 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,300 +381,300 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1369 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1369 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1369 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1369 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1369 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1369 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12175 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 12175 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 12175 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 12175 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 12175 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 12175 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 142455000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 142455000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 142455000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 142455000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 142455000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 142455000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000814 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000814 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000814 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000814 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000814 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000814 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11700.616016 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11700.616016 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11700.616016 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11700.616016 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11700.616016 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11700.616016 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1367 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1367 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1367 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1367 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1367 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1367 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12326 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 12326 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 12326 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 12326 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 12326 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 12326 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 130707500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 130707500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 130707500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 130707500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 130707500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 130707500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000824 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000824 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000824 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000824 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000824 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000824 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10604.210612 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10604.210612 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10604.210612 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 10604.210612 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10604.210612 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 10604.210612 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 158 # number of replacements -system.cpu.dcache.tagsinuse 1456.192464 # Cycle average of tags in use -system.cpu.dcache.total_refs 28189208 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1458.278820 # Cycle average of tags in use +system.cpu.dcache.total_refs 28189701 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2243 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12567.636202 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 12567.855996 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1456.192464 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.355516 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.355516 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 21695723 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21695723 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6493020 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6493020 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 465 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 465 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28188743 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28188743 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28188743 # number of overall hits -system.cpu.dcache.overall_hits::total 28188743 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 984 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 984 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8083 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8083 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 1458.278820 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.356025 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.356025 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 21696214 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21696214 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6493021 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6493021 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 466 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 466 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28189235 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28189235 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28189235 # number of overall hits +system.cpu.dcache.overall_hits::total 28189235 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 958 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 958 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8082 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8082 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9067 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9067 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9067 # number of overall misses -system.cpu.dcache.overall_misses::total 9067 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32711000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32711000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 344620000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 344620000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 45000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 45000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 377331000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 377331000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 377331000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 377331000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21696707 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21696707 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9040 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9040 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9040 # number of overall misses +system.cpu.dcache.overall_misses::total 9040 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29562000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29562000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 293120000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 293120000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 44000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 44000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 322682000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 322682000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 322682000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 322682000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21697172 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21697172 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 466 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28197810 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28197810 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28197810 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28197810 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 467 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 467 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28198275 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28198275 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28198275 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28198275 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000044 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000044 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001243 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001243 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002146 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002146 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000322 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000322 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000322 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000322 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33242.886179 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33242.886179 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42635.160213 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42635.160213 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 45000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 45000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41615.859711 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41615.859711 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41615.859711 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41615.859711 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12500 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002141 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002141 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000321 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000321 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000321 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000321 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30858.037578 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30858.037578 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36268.250433 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36268.250433 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 44000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 44000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35694.911504 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 35694.911504 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35694.911504 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35694.911504 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5500 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 108 # number of writebacks system.cpu.dcache.writebacks::total 108 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 474 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 474 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6351 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6351 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6825 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6825 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6825 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6825 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 510 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 510 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1732 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1732 # number of WriteReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 446 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 446 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6352 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6352 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6798 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6798 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6798 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6798 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 512 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 512 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1730 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1730 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 2242 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 2242 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2242 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2242 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18104500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 18104500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 68881000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 68881000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18075000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 18075000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 68210000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 68210000 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 42000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 42000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 86985500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 86985500 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 99150000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 77116500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 176266500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 99150000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 77116500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 176266500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.250527 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.894531 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.276211 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984980 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984980 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.250527 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964333 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.363851 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.253224 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.360423 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.250527 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964333 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.363851 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32072.656503 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34913.566740 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32439.406780 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35712.192263 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35712.192263 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32072.656503 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35543.458160 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33503.717118 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32072.656503 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35543.458160 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33503.717118 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.360423 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32108.160622 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35073.144105 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32491.116751 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35808.211144 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35808.211144 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32108.160622 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35652.565881 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33568.177490 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32108.160622 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35652.565881 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33568.177490 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index d3e99f110..220e3a05f 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.118780 # Number of seconds simulated -sim_ticks 118779533000 # Number of ticks simulated -final_tick 118779533000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.118729 # Number of seconds simulated +sim_ticks 118729316000 # Number of ticks simulated +final_tick 118729316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1503058 # Simulator instruction rate (inst/s) -host_op_rate 1503057 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1942616372 # Simulator tick rate (ticks/s) -host_mem_usage 222720 # Number of bytes of host memory used -host_seconds 61.14 # Real time elapsed on the host +host_inst_rate 979371 # Simulator instruction rate (inst/s) +host_op_rate 979371 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1265246648 # Simulator tick rate (ticks/s) +host_mem_usage 223148 # Number of bytes of host memory used +host_seconds 93.84 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 167744 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 167744 # Nu system.physmem.num_reads::cpu.inst 2621 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::total 4765 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1412230 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1155216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2567446 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1412230 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1412230 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1412230 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1155216 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2567446 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1412827 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1155704 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2568532 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1412827 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1412827 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1412827 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1155704 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2568532 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -60,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 237559066 # number of cpu cycles simulated +system.cpu.numCycles 237458632 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 91903056 # Number of instructions committed @@ -79,18 +79,18 @@ system.cpu.num_mem_refs 26497334 # nu system.cpu.num_load_insts 19996208 # Number of load instructions system.cpu.num_store_insts 6501126 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 237559066 # Number of busy cycles +system.cpu.num_busy_cycles 237458632 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 6681 # number of replacements -system.cpu.icache.tagsinuse 1417.992791 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1418.052773 # Cycle average of tags in use system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 10798.423032 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1417.992791 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.692379 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.692379 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1418.052773 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.692409 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.692409 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 91894580 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 91894580 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 91894580 # number of demand (read+write) hits @@ -103,12 +103,12 @@ system.cpu.icache.demand_misses::cpu.inst 8510 # n system.cpu.icache.demand_misses::total 8510 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 8510 # number of overall misses system.cpu.icache.overall_misses::total 8510 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 229226000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 229226000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 229226000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 229226000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 229226000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 229226000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 220712000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 220712000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 220712000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 220712000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 220712000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 220712000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 91903090 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 91903090 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 91903090 # number of demand (read+write) accesses @@ -121,12 +121,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26936.075206 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 26936.075206 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 26936.075206 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 26936.075206 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 26936.075206 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 26936.075206 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25935.605170 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25935.605170 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25935.605170 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25935.605170 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25935.605170 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25935.605170 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -141,34 +141,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 8510 system.cpu.icache.demand_mshr_misses::total 8510 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 8510 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 8510 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 203696000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 203696000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 203696000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 203696000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 203696000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 203696000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 203692000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 203692000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 203692000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 203692000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 203692000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 203692000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000093 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000093 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23936.075206 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23936.075206 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23936.075206 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 23936.075206 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23936.075206 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 23936.075206 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23935.605170 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23935.605170 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1441.982871 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1442.043392 # Cycle average of tags in use system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1441.982871 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.352047 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.352047 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 1442.043392 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.352061 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits @@ -185,14 +185,14 @@ system.cpu.dcache.demand_misses::cpu.data 2223 # n system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses system.cpu.dcache.overall_misses::total 2223 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24380000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24380000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 96796000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 96796000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 121176000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 121176000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 121176000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 121176000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 23899000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 23899000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 95048000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 95048000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 118947000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 118947000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 118947000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 118947000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -209,14 +209,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51326.315789 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51326.315789 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55375.286041 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55375.286041 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54510.121457 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54510.121457 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54510.121457 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54510.121457 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50313.684211 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50313.684211 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54375.286041 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54375.286041 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53507.422402 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53507.422402 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -235,14 +235,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22955000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 22955000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22949000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 22949000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 91552000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 91552000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114507000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 114507000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114507000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 114507000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114501000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 114501000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114501000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 114501000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -251,28 +251,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48326.315789 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48326.315789 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48313.684211 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48313.684211 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52375.286041 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52375.286041 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51510.121457 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51510.121457 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51510.121457 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51510.121457 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2073.981313 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2074.070560 # Cycle average of tags in use system.cpu.l2cache.total_refs 5956 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3109 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 1.915729 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.795350 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1704.943449 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 351.242515 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 17.795178 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1705.018003 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 351.257379 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.052031 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.010719 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.063293 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.052033 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.010720 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.063296 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 5889 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 5942 # number of ReadReq hits |