diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
| commit | 8909843a76c723cb9d8a0b1394eeeba4d7abadb1 (patch) | |
| tree | 446fe188000e814cbc7d23075428cab7f44868d1 /tests/long/se/70.twolf/ref/alpha | |
| parent | fc315901ff4aaae0f56c4c1b1c50ffe9bd70b4d6 (diff) | |
| download | gem5-8909843a76c723cb9d8a0b1394eeeba4d7abadb1.tar.xz | |
stats: Update stats to reflect cache and interconnect changes
This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
Diffstat (limited to 'tests/long/se/70.twolf/ref/alpha')
3 files changed, 1111 insertions, 1110 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index ae03186ae..e483ad3f0 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.052167 # Number of seconds simulated -sim_ticks 52167245000 # Number of ticks simulated -final_tick 52167245000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.052202 # Number of seconds simulated +sim_ticks 52201532500 # Number of ticks simulated +final_tick 52201532500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 211928 # Simulator instruction rate (inst/s) -host_op_rate 211928 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 120297341 # Simulator tick rate (ticks/s) -host_mem_usage 286252 # Number of bytes of host memory used -host_seconds 433.65 # Real time elapsed on the host +host_inst_rate 357575 # Simulator instruction rate (inst/s) +host_op_rate 357575 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 203104604 # Simulator tick rate (ticks/s) +host_mem_usage 300132 # Number of bytes of host memory used +host_seconds 257.02 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 202688 # Nu system.physmem.num_reads::cpu.inst 3167 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2151 # Number of read requests responded to by this memory system.physmem.num_reads::total 5318 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3885350 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2638897 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6524247 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3885350 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3885350 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3885350 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2638897 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6524247 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 3882798 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2637164 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6519962 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3882798 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3882798 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3882798 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2637164 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6519962 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 5318 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 5318 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 52167163500 # Total gap between requests +system.physmem.totGap 52201444000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 386 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4919 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 380 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 972 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 348.971193 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 211.834828 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 332.374999 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 320 32.92% 32.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 191 19.65% 52.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 96 9.88% 62.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 99 10.19% 72.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 63 6.48% 79.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 36 3.70% 82.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 24 2.47% 85.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 26 2.67% 87.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 117 12.04% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 972 # Bytes accessed per row activation -system.physmem.totQLat 32099750 # Total ticks spent queuing -system.physmem.totMemAccLat 131812250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 983 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 345.912513 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 209.979760 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.521018 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 325 33.06% 33.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 203 20.65% 53.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 90 9.16% 62.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 89 9.05% 71.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 77 7.83% 79.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 32 3.26% 83.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 28 2.85% 85.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 23 2.34% 88.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 116 11.80% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 983 # Bytes accessed per row activation +system.physmem.totQLat 33415750 # Total ticks spent queuing +system.physmem.totMemAccLat 133128250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26590000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6036.06 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6283.52 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24786.06 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25033.52 # Average memory access latency per DRAM burst system.physmem.avgRdBW 6.52 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 6.52 # Average system read bandwidth in MiByte/s @@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.05 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4338 # Number of row buffer hits during reads +system.physmem.readRowHits 4331 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.57 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.44 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9809545.60 # Average gap between requests -system.physmem.pageHitRate 81.57 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3530520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1926375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 19827600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 9815991.73 # Average gap between requests +system.physmem.pageHitRate 81.44 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3500280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1909875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 19975800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3406843440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1740830445 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29769165000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34942123380 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.898193 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49520504500 # Time in different power states -system.physmem_0.memoryStateTime::REF 1741740000 # Time in different power states +system.physmem_0.refreshEnergy 3409386240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1770933285 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29766117750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34971823230 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.967540 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49515286750 # Time in different power states +system.physmem_0.memoryStateTime::REF 1743040000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 898118000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 940967000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3772440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2058375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 21216000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3908520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2132625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 21301800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3406843440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1807143390 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29710995750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34952029395 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.088108 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49425818250 # Time in different power states -system.physmem_1.memoryStateTime::REF 1741740000 # Time in different power states +system.physmem_1.refreshEnergy 3409386240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1804216725 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29736921750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34977867660 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.083336 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49466733750 # Time in different power states +system.physmem_1.memoryStateTime::REF 1743040000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 995309750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 989849750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 11476348 # Number of BP lookups -system.cpu.branchPred.condPredicted 8235349 # Number of conditional branches predicted +system.cpu.branchPred.lookups 11476351 # Number of BP lookups +system.cpu.branchPred.condPredicted 8235351 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 785844 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 6672654 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5371509 # Number of BTB hits +system.cpu.branchPred.BTBLookups 6672655 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5371510 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.500338 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1176737 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 80.500341 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1176738 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits @@ -276,10 +276,10 @@ system.cpu.dtb.data_hits 26977004 # DT system.cpu.dtb.data_misses 47407 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 27024411 # DTB accesses -system.cpu.itb.fetch_hits 23068130 # ITB hits +system.cpu.itb.fetch_hits 23068140 # ITB hits system.cpu.itb.fetch_misses 88 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 23068218 # ITB accesses +system.cpu.itb.fetch_accesses 23068228 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,26 +293,26 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 104334490 # number of cpu cycles simulated +system.cpu.numCycles 104403065 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 91903089 # Number of instructions committed system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed system.cpu.discardedOps 2153944 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.135266 # CPI: cycles per instruction -system.cpu.ipc 0.880851 # IPC: instructions per cycle -system.cpu.tickCycles 102681434 # Number of cycles that the object actually ticked -system.cpu.idleCycles 1653056 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.136013 # CPI: cycles per instruction +system.cpu.ipc 0.880272 # IPC: instructions per cycle +system.cpu.tickCycles 102681380 # Number of cycles that the object actually ticked +system.cpu.idleCycles 1721685 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1448.700214 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26568138 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1448.443915 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26568135 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11913.963229 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11913.961883 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1448.700214 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.353687 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.353687 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1448.443915 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.353624 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.353624 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id @@ -320,16 +320,16 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 226 system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1380 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 53145366 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 53145366 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20069946 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20069946 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 53145360 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 53145360 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20069943 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20069943 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 6498192 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 6498192 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26568138 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26568138 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26568138 # number of overall hits -system.cpu.dcache.overall_hits::total 26568138 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 26568135 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26568135 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26568135 # number of overall hits +system.cpu.dcache.overall_hits::total 26568135 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 519 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 519 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 2911 # number of WriteReq misses @@ -338,22 +338,22 @@ system.cpu.dcache.demand_misses::cpu.data 3430 # n system.cpu.dcache.demand_misses::total 3430 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 3430 # number of overall misses system.cpu.dcache.overall_misses::total 3430 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 37684500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 37684500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 195045500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 195045500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 232730000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 232730000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 232730000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 232730000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20070465 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20070465 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 40365000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 40365000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 216719250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 216719250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 257084250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 257084250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 257084250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 257084250 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20070462 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20070462 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 26571568 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 26571568 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 26571568 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 26571568 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 26571565 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26571565 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 26571565 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26571565 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000448 # miss rate for WriteReq accesses @@ -362,14 +362,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000129 system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000129 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72609.826590 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72609.826590 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67002.919959 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 67002.919959 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67851.311953 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67851.311953 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67851.311953 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67851.311953 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77774.566474 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 77774.566474 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74448.385435 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 74448.385435 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 74951.676385 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 74951.676385 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 74951.676385 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 74951.676385 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -396,14 +396,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2230 system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2230 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34103500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 34103500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 117640500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 117640500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 151744000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 151744000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 151744000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 151744000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37010250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 37010250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 130741250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 130741250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 167751500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 167751500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 167751500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 167751500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses @@ -412,24 +412,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70316.494845 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70316.494845 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67415.759312 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67415.759312 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68046.636771 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68046.636771 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68046.636771 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68046.636771 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76309.793814 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76309.793814 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74923.352436 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74923.352436 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75224.887892 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75224.887892 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75224.887892 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75224.887892 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13871 # number of replacements -system.cpu.icache.tags.tagsinuse 1640.665289 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 23052294 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1640.396029 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 23052304 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15835 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1455.781118 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1455.781749 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1640.665289 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.801106 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.801106 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1640.396029 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.800975 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.800975 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1964 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id @@ -437,44 +437,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 669 system.cpu.icache.tags.age_task_id_blocks_1024::3 148 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 948 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.958984 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 46152095 # Number of tag accesses -system.cpu.icache.tags.data_accesses 46152095 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 23052294 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 23052294 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 23052294 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 23052294 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 23052294 # number of overall hits -system.cpu.icache.overall_hits::total 23052294 # number of overall hits +system.cpu.icache.tags.tag_accesses 46152115 # Number of tag accesses +system.cpu.icache.tags.data_accesses 46152115 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 23052304 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 23052304 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 23052304 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 23052304 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 23052304 # number of overall hits +system.cpu.icache.overall_hits::total 23052304 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 15836 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 15836 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 15836 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 15836 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15836 # number of overall misses system.cpu.icache.overall_misses::total 15836 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 386327750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 386327750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 386327750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 386327750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 386327750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 386327750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 23068130 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 23068130 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 23068130 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 23068130 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 23068130 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 23068130 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 409644000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 409644000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 409644000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 409644000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 409644000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 409644000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 23068140 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 23068140 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 23068140 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 23068140 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 23068140 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 23068140 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000686 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000686 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000686 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000686 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000686 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000686 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24395.538646 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 24395.538646 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 24395.538646 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 24395.538646 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 24395.538646 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 24395.538646 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25867.895933 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25867.895933 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25867.895933 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25867.895933 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25867.895933 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25867.895933 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -489,38 +489,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15836 system.cpu.icache.demand_mshr_misses::total 15836 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15836 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15836 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 353292250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 353292250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 353292250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 353292250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 353292250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 353292250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 384517500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 384517500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 384517500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 384517500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 384517500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 384517500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000686 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000686 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000686 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22309.437358 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22309.437358 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22309.437358 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22309.437358 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22309.437358 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22309.437358 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24281.226320 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24281.226320 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24281.226320 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24281.226320 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24281.226320 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24281.226320 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2479.833240 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2479.394298 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 12735 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3665 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 3.474761 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.780071 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2101.017125 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 361.036043 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 17.779390 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2100.640552 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 360.974356 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064118 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.011018 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.075679 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064106 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.011016 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.075665 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 3665 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id @@ -554,17 +554,17 @@ system.cpu.l2cache.demand_misses::total 5318 # nu system.cpu.l2cache.overall_misses::cpu.inst 3167 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2151 # number of overall misses system.cpu.l2cache.overall_misses::total 5318 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 210776750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 33082500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 243859250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 115635000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 115635000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 210776750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 148717500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 359494250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 210776750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 148717500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 359494250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 235668000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35962750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 271630750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 128723250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 128723250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 235668000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 164686000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 400354000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 235668000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 164686000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 400354000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 15835 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 485 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 16320 # number of ReadReq accesses(hits+misses) @@ -589,17 +589,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.294381 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200000 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964574 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.294381 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66554.073255 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76579.861111 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67757.502084 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67268.760908 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67268.760908 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66554.073255 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69138.772664 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67599.520496 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66554.073255 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69138.772664 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67599.520496 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74413.640669 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83247.106481 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75473.951098 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74882.635253 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74882.635253 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74413.640669 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76562.529056 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75282.813088 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74413.640669 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76562.529056 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75282.813088 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -619,17 +619,17 @@ system.cpu.l2cache.demand_mshr_misses::total 5318 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3167 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2151 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5318 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 170928750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27694500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 198623250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 93817500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 93817500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 170928750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 121512000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 292440750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 170928750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 121512000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 292440750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 196043000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 30551250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 226594250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 107188750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 107188750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 196043000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137740000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 333783000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 196043000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137740000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 333783000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200000 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.890722 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.220527 # mshr miss rate for ReadReq accesses @@ -641,17 +641,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.294381 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200000 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.294381 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53971.818756 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64107.638889 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55188.455126 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54576.788831 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54576.788831 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53971.818756 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56490.934449 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54990.739000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53971.818756 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56490.934449 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54990.739000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61901.799811 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70720.486111 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62960.336205 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62355.293775 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62355.293775 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61901.799811 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64035.332404 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62764.761188 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61901.799811 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64035.332404 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62764.761188 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 16320 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 16320 # Transaction distribution @@ -678,9 +678,9 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 # system.cpu.toL2Bus.snoop_fanout::total 18172 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 9193000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 24435250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 24439500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3734000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3770500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.trans_dist::ReadReq 3599 # Transaction distribution system.membus.trans_dist::ReadResp 3599 # Transaction distribution @@ -701,9 +701,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 5318 # Request fanout histogram -system.membus.reqLayer0.occupancy 6478000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6453000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 50027750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 28232500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index fbd001a0c..9c86c55d6 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.022159 # Number of seconds simulated -sim_ticks 22159411000 # Number of ticks simulated -final_tick 22159411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.022229 # Number of seconds simulated +sim_ticks 22228749500 # Number of ticks simulated +final_tick 22228749500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 210811 # Simulator instruction rate (inst/s) -host_op_rate 210811 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55493646 # Simulator tick rate (ticks/s) -host_mem_usage 299980 # Number of bytes of host memory used -host_seconds 399.31 # Real time elapsed on the host +host_inst_rate 212613 # Simulator instruction rate (inst/s) +host_op_rate 212613 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56143360 # Simulator tick rate (ticks/s) +host_mem_usage 300388 # Number of bytes of host memory used +host_seconds 395.93 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 196160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138688 # Number of bytes read from this memory -system.physmem.bytes_read::total 334848 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 196160 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 196160 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3065 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2167 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5232 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8852221 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6258650 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15110871 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8852221 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8852221 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8852221 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6258650 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15110871 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5232 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 196032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138560 # Number of bytes read from this memory +system.physmem.bytes_read::total 334592 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 196032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 196032 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3063 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2165 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5228 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8818850 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6233369 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15052219 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8818850 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8818850 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8818850 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6233369 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15052219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5228 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5232 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5228 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 334848 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 334592 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 334848 # Total read bytes from the system interface side +system.physmem.bytesReadSys 334592 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 471 # Per bank write bursts -system.physmem.perBankRdBursts::1 289 # Per bank write bursts +system.physmem.perBankRdBursts::0 472 # Per bank write bursts +system.physmem.perBankRdBursts::1 290 # Per bank write bursts system.physmem.perBankRdBursts::2 302 # Per bank write bursts -system.physmem.perBankRdBursts::3 527 # Per bank write bursts -system.physmem.perBankRdBursts::4 218 # Per bank write bursts +system.physmem.perBankRdBursts::3 525 # Per bank write bursts +system.physmem.perBankRdBursts::4 219 # Per bank write bursts system.physmem.perBankRdBursts::5 224 # Per bank write bursts -system.physmem.perBankRdBursts::6 217 # Per bank write bursts -system.physmem.perBankRdBursts::7 287 # Per bank write bursts -system.physmem.perBankRdBursts::8 239 # Per bank write bursts -system.physmem.perBankRdBursts::9 281 # Per bank write bursts -system.physmem.perBankRdBursts::10 249 # Per bank write bursts -system.physmem.perBankRdBursts::11 253 # Per bank write bursts -system.physmem.perBankRdBursts::12 396 # Per bank write bursts +system.physmem.perBankRdBursts::6 218 # Per bank write bursts +system.physmem.perBankRdBursts::7 285 # Per bank write bursts +system.physmem.perBankRdBursts::8 238 # Per bank write bursts +system.physmem.perBankRdBursts::9 279 # Per bank write bursts +system.physmem.perBankRdBursts::10 248 # Per bank write bursts +system.physmem.perBankRdBursts::11 252 # Per bank write bursts +system.physmem.perBankRdBursts::12 398 # Per bank write bursts system.physmem.perBankRdBursts::13 338 # Per bank write bursts -system.physmem.perBankRdBursts::14 493 # Per bank write bursts -system.physmem.perBankRdBursts::15 448 # Per bank write bursts +system.physmem.perBankRdBursts::14 491 # Per bank write bursts +system.physmem.perBankRdBursts::15 449 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22159321500 # Total gap between requests +system.physmem.totGap 22228653000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5232 # Read request sizes (log2) +system.physmem.readPktSize::6 5228 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,12 +90,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3250 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1221 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 631 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1223 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 210 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -188,27 +188,27 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 866 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 383.630485 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 228.084782 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 358.284844 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 269 31.06% 31.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 171 19.75% 50.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 88 10.16% 60.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 63 7.27% 68.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 38 4.39% 72.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 33 3.81% 76.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 35 4.04% 80.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 46 5.31% 85.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 123 14.20% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 225.895164 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 361.482180 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 274 31.64% 31.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 174 20.09% 51.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 79 9.12% 60.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 66 7.62% 68.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 29 3.35% 71.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 37 4.27% 76.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 36 4.16% 80.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 45 5.20% 85.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 126 14.55% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 866 # Bytes accessed per row activation -system.physmem.totQLat 41292000 # Total ticks spent queuing -system.physmem.totMemAccLat 139392000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26160000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7892.20 # Average queueing delay per DRAM burst +system.physmem.totQLat 39875750 # Total ticks spent queuing +system.physmem.totMemAccLat 137900750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26140000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7627.34 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26642.20 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 15.11 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26377.34 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 15.05 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 15.11 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 15.05 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.12 # Data bus utilization in percentage @@ -216,70 +216,70 @@ system.physmem.busUtilRead 0.12 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4354 # Number of row buffer hits during reads +system.physmem.readRowHits 4353 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.22 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.26 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4235344.32 # Average gap between requests -system.physmem.pageHitRate 83.22 # Row buffer hit rate, read and write combined +system.physmem.avgGap 4251846.40 # Average gap between requests +system.physmem.pageHitRate 83.26 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 3137400 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 1711875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 19453200 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 19476600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1446853200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 894020490 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 12507056250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14872232415 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.367713 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 20804380500 # Time in different power states -system.physmem_0.memoryStateTime::REF 739700000 # Time in different power states +system.physmem_0.refreshEnergy 1451430240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 894518100 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 12548665500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14918939715 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.352430 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 20873521000 # Time in different power states +system.physmem_0.memoryStateTime::REF 742040000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 608242500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 606815000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3341520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1823250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 20802600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3349080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1827375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 20794800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1446853200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 920005650 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 12484262250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 14877088470 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.586927 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 20766250250 # Time in different power states -system.physmem_1.memoryStateTime::REF 739700000 # Time in different power states +system.physmem_1.refreshEnergy 1451430240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 919030095 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 12527163750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14923595340 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.561933 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 20841181500 # Time in different power states +system.physmem_1.memoryStateTime::REF 742040000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 646430250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 642887000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 16298030 # Number of BP lookups -system.cpu.branchPred.condPredicted 11843884 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 974423 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8872850 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7618799 # Number of BTB hits +system.cpu.branchPred.lookups 16323961 # Number of BP lookups +system.cpu.branchPred.condPredicted 11865379 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 978310 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9045215 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7641567 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 85.866424 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1608574 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 439 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 84.481872 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1608650 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 453 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 24142171 # DTB read hits -system.cpu.dtb.read_misses 235539 # DTB read misses +system.cpu.dtb.read_hits 24152698 # DTB read hits +system.cpu.dtb.read_misses 236585 # DTB read misses system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 24377710 # DTB read accesses -system.cpu.dtb.write_hits 7161357 # DTB write hits -system.cpu.dtb.write_misses 1208 # DTB write misses -system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_accesses 7162565 # DTB write accesses -system.cpu.dtb.data_hits 31303528 # DTB hits -system.cpu.dtb.data_misses 236747 # DTB misses -system.cpu.dtb.data_acv 3 # DTB access violations -system.cpu.dtb.data_accesses 31540275 # DTB accesses -system.cpu.itb.fetch_hits 16127186 # ITB hits -system.cpu.itb.fetch_misses 86 # ITB misses +system.cpu.dtb.read_accesses 24389283 # DTB read accesses +system.cpu.dtb.write_hits 7160578 # DTB write hits +system.cpu.dtb.write_misses 1214 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 7161792 # DTB write accesses +system.cpu.dtb.data_hits 31313276 # DTB hits +system.cpu.dtb.data_misses 237799 # DTB misses +system.cpu.dtb.data_acv 2 # DTB access violations +system.cpu.dtb.data_accesses 31551075 # DTB accesses +system.cpu.itb.fetch_hits 16159751 # ITB hits +system.cpu.itb.fetch_misses 85 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 16127272 # ITB accesses +system.cpu.itb.fetch_accesses 16159836 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,139 +293,140 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 44318823 # number of cpu cycles simulated +system.cpu.numCycles 44457500 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 16859439 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 139373095 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16298030 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9227373 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 26218422 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2029202 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 113 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2359 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 16127186 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 380559 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 44094963 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.160749 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.432020 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 16896881 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 139613933 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16323961 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9250217 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 26293708 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2036816 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 2 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 203 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2338 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 16159751 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 382144 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 44211553 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.157861 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.431266 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19653198 44.57% 44.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2660337 6.03% 50.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1339868 3.04% 53.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1948475 4.42% 58.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3047157 6.91% 64.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1303414 2.96% 67.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1381873 3.13% 71.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 894467 2.03% 73.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11866174 26.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19722112 44.61% 44.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2663068 6.02% 50.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1345508 3.04% 53.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1957580 4.43% 58.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3052640 6.90% 65.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1306785 2.96% 67.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1385791 3.13% 71.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 896674 2.03% 73.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11881395 26.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 44094963 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.367745 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.144783 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 13063435 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8246931 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19674377 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2107337 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1002883 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2678530 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12053 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 133445502 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 49010 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1002883 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 14206625 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4728440 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8922 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20521133 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3626960 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 129917938 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 71936 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1987853 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1348485 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 46206 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 95420653 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 168813407 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 161260201 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7553205 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 44211553 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.367181 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.140391 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 13076592 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8324763 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19681975 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2121490 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1006733 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2681054 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12065 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 133596496 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 48387 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1006733 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 14226924 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4752424 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9184 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20532599 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3683689 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 130038627 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 69797 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2001155 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1372929 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 55394 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 95511389 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 168978901 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 161414982 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7563918 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 26993292 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 764 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 773 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8204907 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 27105677 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8747640 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3541499 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1618929 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 112639456 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1940 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 100102500 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 120259 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 27967887 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 21886191 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1551 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 44094963 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.270157 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.096378 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 27084028 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 772 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 782 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8280120 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 27136625 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8757663 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3565364 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1670156 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 112744524 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2237 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 100145020 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 122649 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 28075682 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 21979359 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1848 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 44211553 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.265132 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.094303 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11535006 26.16% 26.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 7754470 17.59% 43.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7555421 17.13% 60.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5737104 13.01% 73.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4489384 10.18% 84.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2977388 6.75% 90.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2013844 4.57% 95.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1160432 2.63% 98.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 871914 1.98% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11585483 26.20% 26.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 7800031 17.64% 43.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7580714 17.15% 60.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5746471 13.00% 73.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4482670 10.14% 84.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2978699 6.74% 90.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2013201 4.55% 95.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1153505 2.61% 98.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 870779 1.97% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 44094963 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44211553 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 479018 20.14% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 443 0.02% 20.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 33638 1.41% 21.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 11723 0.49% 22.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1006429 42.32% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 686405 28.86% 93.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 160330 6.74% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 481856 20.25% 20.25% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 20.25% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 20.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 350 0.01% 20.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 34531 1.45% 21.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 11644 0.49% 22.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1006485 42.29% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 687304 28.88% 93.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 157568 6.62% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60895268 60.83% 60.83% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 491428 0.49% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60921013 60.83% 60.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 491088 0.49% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2836761 2.83% 64.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115534 0.12% 64.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2437739 2.44% 66.71% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 313998 0.31% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 765483 0.76% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2841000 2.84% 64.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115643 0.12% 64.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2440640 2.44% 66.71% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 314095 0.31% 67.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 766051 0.76% 67.79% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.79% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.79% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.79% # Type of FU issued @@ -447,84 +448,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.79% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.79% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.79% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24980978 24.96% 92.74% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7264985 7.26% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24991126 24.95% 92.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7264038 7.25% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 100102500 # Type of FU issued -system.cpu.iq.rate 2.258690 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2377986 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023756 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 231175586 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 131029945 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 90008848 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15622622 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9621224 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7166740 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 94135370 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8345109 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1908744 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 100145020 # Type of FU issued +system.cpu.iq.rate 2.252601 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2379738 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023763 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 231363005 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 131215529 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 90039702 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15640975 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9648680 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7175345 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 94170320 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8354431 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1902679 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 7109479 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 10719 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 42241 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2246537 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 7140427 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11100 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 42139 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2256560 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 42761 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2468 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 42760 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1687 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1002883 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3707612 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 461807 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 123638491 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 278104 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 27105677 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8747640 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1940 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 39979 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 414885 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 42241 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 554445 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 525545 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1079990 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 98729735 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 24378234 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1372765 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1006733 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3731793 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 447885 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 123749930 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 277756 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 27136625 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8757663 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2237 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 43684 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 396903 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 42139 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 560048 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 524506 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1084554 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 98770041 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 24389817 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1374979 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10997095 # number of nop insts executed -system.cpu.iew.exec_refs 31540837 # number of memory reference insts executed -system.cpu.iew.exec_branches 12532490 # Number of branches executed -system.cpu.iew.exec_stores 7162603 # Number of stores executed -system.cpu.iew.exec_rate 2.227716 # Inst execution rate -system.cpu.iew.wb_sent 97918369 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 97175588 # cumulative count of insts written-back -system.cpu.iew.wb_producers 67088120 # num instructions producing a value -system.cpu.iew.wb_consumers 95122376 # num instructions consuming a value +system.cpu.iew.exec_nop 11003169 # number of nop insts executed +system.cpu.iew.exec_refs 31551638 # number of memory reference insts executed +system.cpu.iew.exec_branches 12536484 # Number of branches executed +system.cpu.iew.exec_stores 7161821 # Number of stores executed +system.cpu.iew.exec_rate 2.221673 # Inst execution rate +system.cpu.iew.wb_sent 97959187 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 97215047 # cumulative count of insts written-back +system.cpu.iew.wb_producers 67118954 # num instructions producing a value +system.cpu.iew.wb_consumers 95176065 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.192648 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.705282 # average fanout of values written-back +system.cpu.iew.wb_rate 2.186696 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.705208 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 31736961 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 31848480 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 962705 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 39466887 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.328612 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.908948 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 966635 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 39567002 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.322720 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.905630 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 14969500 37.93% 37.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8597582 21.78% 59.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3898491 9.88% 69.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1956472 4.96% 74.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1378246 3.49% 78.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1028775 2.61% 80.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 694003 1.76% 82.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 732346 1.86% 84.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6211472 15.74% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15032687 37.99% 37.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8622118 21.79% 59.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3917590 9.90% 69.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1951695 4.93% 74.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1384336 3.50% 78.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1033619 2.61% 80.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 694183 1.75% 82.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 726057 1.84% 84.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6204717 15.68% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 39466887 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 39567002 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -570,345 +571,345 @@ system.cpu.commit.op_class_0::MemWrite 6501103 7.07% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction -system.cpu.commit.bw_lim_events 6211472 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6204717 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 156894391 # The number of ROB reads -system.cpu.rob.rob_writes 251967276 # The number of ROB writes -system.cpu.timesIdled 4539 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 223860 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 157112780 # The number of ROB reads +system.cpu.rob.rob_writes 252206838 # The number of ROB writes +system.cpu.timesIdled 4633 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 245947 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.526479 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.526479 # CPI: Total CPI of All Threads -system.cpu.ipc 1.899412 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.899412 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 133358103 # number of integer regfile reads -system.cpu.int_regfile_writes 73122882 # number of integer regfile writes -system.cpu.fp_regfile_reads 6250590 # number of floating regfile reads -system.cpu.fp_regfile_writes 6153622 # number of floating regfile writes -system.cpu.misc_regfile_reads 718773 # number of misc regfile reads +system.cpu.cpi 0.528126 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.528126 # CPI: Total CPI of All Threads +system.cpu.ipc 1.893487 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.893487 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 133407543 # number of integer regfile reads +system.cpu.int_regfile_writes 73150911 # number of integer regfile writes +system.cpu.fp_regfile_reads 6256040 # number of floating regfile reads +system.cpu.fp_regfile_writes 6161921 # number of floating regfile writes +system.cpu.misc_regfile_reads 718993 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 160 # number of replacements -system.cpu.dcache.tags.tagsinuse 1457.564933 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28680753 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2248 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12758.342082 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 159 # number of replacements +system.cpu.dcache.tags.tagsinuse 1458.668074 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28697534 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2246 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12777.174533 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1457.564933 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.355851 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.355851 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2088 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1458.668074 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.356120 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.356120 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2087 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 542 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1388 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.509766 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 57382576 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 57382576 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22187756 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22187756 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492735 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492735 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 262 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 262 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28680491 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28680491 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28680491 # number of overall hits -system.cpu.dcache.overall_hits::total 28680491 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1042 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1042 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8368 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8368 # number of WriteReq misses +system.cpu.dcache.tags.age_task_id_blocks_1024::2 541 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1390 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.509521 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 57416312 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 57416312 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22204643 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22204643 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492628 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492628 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 263 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 263 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28697271 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28697271 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28697271 # number of overall hits +system.cpu.dcache.overall_hits::total 28697271 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1023 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1023 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8475 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8475 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # 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number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 589325718 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 589325718 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 589325718 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22188798 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22188798 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9498 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9498 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9498 # number of overall misses +system.cpu.dcache.overall_misses::total 9498 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 69711000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 69711000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 550954965 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 550954965 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 85000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 85000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 620665965 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 620665965 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 620665965 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 620665965 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22205666 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22205666 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 263 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 263 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28689901 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28689901 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28689901 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28689901 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000047 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000047 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001287 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001287 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003802 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003802 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000328 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000328 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000328 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000328 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62836.612284 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62836.612284 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62601.573614 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62601.573614 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62627.600213 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62627.600213 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62627.600213 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62627.600213 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29227 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 416 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 894 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.692394 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 208 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 264 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 264 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28706769 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28706769 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28706769 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28706769 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001304 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001304 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003788 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003788 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000331 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000331 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000331 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000331 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68143.695015 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68143.695015 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65009.435398 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65009.435398 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65347.016740 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65347.016740 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65347.016740 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65347.016740 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 33287 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 426 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 78.138498 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 110 # number of writebacks -system.cpu.dcache.writebacks::total 110 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 529 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 529 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7163 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7163 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7163 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7163 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 513 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 513 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 109 # number of writebacks +system.cpu.dcache.writebacks::total 109 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 512 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 512 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6741 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6741 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7253 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7253 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7253 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7253 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 511 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 511 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1734 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1734 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # 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number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161884745 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 161884745 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161884745 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 161884745 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2245 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2245 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2245 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2245 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 38736500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 38736500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 136484495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 136484495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 83500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 83500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 175220995 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 175220995 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 175220995 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 175220995 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000267 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.003802 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.003802 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.003788 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.003788 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000078 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000078 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70473.684211 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70473.684211 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72509.656863 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72509.656863 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72044.835336 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72044.835336 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72044.835336 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72044.835336 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75805.283757 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75805.283757 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78710.781430 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78710.781430 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 83500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 83500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78049.440980 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78049.440980 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78049.440980 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78049.440980 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 9583 # number of replacements -system.cpu.icache.tags.tagsinuse 1600.631053 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 16112652 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 11519 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1398.789131 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 9845 # number of replacements +system.cpu.icache.tags.tagsinuse 1600.510636 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 16144798 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 11783 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1370.177204 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1600.631053 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.781558 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.781558 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1936 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 763 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 930 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 32265889 # Number of tag accesses -system.cpu.icache.tags.data_accesses 32265889 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 16112652 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 16112652 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 16112652 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 16112652 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 16112652 # number of overall hits -system.cpu.icache.overall_hits::total 16112652 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14533 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14533 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14533 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14533 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14533 # number of overall misses -system.cpu.icache.overall_misses::total 14533 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 419570250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 419570250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 419570250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 419570250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 419570250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 419570250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 16127185 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 16127185 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 16127185 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 16127185 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 16127185 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 16127185 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000901 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000901 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000901 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000901 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000901 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000901 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28870.174775 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28870.174775 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28870.174775 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28870.174775 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28870.174775 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28870.174775 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 196 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1600.510636 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.781499 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.781499 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1938 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 760 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 936 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.946289 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 32331281 # Number of tag accesses +system.cpu.icache.tags.data_accesses 32331281 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 16144798 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 16144798 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 16144798 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 16144798 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 16144798 # number of overall hits +system.cpu.icache.overall_hits::total 16144798 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14951 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14951 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14951 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14951 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14951 # number of overall misses +system.cpu.icache.overall_misses::total 14951 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 446766000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 446766000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 446766000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 446766000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 446766000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 446766000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 16159749 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 16159749 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 16159749 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 16159749 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 16159749 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 16159749 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000925 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000925 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000925 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000925 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000925 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000925 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29882.014581 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 29882.014581 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 29882.014581 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 29882.014581 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 29882.014581 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 29882.014581 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 502 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 39.200000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 55.777778 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3014 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3014 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3014 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3014 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3014 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3014 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11519 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 11519 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 11519 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 11519 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 11519 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 11519 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 306551250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 306551250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 306551250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 306551250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 306551250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 306551250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000714 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000714 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000714 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000714 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000714 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000714 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26612.661689 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26612.661689 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26612.661689 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 26612.661689 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26612.661689 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 26612.661689 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3168 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3168 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3168 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3168 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3168 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3168 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11783 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 11783 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 11783 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 11783 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 11783 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 11783 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 332403750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 332403750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 332403750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 332403750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 332403750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 332403750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000729 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000729 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000729 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000729 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000729 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000729 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28210.451498 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28210.451498 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28210.451498 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 28210.451498 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28210.451498 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 28210.451498 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2401.991328 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8524 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3591 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.373712 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2407.331968 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8790 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3587 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.450516 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.703660 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.347225 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 376.940444 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 17.698797 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2011.289043 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 378.344128 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000540 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061259 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.011503 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.073303 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3591 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 915 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2425 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.109589 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 116342 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 116342 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 8454 # number of ReadReq hits +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061380 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.011546 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.073466 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3587 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 911 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2 # 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Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 12032 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 110 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1735 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1735 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23038 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4606 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27644 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 888128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 12295 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 12295 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 109 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1734 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1734 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23566 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4601 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 28167 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 754112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 904832 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 13877 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 14138 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 13877 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 14138 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 13877 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7048500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 14138 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7178000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 17856250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 18279750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3547750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3635750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 3523 # Transaction distribution -system.membus.trans_dist::ReadResp 3523 # Transaction distribution -system.membus.trans_dist::ReadExReq 1709 # Transaction distribution -system.membus.trans_dist::ReadExResp 1709 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10464 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10464 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334848 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 334848 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 3520 # Transaction distribution +system.membus.trans_dist::ReadResp 3520 # Transaction distribution +system.membus.trans_dist::ReadExReq 1708 # Transaction distribution +system.membus.trans_dist::ReadExResp 1708 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10456 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10456 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334592 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 334592 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5232 # Request fanout histogram +system.membus.snoop_fanout::samples 5228 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5232 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5228 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5232 # Request fanout histogram -system.membus.reqLayer0.occupancy 6529000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5228 # Request fanout histogram +system.membus.reqLayer0.occupancy 6467500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 48920250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 27502000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index 4e099442b..85445221a 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.118729 # Number of seconds simulated -sim_ticks 118729316000 # Number of ticks simulated -final_tick 118729316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 118729316500 # Number of ticks simulated +final_tick 118729316500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1660785 # Simulator instruction rate (inst/s) -host_op_rate 1660785 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2145562848 # Simulator tick rate (ticks/s) -host_mem_usage 293264 # Number of bytes of host memory used -host_seconds 55.34 # Real time elapsed on the host +host_inst_rate 1507080 # Simulator instruction rate (inst/s) +host_op_rate 1507080 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1946992285 # Simulator tick rate (ticks/s) +host_mem_usage 297820 # Number of bytes of host memory used +host_seconds 60.98 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,29 +29,6 @@ system.physmem.bw_inst_read::total 1412827 # In system.physmem.bw_total::cpu.inst 1412827 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1155704 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2568532 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 3043 # Transaction distribution -system.membus.trans_dist::ReadResp 3043 # Transaction distribution -system.membus.trans_dist::ReadExReq 1722 # Transaction distribution -system.membus.trans_dist::ReadExResp 1722 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9530 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 9530 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 304960 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 304960 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 4765 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4765 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 4765 # Request fanout histogram -system.membus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 42885000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -86,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 237458632 # number of cpu cycles simulated +system.cpu.numCycles 237458633 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 91903056 # Number of instructions committed @@ -105,7 +82,7 @@ system.cpu.num_mem_refs 26497334 # nu system.cpu.num_load_insts 19996208 # Number of load instructions system.cpu.num_store_insts 6501126 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 237458632 # Number of busy cycles +system.cpu.num_busy_cycles 237458633 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 10240685 # Number of branches fetched @@ -144,13 +121,122 @@ system.cpu.op_class::MemWrite 6501126 7.07% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91903089 # Class of executed instruction +system.cpu.dcache.tags.replacements 157 # number of replacements +system.cpu.dcache.tags.tagsinuse 1442.043377 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26495078 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11918.613585 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1442.043377 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.352061 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2066 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 173 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 487 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1372 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.504395 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 52996825 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 52996825 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6499355 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26495078 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26495078 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26495078 # number of overall hits +system.cpu.dcache.overall_hits::total 26495078 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 475 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 475 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1748 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1748 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2223 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses +system.cpu.dcache.overall_misses::total 2223 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 23899000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 23899000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 95048000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 95048000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 118947000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 118947000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 118947000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 118947000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000269 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50313.684211 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50313.684211 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54375.286041 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54375.286041 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53507.422402 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53507.422402 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 107 # number of writebacks +system.cpu.dcache.writebacks::total 107 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23186500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23186500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92426000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 92426000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 115612500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 115612500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 115612500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 115612500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48813.684211 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48813.684211 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52875.286041 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52875.286041 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52007.422402 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52007.422402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52007.422402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52007.422402 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 6681 # number of replacements -system.cpu.icache.tags.tagsinuse 1418.052773 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1418.052759 # Cycle average of tags in use system.cpu.icache.tags.total_refs 91894580 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 8510 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 10798.423032 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1418.052773 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1418.052759 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.692409 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.692409 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id @@ -174,12 +260,12 @@ system.cpu.icache.demand_misses::cpu.inst 8510 # n system.cpu.icache.demand_misses::total 8510 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 8510 # number of overall misses system.cpu.icache.overall_misses::total 8510 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 220712000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 220712000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 220712000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 220712000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 220712000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 220712000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 220712500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 220712500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 220712500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 220712500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 220712500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 220712500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 91903090 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 91903090 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 91903090 # number of demand (read+write) accesses @@ -192,12 +278,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25935.605170 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25935.605170 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25935.605170 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25935.605170 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25935.605170 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25935.605170 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25935.663925 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25935.663925 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25935.663925 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25935.663925 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25935.663925 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25935.663925 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -212,34 +298,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 8510 system.cpu.icache.demand_mshr_misses::total 8510 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 8510 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 8510 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 203692000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 203692000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 203692000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 203692000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 203692000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 203692000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 207947500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 207947500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 207947500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 207947500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 207947500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 207947500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000093 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000093 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23935.605170 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23935.605170 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24435.663925 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24435.663925 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24435.663925 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24435.663925 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24435.663925 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24435.663925 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2074.070560 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2074.070538 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 5956 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3109 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.915729 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.795178 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1705.018003 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 351.257379 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 17.795177 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1705.017985 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 351.257376 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052033 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.010720 # Average percentage of cache occupancy @@ -277,17 +363,17 @@ system.cpu.l2cache.demand_misses::total 4765 # nu system.cpu.l2cache.overall_misses::cpu.inst 2621 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4765 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 136292000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21944000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 158236000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 89544000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 89544000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 136292000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 111488000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 247780000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 136292000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 111488000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 247780000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 137603000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22155000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 159758000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 90405000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 90405000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 137603000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 112560000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 250163000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 137603000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 112560000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 250163000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 8510 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 8985 # number of ReadReq accesses(hits+misses) @@ -312,17 +398,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.443958 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.307991 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.443958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.190767 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.164312 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.190767 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.104932 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.190767 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.104932 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -342,17 +428,17 @@ system.cpu.l2cache.demand_mshr_misses::total 4765 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2621 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4765 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104840000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16880000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 121720000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 68880000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 68880000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104840000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 85760000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 190600000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104840000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 85760000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 190600000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 106150500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17091000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 123241500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69741000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69741000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106150500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86832000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 192982500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106150500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86832000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 192982500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.338676 # mshr miss rate for ReadReq accesses @@ -364,127 +450,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.443958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.443958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1442.043392 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26495078 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11918.613585 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1442.043392 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.352061 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2066 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 173 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 487 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1372 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.504395 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 52996825 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 52996825 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6499355 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26495078 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26495078 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26495078 # number of overall hits -system.cpu.dcache.overall_hits::total 26495078 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 475 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 475 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1748 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1748 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2223 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses -system.cpu.dcache.overall_misses::total 2223 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 23899000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 23899000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 95048000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 95048000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 118947000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 118947000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 118947000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 118947000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000269 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50313.684211 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50313.684211 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54375.286041 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54375.286041 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 53507.422402 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 53507.422402 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 107 # number of writebacks -system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22949000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 22949000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 91552000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 91552000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114501000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 114501000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114501000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 114501000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48313.684211 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48313.684211 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52375.286041 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52375.286041 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 8985 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 8985 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution @@ -514,5 +491,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 12765000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3334500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 3043 # Transaction distribution +system.membus.trans_dist::ReadResp 3043 # Transaction distribution +system.membus.trans_dist::ReadExReq 1722 # Transaction distribution +system.membus.trans_dist::ReadExResp 1722 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9530 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 9530 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 304960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 304960 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 4765 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 4765 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 4765 # Request fanout histogram +system.membus.reqLayer0.occupancy 4765500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 23825500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |