diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-01-31 07:49:16 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-01-31 07:49:16 -0500 |
| commit | fce3433b2eb764d9519ffbc4c7e95049f3200ba3 (patch) | |
| tree | 26e90c5190c4751532683d1f4b5bf6094e6ba4b7 /tests/long/se/70.twolf/ref/alpha | |
| parent | c4898b15bcf5458e35f17cb0c3b4185cec0081aa (diff) | |
| download | gem5-fce3433b2eb764d9519ffbc4c7e95049f3200ba3.tar.xz | |
stats: Update stats for regressions using SimpleDDR3
This patch updates the regression stats to reflect that they are using
the SimpleDDR3 controller by default.
Diffstat (limited to 'tests/long/se/70.twolf/ref/alpha')
| -rw-r--r-- | tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt | 514 | ||||
| -rw-r--r-- | tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt | 1159 |
2 files changed, 837 insertions, 836 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 2877a6d58..7e4c9be17 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.041615 # Number of seconds simulated -sim_ticks 41615049000 # Number of ticks simulated -final_tick 41615049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.041622 # Number of seconds simulated +sim_ticks 41622221000 # Number of ticks simulated +final_tick 41622221000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 92405 # Simulator instruction rate (inst/s) -host_op_rate 92405 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41842312 # Simulator tick rate (ticks/s) -host_mem_usage 276220 # Number of bytes of host memory used -host_seconds 994.57 # Real time elapsed on the host +host_inst_rate 156492 # Simulator instruction rate (inst/s) +host_op_rate 156492 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 70874179 # Simulator tick rate (ticks/s) +host_mem_usage 228076 # Number of bytes of host memory used +host_seconds 587.27 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 178816 # Nu system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 4296907 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3297269 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7594176 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4296907 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4296907 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4296907 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3297269 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7594176 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 4296167 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3296701 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7592867 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4296167 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4296167 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4296167 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3296701 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7592867 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 4938 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 4938 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 316032 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 349 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 313 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 229 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 290 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 250 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 283 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 352 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 383 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 306 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 282 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 254 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 283 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 313 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 363 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 356 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 332 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 311 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 344 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 302 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 293 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 259 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 224 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 279 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 294 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 290 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 273 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 301 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 345 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 351 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 357 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 333 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 382 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 41614997000 # Total gap between requests +system.physmem.totGap 41622168000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 3467 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1008 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 421 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3236 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 433 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -164,56 +164,56 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 17845427 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 106827427 # Sum of mem lat for all requests -system.physmem.totBusLat 19752000 # Total cycles spent in databus access -system.physmem.totBankLat 69230000 # Total cycles spent in bank access -system.physmem.avgQLat 3613.90 # Average queueing delay per request -system.physmem.avgBankLat 14019.85 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 21633.74 # Average memory access latency +system.physmem.totQLat 23375922 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 122137172 # Sum of mem lat for all requests +system.physmem.totBusLat 24690000 # Total cycles spent in databus access +system.physmem.totBankLat 74071250 # Total cycles spent in bank access +system.physmem.avgQLat 4733.88 # Average queueing delay per request +system.physmem.avgBankLat 15000.25 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 24734.14 # Average memory access latency system.physmem.avgRdBW 7.59 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 7.59 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.05 # Data bus utilization in percentage +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4457 # Number of row buffer hits during reads +system.physmem.readRowHits 4243 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.26 # Row buffer hit rate for reads +system.physmem.readRowHitRate 85.93 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 8427500.41 # Average gap between requests -system.cpu.branchPred.lookups 13412629 # Number of BP lookups -system.cpu.branchPred.condPredicted 9650146 # Number of conditional branches predicted +system.physmem.avgGap 8428952.61 # Average gap between requests +system.cpu.branchPred.lookups 13412628 # Number of BP lookups +system.cpu.branchPred.condPredicted 9650145 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 4269214 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 7424481 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 7424480 # Number of BTB lookups system.cpu.branchPred.BTBHits 3768497 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 50.757716 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 50.757723 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1029619 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 126 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 19996253 # DTB read hits +system.cpu.dtb.read_hits 19996247 # DTB read hits system.cpu.dtb.read_misses 10 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 19996263 # DTB read accesses -system.cpu.dtb.write_hits 6501863 # DTB write hits +system.cpu.dtb.read_accesses 19996257 # DTB read accesses +system.cpu.dtb.write_hits 6501860 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6501886 # DTB write accesses -system.cpu.dtb.data_hits 26498116 # DTB hits +system.cpu.dtb.write_accesses 6501883 # DTB write accesses +system.cpu.dtb.data_hits 26498107 # DTB hits system.cpu.dtb.data_misses 33 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 26498149 # DTB accesses -system.cpu.itb.fetch_hits 9956935 # ITB hits +system.cpu.dtb.data_accesses 26498140 # DTB accesses +system.cpu.itb.fetch_hits 9956943 # ITB hits system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 9956984 # ITB accesses +system.cpu.itb.fetch_accesses 9956992 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -227,18 +227,18 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 83230099 # number of cpu cycles simulated +system.cpu.numCycles 83244443 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 5905664 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 7506965 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 73570547 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedNotTaken 7506964 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 73570549 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 136146019 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 136146021 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 2206128 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 8058016 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 38521872 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 38521870 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 26722393 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 3469296 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 799060 # Number of Branches Incorrectly Predicted As Not Taken). @@ -249,12 +249,12 @@ system.cpu.execution_unit.executions 57404029 # Nu system.cpu.mult_div_unit.multiplies 458253 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 82970257 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 82970167 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 10685 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7622365 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 75607734 # Number of cycles cpu stages are processed. -system.cpu.activity 90.841817 # Percentage of cycles cpu is active +system.cpu.timesIdled 10691 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7636719 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 75607724 # Number of cycles cpu stages are processed. +system.cpu.activity 90.826152 # Percentage of cycles cpu is active system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed @@ -266,72 +266,72 @@ system.cpu.committedInsts 91903056 # Nu system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) -system.cpu.cpi 0.905629 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.905785 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.905629 # CPI: Total CPI of All Threads -system.cpu.ipc 1.104205 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.905785 # CPI: Total CPI of All Threads +system.cpu.ipc 1.104014 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.104205 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 27549736 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 55680363 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 66.899311 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 33978401 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 49251698 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 59.175345 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33378776 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 49851323 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 59.895787 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65203595 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 18026504 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.658636 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 29370403 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 53859696 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.711801 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.104014 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 27564085 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 55680358 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 66.887778 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 33992749 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 49251694 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 59.165143 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 33393108 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 49851335 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 59.885481 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65217942 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 18026501 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.654900 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 29384711 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 53859732 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.700694 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 7635 # number of replacements -system.cpu.icache.tagsinuse 1492.730683 # Cycle average of tags in use -system.cpu.icache.total_refs 9945572 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1492.649363 # Cycle average of tags in use +system.cpu.icache.total_refs 9945578 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 9520 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1044.702941 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1044.703571 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1492.730683 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.728872 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.728872 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 9945572 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 9945572 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 9945572 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 9945572 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 9945572 # number of overall hits -system.cpu.icache.overall_hits::total 9945572 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11363 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11363 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11363 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11363 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11363 # number of overall misses -system.cpu.icache.overall_misses::total 11363 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 253418000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 253418000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 253418000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 253418000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 253418000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 253418000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9956935 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9956935 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9956935 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9956935 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9956935 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9956935 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1492.649363 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.728833 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.728833 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 9945578 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 9945578 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 9945578 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 9945578 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 9945578 # number of overall hits +system.cpu.icache.overall_hits::total 9945578 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11365 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11365 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11365 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11365 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11365 # number of overall misses +system.cpu.icache.overall_misses::total 11365 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 259189500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 259189500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 259189500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 259189500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 259189500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 259189500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9956943 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9956943 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9956943 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9956943 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9956943 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9956943 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001141 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001141 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001141 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.001141 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001141 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001141 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22302.032914 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22302.032914 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22302.032914 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22302.032914 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22302.032914 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22302.032914 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22805.939287 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22805.939287 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22805.939287 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22805.939287 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22805.939287 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22805.939287 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -340,50 +340,50 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 7 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1843 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1843 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1843 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1843 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1843 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1843 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1845 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1845 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1845 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1845 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1845 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 204186500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 204186500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 209613500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 209613500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 209613500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 209613500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 209613500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 209613500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000956 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000956 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21448.161765 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21448.161765 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21448.161765 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21448.161765 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21448.161765 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21448.161765 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22018.224790 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22018.224790 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22018.224790 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22018.224790 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22018.224790 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22018.224790 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2190.387059 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2190.263467 # Cycle average of tags in use system.cpu.l2cache.total_refs 6793 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.069775 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.839462 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1821.429033 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 351.118565 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 17.839012 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1821.325234 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 351.099221 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000544 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.055586 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.055582 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.010715 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.066845 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.066842 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 6726 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6779 # number of ReadReq hits @@ -408,17 +408,17 @@ system.cpu.l2cache.demand_misses::total 4938 # nu system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4938 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 127130500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21966500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 149097000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 79600500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 79600500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 127130500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 101567000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 228697500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 127130500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 101567000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 228697500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 132557500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 24069000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 156626500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84092000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 84092000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 132557500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 108161000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 240718500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 132557500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 108161000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 240718500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 9520 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 9995 # number of ReadReq accesses(hits+misses) @@ -443,17 +443,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.420506 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293487 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.420506 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 45501.252684 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52053.317536 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 46361.007463 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46225.609756 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46225.609756 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 45501.252684 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47372.667910 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 46313.791009 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 45501.252684 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47372.667910 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 46313.791009 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47443.629205 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57035.545024 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 48702.269900 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48833.914053 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48833.914053 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47443.629205 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50448.227612 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 48748.177400 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47443.629205 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50448.227612 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 48748.177400 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -473,17 +473,17 @@ system.cpu.l2cache.demand_mshr_misses::total 4938 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 91774816 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16652177 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 108426993 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 58348895 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 58348895 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 91774816 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 75001072 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 166775888 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 91774816 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 75001072 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 166775888 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 97843336 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18812201 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 116655537 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63127136 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63127136 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97843336 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 81939337 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 179782673 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97843336 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 81939337 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 179782673 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321761 # mshr miss rate for ReadReq accesses @@ -495,51 +495,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.420506 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.420506 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32847.106657 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39460.135071 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33714.861007 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33884.375726 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33884.375726 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32847.106657 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34981.843284 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33773.974889 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32847.106657 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34981.843284 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33773.974889 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35019.089477 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44578.675355 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36273.487873 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36659.196283 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36659.196283 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35019.089477 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38217.974347 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36407.993722 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35019.089477 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38217.974347 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36407.993722 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1441.892023 # Cycle average of tags in use -system.cpu.dcache.total_refs 26488629 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1441.801688 # Cycle average of tags in use +system.cpu.dcache.total_refs 26488625 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11915.712551 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11915.710751 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1441.892023 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.352024 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.352024 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 1441.801688 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.352002 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.352002 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 19995623 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 19995623 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6493006 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6493006 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26488629 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26488629 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26488629 # number of overall hits -system.cpu.dcache.overall_hits::total 26488629 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 6493002 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6493002 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26488625 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26488625 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26488625 # number of overall hits +system.cpu.dcache.overall_hits::total 26488625 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 575 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 575 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8097 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8097 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 8672 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 8672 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 8672 # number of overall misses -system.cpu.dcache.overall_misses::total 8672 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 28721000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 28721000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 329862500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 329862500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 358583500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 358583500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 358583500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 358583500 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 8101 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8101 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 8676 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8676 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 8676 # number of overall misses +system.cpu.dcache.overall_misses::total 8676 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31383500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31383500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 345698500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 345698500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 377082000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 377082000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 377082000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 377082000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -550,25 +550,25 @@ system.cpu.dcache.overall_accesses::cpu.data 26497301 system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000029 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001245 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001245 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001246 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001246 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000327 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000327 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000327 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000327 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49949.565217 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 49949.565217 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40738.853897 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 40738.853897 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41349.573339 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41349.573339 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41349.573339 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41349.573339 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 11994 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54580 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54580 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42673.558820 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42673.558820 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 43462.655602 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 43462.655602 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 43462.655602 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 43462.655602 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 13684 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 830 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 822 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.450602 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.647202 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -576,12 +576,12 @@ system.cpu.dcache.writebacks::writebacks 107 # nu system.cpu.dcache.writebacks::total 107 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 100 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 100 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6349 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6349 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6449 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6449 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6449 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6449 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6353 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6353 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6453 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6453 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6453 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6453 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses @@ -590,14 +590,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22990000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 22990000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 81618000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 81618000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 104608000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 104608000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 104608000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 104608000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25092500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 25092500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86109500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 86109500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 111202000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 111202000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 111202000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 111202000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -606,14 +606,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48400 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48400 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46692.219680 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46692.219680 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 47057.130004 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 47057.130004 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 47057.130004 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 47057.130004 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52826.315789 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52826.315789 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49261.727689 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49261.727689 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50023.391813 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 50023.391813 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50023.391813 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 50023.391813 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 32c2b95d3..c7256bad9 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023378 # Number of seconds simulated -sim_ticks 23378067000 # Number of ticks simulated -final_tick 23378067000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023427 # Number of seconds simulated +sim_ticks 23426793000 # Number of ticks simulated +final_tick 23426793000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125836 # Simulator instruction rate (inst/s) -host_op_rate 125836 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34946651 # Simulator tick rate (ticks/s) -host_mem_usage 277248 # Number of bytes of host memory used -host_seconds 668.96 # Real time elapsed on the host +host_inst_rate 213464 # Simulator instruction rate (inst/s) +host_op_rate 213464 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59405864 # Simulator tick rate (ticks/s) +host_mem_usage 230136 # Number of bytes of host memory used +host_seconds 394.35 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 196096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 195968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138624 # Number of bytes read from this memory system.physmem.bytes_read::total 334592 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 196096 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 196096 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3064 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2164 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 195968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 195968 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3062 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2166 # Number of read requests responded to by this memory system.physmem.num_reads::total 5228 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8388033 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5924185 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14312218 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8388033 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8388033 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8388033 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5924185 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 14312218 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 8365123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5917327 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14282450 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8365123 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8365123 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8365123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5917327 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 14282450 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 5228 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 5228 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 334592 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 367 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 340 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 253 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 316 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 255 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 295 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 373 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 401 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 320 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 300 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 275 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 288 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 326 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 385 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 382 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 352 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 325 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 362 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 326 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 312 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 285 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 246 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 295 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 308 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 299 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 282 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 315 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 365 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 376 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 379 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 355 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 398 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 23377961000 # Total gap between requests +system.physmem.totGap 23426687000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,12 +98,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 3190 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1567 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 365 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 92 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1385 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 549 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -164,56 +164,56 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 21787213 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 116311213 # Sum of mem lat for all requests -system.physmem.totBusLat 20912000 # Total cycles spent in databus access -system.physmem.totBankLat 73612000 # Total cycles spent in bank access -system.physmem.avgQLat 4167.41 # Average queueing delay per request -system.physmem.avgBankLat 14080.34 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22247.75 # Average memory access latency -system.physmem.avgRdBW 14.31 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 28657456 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 133887456 # Sum of mem lat for all requests +system.physmem.totBusLat 26140000 # Total cycles spent in databus access +system.physmem.totBankLat 79090000 # Total cycles spent in bank access +system.physmem.avgQLat 5481.53 # Average queueing delay per request +system.physmem.avgBankLat 15128.16 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 25609.69 # Average memory access latency +system.physmem.avgRdBW 14.28 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 14.31 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 14.28 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.09 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.11 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.01 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4677 # Number of row buffer hits during reads +system.physmem.readRowHits 4452 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.46 # Row buffer hit rate for reads +system.physmem.readRowHitRate 85.16 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4471683.44 # Average gap between requests -system.cpu.branchPred.lookups 14833517 # Number of BP lookups -system.cpu.branchPred.condPredicted 10762267 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 917019 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8075874 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6944735 # Number of BTB hits +system.physmem.avgGap 4481003.63 # Average gap between requests +system.cpu.branchPred.lookups 14862899 # Number of BP lookups +system.cpu.branchPred.condPredicted 10784279 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 925607 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8448126 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6969256 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 85.993603 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1466052 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3147 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 82.494698 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1468807 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3068 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 23102664 # DTB read hits -system.cpu.dtb.read_misses 192481 # DTB read misses +system.cpu.dtb.read_hits 23133213 # DTB read hits +system.cpu.dtb.read_misses 193272 # DTB read misses system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 23295145 # DTB read accesses -system.cpu.dtb.write_hits 7068005 # DTB write hits -system.cpu.dtb.write_misses 1092 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 7069097 # DTB write accesses -system.cpu.dtb.data_hits 30170669 # DTB hits -system.cpu.dtb.data_misses 193573 # DTB misses -system.cpu.dtb.data_acv 2 # DTB access violations -system.cpu.dtb.data_accesses 30364242 # DTB accesses -system.cpu.itb.fetch_hits 14708082 # ITB hits -system.cpu.itb.fetch_misses 96 # ITB misses +system.cpu.dtb.read_accesses 23326485 # DTB read accesses +system.cpu.dtb.write_hits 7072266 # DTB write hits +system.cpu.dtb.write_misses 1114 # DTB write misses +system.cpu.dtb.write_acv 4 # DTB write access violations +system.cpu.dtb.write_accesses 7073380 # DTB write accesses +system.cpu.dtb.data_hits 30205479 # DTB hits +system.cpu.dtb.data_misses 194386 # DTB misses +system.cpu.dtb.data_acv 6 # DTB access violations +system.cpu.dtb.data_accesses 30399865 # DTB accesses +system.cpu.itb.fetch_hits 14751258 # ITB hits +system.cpu.itb.fetch_misses 97 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14708178 # ITB accesses +system.cpu.itb.fetch_accesses 14751355 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -227,237 +227,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 46756135 # number of cpu cycles simulated +system.cpu.numCycles 46853587 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15430530 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 126815242 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14833517 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 8410787 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22106787 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4454905 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5569972 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 51 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2009 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14708082 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 322729 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46612836 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.720608 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.376239 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15478226 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 127086204 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14862899 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 8438063 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22152522 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4487790 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5536762 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 83 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2724 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 14751258 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 326039 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46698540 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.721417 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.376215 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24506049 52.57% 52.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2362426 5.07% 57.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1191299 2.56% 60.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1739407 3.73% 63.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2752944 5.91% 69.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1147923 2.46% 72.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1216668 2.61% 74.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 768362 1.65% 76.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10927758 23.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24546018 52.56% 52.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2363136 5.06% 57.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1191999 2.55% 60.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1747286 3.74% 63.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2758963 5.91% 69.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1151332 2.47% 72.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1219220 2.61% 74.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 775308 1.66% 76.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10945278 23.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46612836 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.317253 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.712270 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17256308 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4263506 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20503237 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1097959 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3491826 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2511850 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12028 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 123858190 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 32546 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3491826 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18399179 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 964925 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7287 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20435541 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3314078 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 121046582 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 48 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 399182 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2434828 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 88894409 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 157311905 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 147648223 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9663682 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 46698540 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.317220 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.712411 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17303274 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4237001 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20547487 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1094236 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3516542 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2516790 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12060 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 124092936 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 31896 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3516542 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18446150 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 953596 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7276 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20476535 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3298441 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 121253427 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 58 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 399455 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2423561 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 89048453 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 157563733 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 147863840 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9699893 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 20467048 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 739 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 732 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8795383 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 25343096 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8237940 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2594464 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 920924 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 105370947 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1446 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 96530679 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 178191 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 20721356 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15565520 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1057 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46612836 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.070903 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.875751 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 20621092 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 715 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 706 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8762124 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 25385907 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8248290 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2586709 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 908922 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 105520430 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1810 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 96627173 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 179301 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 20866432 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15656081 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1421 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46698540 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.069169 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.876778 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12074665 25.90% 25.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 9351108 20.06% 45.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8402793 18.03% 63.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6288710 13.49% 77.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4905546 10.52% 88.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2859533 6.13% 94.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1729691 3.71% 97.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 796460 1.71% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 204330 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12145462 26.01% 26.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9347287 20.02% 46.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8392983 17.97% 64.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6295181 13.48% 77.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4922186 10.54% 88.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2865412 6.14% 94.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1725444 3.69% 97.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 796771 1.71% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 207814 0.45% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46612836 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46698540 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 190047 12.12% 12.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 12.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 12.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 203 0.01% 12.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 7055 0.45% 12.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 5882 0.38% 12.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 842974 53.75% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 444058 28.31% 95.01% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 78249 4.99% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 188040 12.01% 12.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 12.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 12.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 192 0.01% 12.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 7132 0.46% 12.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 5753 0.37% 12.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 842663 53.82% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 443560 28.33% 95.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 78346 5.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58717725 60.83% 60.83% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 479593 0.50% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58768195 60.82% 60.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 479903 0.50% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2796739 2.90% 64.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115257 0.12% 64.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2386885 2.47% 66.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 311006 0.32% 67.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 760000 0.79% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23812199 24.67% 92.59% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7150949 7.41% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2800414 2.90% 64.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115399 0.12% 64.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2387049 2.47% 66.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 311103 0.32% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 759957 0.79% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23849343 24.68% 92.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7155484 7.41% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 96530679 # Type of FU issued -system.cpu.iq.rate 2.064556 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1568468 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016248 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 226318050 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 117401953 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87051166 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15102803 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 8726703 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7059295 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90117667 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7981473 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1519109 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 96627173 # Type of FU issued +system.cpu.iq.rate 2.062322 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1565686 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016203 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 226574505 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 117655638 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87117393 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15123368 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 8767383 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7066303 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90201258 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7991594 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1516780 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5346898 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 18469 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 35032 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1736837 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5389709 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 18571 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34473 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1747187 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10557 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1512 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10549 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1581 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3491826 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 132020 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18316 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 115597875 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 364987 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 25343096 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8237940 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1446 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3142 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 30 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 35032 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 529110 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 494336 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1023446 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 95309066 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23295605 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1221613 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3516542 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 131686 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 18180 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 115763317 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 371525 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 25385907 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8248290 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1810 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2912 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 33 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 34473 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 538490 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 495901 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1034391 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 95392807 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23326978 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1234366 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10225482 # number of nop insts executed -system.cpu.iew.exec_refs 30364899 # number of memory reference insts executed -system.cpu.iew.exec_branches 12021435 # Number of branches executed -system.cpu.iew.exec_stores 7069294 # Number of stores executed -system.cpu.iew.exec_rate 2.038429 # Inst execution rate -system.cpu.iew.wb_sent 94627849 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 94110461 # cumulative count of insts written-back -system.cpu.iew.wb_producers 64468484 # num instructions producing a value -system.cpu.iew.wb_consumers 89853069 # num instructions consuming a value +system.cpu.iew.exec_nop 10241077 # number of nop insts executed +system.cpu.iew.exec_refs 30400564 # number of memory reference insts executed +system.cpu.iew.exec_branches 12029650 # Number of branches executed +system.cpu.iew.exec_stores 7073586 # Number of stores executed +system.cpu.iew.exec_rate 2.035977 # Inst execution rate +system.cpu.iew.wb_sent 94705450 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 94183696 # cumulative count of insts written-back +system.cpu.iew.wb_producers 64505139 # num instructions producing a value +system.cpu.iew.wb_consumers 89892889 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.012794 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717488 # average fanout of values written-back +system.cpu.iew.wb_rate 2.010170 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717578 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23695922 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 23861264 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 905358 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43121010 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.131283 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.747044 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 913934 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43181998 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.128272 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.745397 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16684738 38.69% 38.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9903892 22.97% 61.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4485087 10.40% 72.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2259914 5.24% 77.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1605498 3.72% 81.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1123100 2.60% 83.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 719913 1.67% 85.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 818667 1.90% 87.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5520201 12.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16729209 38.74% 38.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9919354 22.97% 61.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4482137 10.38% 72.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2267062 5.25% 77.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1606601 3.72% 81.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1122793 2.60% 83.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 721285 1.67% 85.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 818294 1.89% 87.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5515263 12.77% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43121010 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43181998 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -468,192 +469,192 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5520201 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5515263 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 153198746 # The number of ROB reads -system.cpu.rob.rob_writes 234713539 # The number of ROB writes -system.cpu.timesIdled 5103 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 143299 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 153430014 # The number of ROB reads +system.cpu.rob.rob_writes 235069144 # The number of ROB writes +system.cpu.timesIdled 5265 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 155047 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.555432 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.555432 # CPI: Total CPI of All Threads -system.cpu.ipc 1.800399 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.800399 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 129015669 # number of integer regfile reads -system.cpu.int_regfile_writes 70499119 # number of integer regfile writes -system.cpu.fp_regfile_reads 6185969 # number of floating regfile reads -system.cpu.fp_regfile_writes 6040722 # number of floating regfile writes -system.cpu.misc_regfile_reads 714490 # number of misc regfile reads +system.cpu.cpi 0.556590 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.556590 # CPI: Total CPI of All Threads +system.cpu.ipc 1.796655 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.796655 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 129123035 # number of integer regfile reads +system.cpu.int_regfile_writes 70557439 # number of integer regfile writes +system.cpu.fp_regfile_reads 6190540 # number of floating regfile reads +system.cpu.fp_regfile_writes 6048182 # number of floating regfile writes +system.cpu.misc_regfile_reads 714455 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 9535 # number of replacements -system.cpu.icache.tagsinuse 1597.711655 # Cycle average of tags in use -system.cpu.icache.total_refs 14694095 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 11468 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1281.312783 # Average number of references to valid blocks. +system.cpu.icache.replacements 9558 # number of replacements +system.cpu.icache.tagsinuse 1591.672723 # Cycle average of tags in use +system.cpu.icache.total_refs 14737290 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 11492 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1282.395580 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1597.711655 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.780133 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.780133 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14694095 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14694095 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14694095 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14694095 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14694095 # number of overall hits -system.cpu.icache.overall_hits::total 14694095 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13987 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 13987 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 13987 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13987 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13987 # number of overall misses -system.cpu.icache.overall_misses::total 13987 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 308160500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 308160500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 308160500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 308160500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 308160500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 308160500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14708082 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14708082 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14708082 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14708082 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14708082 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14708082 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000951 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000951 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000951 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000951 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000951 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000951 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22031.922499 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22031.922499 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22031.922499 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22031.922499 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22031.922499 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22031.922499 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 97 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1591.672723 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.777184 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.777184 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14737290 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14737290 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14737290 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14737290 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14737290 # number of overall hits +system.cpu.icache.overall_hits::total 14737290 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 13967 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 13967 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 13967 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 13967 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 13967 # number of overall misses +system.cpu.icache.overall_misses::total 13967 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 317608000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 317608000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 317608000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 317608000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 317608000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 317608000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14751257 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14751257 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14751257 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14751257 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14751257 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14751257 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000947 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000947 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000947 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000947 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000947 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000947 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22739.886876 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22739.886876 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22739.886876 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22739.886876 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22739.886876 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22739.886876 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 107 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 19.400000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 21.400000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 11468 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 11468 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 234957500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 234957500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 234957500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 234957500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 234957500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 234957500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000780 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000780 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000780 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000780 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000780 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000780 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20488.097314 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20488.097314 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20488.097314 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20488.097314 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20488.097314 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20488.097314 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2475 # 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mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000779 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20958.884441 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20958.884441 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20958.884441 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20958.884441 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20958.884441 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20958.884441 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2411.634709 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8474 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3589 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.361103 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2404.595595 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8500 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3590 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.367688 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.671111 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2014.246310 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 379.717288 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 17.668263 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2005.213140 # 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number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 8485 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 109 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 109 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 8404 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 8430 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 81 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 8485 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 8404 # number of overall hits +system.cpu.l2cache.demand_hits::total 8511 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 8430 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 81 # number of overall hits -system.cpu.l2cache.overall_hits::total 8485 # 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number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21571640 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21571640 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 406953799 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 406953799 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 406953799 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 406953799 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21604314 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21604314 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 235 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 235 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28072743 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28072743 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28072743 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28072743 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 231 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 231 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28105417 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28105417 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28105417 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28105417 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001245 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001245 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004255 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004255 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000323 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000323 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000323 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000323 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45160.696008 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 45160.696008 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42389.902915 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42389.902915 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004329 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004329 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000324 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000324 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000324 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000324 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50286.354582 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50286.354582 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44024.490429 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44024.490429 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 42688.267828 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 42688.267828 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 42688.267828 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 42688.267828 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 10592 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 44715.283925 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 44715.283925 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 44715.283925 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 44715.283925 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 14195 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 468 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 327 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.632479 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.409786 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 109 # number of writebacks system.cpu.dcache.writebacks::total 109 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 465 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6364 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6364 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6829 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6829 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6829 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6829 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 512 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 512 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1732 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1732 # number of WriteReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 489 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6366 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6366 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6855 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6855 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6855 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6855 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 515 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 515 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1731 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1731 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2244 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2244 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2244 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2244 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26453500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26453500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 82660498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 82660498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2246 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2246 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2246 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2246 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30190000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30190000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 88528998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 88528998 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 70000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 70000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 109113998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 109113998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 109113998 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 109113998 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 118718998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 118718998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 118718998 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 118718998 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004255 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004255 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004329 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004329 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51666.992188 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51666.992188 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47725.460739 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47725.460739 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58621.359223 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58621.359223 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51143.268631 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51143.268631 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 70000 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 70000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48624.776292 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 48624.776292 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48624.776292 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 48624.776292 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52857.968833 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52857.968833 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52857.968833 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52857.968833 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |