diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
| commit | 324bc9771d1f3129aee87ccb73bcf23ea4c3b60e (patch) | |
| tree | e5ca02cc181b18d2806e30b99da07d6072724988 /tests/long/se/70.twolf/ref/alpha | |
| parent | 337774e192cb9268244d05e828b395060ba1cefb (diff) | |
| download | gem5-324bc9771d1f3129aee87ccb73bcf23ea4c3b60e.tar.xz | |
stats: Update stats to match cache changes
Diffstat (limited to 'tests/long/se/70.twolf/ref/alpha')
| -rw-r--r-- | tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt | 219 | ||||
| -rw-r--r-- | tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt | 1137 |
2 files changed, 685 insertions, 671 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index 11356e644..8b18f9604 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.051911 # Nu sim_ticks 51910606500 # Number of ticks simulated final_tick 51910606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 339215 # Simulator instruction rate (inst/s) -host_op_rate 339215 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 191602600 # Simulator tick rate (ticks/s) -host_mem_usage 303192 # Number of bytes of host memory used -host_seconds 270.93 # Real time elapsed on the host +host_inst_rate 362776 # Simulator instruction rate (inst/s) +host_op_rate 362776 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 204910533 # Simulator tick rate (ticks/s) +host_mem_usage 303308 # Number of bytes of host memory used +host_seconds 253.33 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -200,12 +200,12 @@ system.physmem.bytesPerActivate::768-895 27 2.76% 85.70% # By system.physmem.bytesPerActivate::896-1023 27 2.76% 88.46% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 113 11.54% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 979 # Bytes accessed per row activation -system.physmem.totQLat 35331250 # Total ticks spent queuing -system.physmem.totMemAccLat 135062500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 35329750 # Total ticks spent queuing +system.physmem.totMemAccLat 135061000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26595000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6642.46 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6642.18 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25392.46 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25392.18 # Average memory access latency per DRAM burst system.physmem.avgRdBW 6.56 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 6.56 # Average system read bandwidth in MiByte/s @@ -227,28 +227,28 @@ system.physmem_0.preEnergy 1914000 # En system.physmem_0.readEnergy 19835400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 3390060960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1735578180 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29619604500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34770500880 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.907929 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49271576750 # Time in different power states +system.physmem_0.actBackEnergy 1735573905 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29619608250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34770500355 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.907919 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49271583750 # Time in different power states system.physmem_0.memoryStateTime::REF 1733160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 898679500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 898672500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 3848040 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 2099625 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 21216000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 3390060960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1825261695 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29540934750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34783421070 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.156857 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49142723000 # Time in different power states +system.physmem_1.actBackEnergy 1825260840 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29540935500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34783420965 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.156855 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49142724000 # Time in different power states system.physmem_1.memoryStateTime::REF 1733160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1030068000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1030067000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 11441088 # Number of BP lookups system.cpu.branchPred.condPredicted 8207826 # Number of conditional branches predicted @@ -305,12 +305,12 @@ system.cpu.ipc 0.885205 # IP system.cpu.tickCycles 102104321 # Number of cycles that the object actually ticked system.cpu.idleCycles 1716892 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1447.424804 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1447.424803 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26573200 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11916.233184 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1447.424804 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1447.424803 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.353375 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.353375 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id @@ -340,12 +340,12 @@ system.cpu.dcache.overall_misses::cpu.data 3431 # system.cpu.dcache.overall_misses::total 3431 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 40212500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 40212500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 214035000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 214035000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 254247500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 254247500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 254247500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 254247500 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 214034000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 214034000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 254246500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 254246500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 254246500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 254246500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20075528 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20075528 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -364,12 +364,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.000129 system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77183.301344 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 77183.301344 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73551.546392 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73551.546392 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 74103.031186 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 74103.031186 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 74103.031186 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 74103.031186 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73551.202749 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73551.202749 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 74102.739726 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 74102.739726 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 74102.739726 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 74102.739726 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -398,12 +398,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 2230 system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37107000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 37107000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131707500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 131707500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 168814500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 168814500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 168814500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 168814500 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131706500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 131706500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 168813500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 168813500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 168813500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 168813500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses @@ -414,20 +414,20 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76509.278351 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76509.278351 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75477.077364 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75477.077364 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75701.569507 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75701.569507 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75701.569507 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75701.569507 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75476.504298 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75476.504298 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75701.121076 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75701.121076 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75701.121076 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75701.121076 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13850 # number of replacements -system.cpu.icache.tags.tagsinuse 1640.456656 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1640.456655 # Cycle average of tags in use system.cpu.icache.tags.total_refs 22937703 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15815 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1450.376415 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1640.456656 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1640.456655 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.801004 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.801004 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id @@ -483,6 +483,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 13850 # number of writebacks +system.cpu.icache.writebacks::total 13850 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15816 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 15816 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 15816 # number of demand (read+write) MSHR misses @@ -509,13 +511,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24855.620890 system.cpu.icache.overall_avg_mshr_miss_latency::total 24855.620890 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2477.794194 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2477.794192 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 26614 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3666 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 7.259684 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 17.781001 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2100.046720 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2100.046719 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 359.966473 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064088 # Average percentage of cache occupancy @@ -530,8 +532,10 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2505 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.111877 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 261827 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 261827 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 13850 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 13850 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12647 # number of ReadCleanReq hits @@ -556,20 +560,22 @@ system.cpu.l2cache.demand_misses::total 5319 # nu system.cpu.l2cache.overall_misses::cpu.inst 3168 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2151 # number of overall misses system.cpu.l2cache.overall_misses::total 5319 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 128817000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 128817000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 236600000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 236600000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 128816000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 128816000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 236598500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 236598500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 35817000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 35817000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 236600000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 164634000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 401234000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 236600000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 164634000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 401234000 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.demand_miss_latency::cpu.inst 236598500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 164633000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 401231500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 236598500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 164633000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 401231500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 107 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 107 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 13850 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 13850 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1745 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1745 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15815 # number of ReadCleanReq accesses(hits+misses) @@ -594,18 +600,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.294763 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200316 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964574 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.294763 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74937.172775 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74937.172775 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74684.343434 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74684.343434 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74936.591041 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74936.591041 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74683.869949 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74683.869949 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82909.722222 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82909.722222 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74684.343434 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76538.354254 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75434.104155 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74684.343434 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76538.354254 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75434.104155 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74683.869949 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76537.889354 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75433.634142 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74683.869949 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76537.889354 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75433.634142 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -626,18 +632,18 @@ system.cpu.l2cache.demand_mshr_misses::total 5319 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2151 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5319 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 111627000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 111627000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 204920000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 204920000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 111626000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 111626000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 204918500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 204918500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31497000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31497000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 204920000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 143124000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 348044000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 204920000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 143124000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 348044000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 204918500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 143123000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 348041500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 204918500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 143123000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 348041500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985100 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985100 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.200316 # mshr miss rate for ReadCleanReq accesses @@ -650,18 +656,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.294763 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200316 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.294763 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64937.172775 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64937.172775 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64684.343434 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64684.343434 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64936.591041 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64936.591041 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64683.869949 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64683.869949 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72909.722222 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72909.722222 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64684.343434 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66538.354254 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65434.104155 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64684.343434 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66538.354254 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65434.104155 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64683.869949 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66537.889354 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65433.634142 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64683.869949 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66537.889354 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65433.634142 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 32052 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 14007 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -670,8 +676,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 16300 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 13900 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 13850 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1745 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1745 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 15815 # Transaction distribution @@ -679,23 +686,23 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 485 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45480 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4617 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 50097 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1012160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1898560 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1161728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2048128 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 32052 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 18045 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 32052 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 18045 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 32052 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 16133000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.snoop_fanout::total 18045 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 29983000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 23722500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3345000 # Layer occupancy (ticks) @@ -719,9 +726,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 5319 # Request fanout histogram -system.membus.reqLayer0.occupancy 6413000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6412500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 28165750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 28165250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index cc5b93144..fdd161331 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.021919 # Number of seconds simulated -sim_ticks 21919473500 # Number of ticks simulated -final_tick 21919473500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.021917 # Number of seconds simulated +sim_ticks 21916940500 # Number of ticks simulated +final_tick 21916940500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 199769 # Simulator instruction rate (inst/s) -host_op_rate 199769 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52017673 # Simulator tick rate (ticks/s) -host_mem_usage 302932 # Number of bytes of host memory used -host_seconds 421.39 # Real time elapsed on the host +host_inst_rate 209109 # Simulator instruction rate (inst/s) +host_op_rate 209109 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54443336 # Simulator tick rate (ticks/s) +host_mem_usage 303052 # Number of bytes of host memory used +host_seconds 402.56 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 195776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 195712 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 138496 # Number of bytes read from this memory -system.physmem.bytes_read::total 334272 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 195776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 195776 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3059 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 334208 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 195712 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 195712 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3058 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2164 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5223 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8931601 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6318400 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15250001 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8931601 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8931601 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8931601 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6318400 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15250001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5223 # Number of read requests accepted +system.physmem.num_reads::total 5222 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8929714 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6319130 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15248844 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8929714 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8929714 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8929714 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6319130 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15248844 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5222 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5223 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5222 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 334272 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 334208 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 334272 # Total read bytes from the system interface side +system.physmem.bytesReadSys 334208 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -50,7 +50,7 @@ system.physmem.perBankRdBursts::5 223 # Pe system.physmem.perBankRdBursts::6 218 # Per bank write bursts system.physmem.perBankRdBursts::7 288 # Per bank write bursts system.physmem.perBankRdBursts::8 239 # Per bank write bursts -system.physmem.perBankRdBursts::9 278 # Per bank write bursts +system.physmem.perBankRdBursts::9 277 # Per bank write bursts system.physmem.perBankRdBursts::10 249 # Per bank write bursts system.physmem.perBankRdBursts::11 251 # Per bank write bursts system.physmem.perBankRdBursts::12 396 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21919378500 # Total gap between requests +system.physmem.totGap 21916845500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5223 # Read request sizes (log2) +system.physmem.readPktSize::6 5222 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1189 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 507 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1190 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 509 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 237 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 860 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 387.497674 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 231.928894 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 358.454487 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 254 29.53% 29.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 187 21.74% 51.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 83 9.65% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 58 6.74% 67.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 36 4.19% 71.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 34 3.95% 75.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 40 4.65% 80.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 50 5.81% 86.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 118 13.72% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 860 # Bytes accessed per row activation -system.physmem.totQLat 44538500 # Total ticks spent queuing -system.physmem.totMemAccLat 142469750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26115000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8527.38 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 859 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 386.235157 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 231.364931 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 358.000658 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 253 29.45% 29.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 187 21.77% 51.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 82 9.55% 60.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 62 7.22% 67.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 35 4.07% 72.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 38 4.42% 76.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 35 4.07% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 43 5.01% 85.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 124 14.44% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 859 # Bytes accessed per row activation +system.physmem.totQLat 43137250 # Total ticks spent queuing +system.physmem.totMemAccLat 141049750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26110000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8260.68 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27277.38 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27010.68 # Average memory access latency per DRAM burst system.physmem.avgRdBW 15.25 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 15.25 # Average system read bandwidth in MiByte/s @@ -216,70 +216,70 @@ system.physmem.busUtilRead 0.12 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4358 # Number of row buffer hits during reads +system.physmem.readRowHits 4353 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.44 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.36 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4196702.76 # Average gap between requests -system.physmem.pageHitRate 83.44 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3160080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1724250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 19741800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 4197021.35 # Average gap between requests +system.physmem.pageHitRate 83.36 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3122280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1703625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 19461000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1431596400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 935708580 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 12330335250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14722266360 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.680556 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 20510216250 # Time in different power states -system.physmem_0.memoryStateTime::REF 731900000 # Time in different power states +system.physmem_0.refreshEnergy 1431087840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 912284145 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 12346211250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14713870140 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.536045 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 20536521000 # Time in different power states +system.physmem_0.memoryStateTime::REF 731640000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 676644750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 642620250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3341520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1823250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 20872800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3311280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1806750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 20748000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1431596400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 913464900 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 12349847250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 14720946120 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.620322 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 20542312250 # Time in different power states -system.physmem_1.memoryStateTime::REF 731900000 # Time in different power states +system.physmem_1.refreshEnergy 1431087840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 917766405 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 12341402250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14716122525 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.638843 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 20529652250 # Time in different power states +system.physmem_1.memoryStateTime::REF 731640000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 644355250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 650829750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 16112018 # Number of BP lookups -system.cpu.branchPred.condPredicted 11701868 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 926184 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8628002 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7529875 # Number of BTB hits +system.cpu.branchPred.lookups 16111441 # Number of BP lookups +system.cpu.branchPred.condPredicted 11701383 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 926235 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8627871 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7529688 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.272523 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1595504 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 407 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 87.271680 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1595490 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 408 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 24062707 # DTB read hits -system.cpu.dtb.read_misses 205786 # DTB read misses +system.cpu.dtb.read_hits 24061115 # DTB read hits +system.cpu.dtb.read_misses 205797 # DTB read misses system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 24268493 # DTB read accesses -system.cpu.dtb.write_hits 7162407 # DTB write hits -system.cpu.dtb.write_misses 1203 # DTB write misses +system.cpu.dtb.read_accesses 24266912 # DTB read accesses +system.cpu.dtb.write_hits 7162299 # DTB write hits +system.cpu.dtb.write_misses 1202 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 7163610 # DTB write accesses -system.cpu.dtb.data_hits 31225114 # DTB hits -system.cpu.dtb.data_misses 206989 # DTB misses +system.cpu.dtb.write_accesses 7163501 # DTB write accesses +system.cpu.dtb.data_hits 31223414 # DTB hits +system.cpu.dtb.data_misses 206999 # DTB misses system.cpu.dtb.data_acv 2 # DTB access violations -system.cpu.dtb.data_accesses 31432103 # DTB accesses -system.cpu.itb.fetch_hits 15925407 # ITB hits +system.cpu.dtb.data_accesses 31430413 # DTB accesses +system.cpu.itb.fetch_hits 15924997 # ITB hits system.cpu.itb.fetch_misses 77 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 15925484 # ITB accesses +system.cpu.itb.fetch_accesses 15925074 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,139 +293,139 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 43838948 # number of cpu cycles simulated +system.cpu.numCycles 43833882 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 16632320 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 137954260 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16112018 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9125379 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 25989721 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1930958 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 137 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 16631894 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 137948476 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16111441 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9125178 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 25988337 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1931044 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 165 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 2266 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 15925407 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 365179 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 43589931 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.164819 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.433135 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 15924997 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 365277 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 43588192 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.164813 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.433150 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19407451 44.52% 44.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2621129 6.01% 50.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1337584 3.07% 53.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1925835 4.42% 58.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3007413 6.90% 64.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1288266 2.96% 67.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1362128 3.12% 71.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 884292 2.03% 73.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11755833 26.97% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19406935 44.52% 44.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2620914 6.01% 50.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1337526 3.07% 53.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1925752 4.42% 58.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3007087 6.90% 64.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1288201 2.96% 67.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1362015 3.12% 71.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 884285 2.03% 73.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11755477 26.97% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43589931 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.367527 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.146842 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12848398 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8248987 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19437203 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2101434 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 953909 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2651089 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 11974 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 132128383 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 49953 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 953909 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13970899 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4649700 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10898 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20300581 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3703944 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 128750721 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 69632 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2039237 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1388591 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 55010 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 94550726 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 167277672 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 159796203 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7481468 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 43588192 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.367557 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.147074 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12849243 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8247037 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19437084 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2100878 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 953950 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2651003 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 11975 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 132120831 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 49966 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 953950 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13971462 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4650933 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10896 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20300187 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3700764 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 128743195 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 69669 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2038779 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1385854 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 54667 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 94545107 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 167268798 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 159787749 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7481048 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 26123365 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 949 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 946 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8314647 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26912240 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8709829 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3514186 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1623457 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111857121 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1283 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 99743085 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 115820 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 27678694 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 21106490 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 894 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43589931 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.288214 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.099779 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 26117746 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 950 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 948 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8310352 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26910154 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8709135 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3511293 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1618997 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111850389 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1284 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 99739394 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 116060 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 27671963 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 21101257 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 895 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43588192 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.288220 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.099837 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11253194 25.82% 25.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 7641118 17.53% 43.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7479948 17.16% 60.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5719610 13.12% 73.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4459621 10.23% 83.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2975044 6.83% 90.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2026173 4.65% 95.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1169285 2.68% 98.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 865938 1.99% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11252596 25.82% 25.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 7641941 17.53% 43.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7479961 17.16% 60.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5717065 13.12% 73.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4459781 10.23% 83.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2974994 6.83% 90.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2026656 4.65% 95.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1169278 2.68% 98.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 865920 1.99% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43589931 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43588192 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 482162 20.24% 20.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 482625 20.24% 20.24% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 20.24% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 20.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 537 0.02% 20.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 536 0.02% 20.26% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 34275 1.44% 21.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 12320 0.52% 22.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1010506 42.41% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 685066 28.75% 93.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 157661 6.62% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 34267 1.44% 21.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 12315 0.52% 22.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1010469 42.37% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 686537 28.79% 93.37% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 158059 6.63% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60678292 60.83% 60.83% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 490564 0.49% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60676588 60.84% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 490565 0.49% 61.33% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2838989 2.85% 64.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115355 0.12% 64.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2438911 2.45% 66.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 313691 0.31% 67.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 766049 0.77% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2839004 2.85% 64.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115354 0.12% 64.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2438838 2.45% 66.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 313701 0.31% 67.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 766055 0.77% 67.82% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.82% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.82% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.82% # Type of FU issued @@ -447,84 +447,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.82% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.82% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.82% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24838081 24.90% 92.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7262827 7.28% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24836317 24.90% 92.72% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7262646 7.28% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 99743085 # Type of FU issued -system.cpu.iq.rate 2.275216 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2382527 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023887 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 229948900 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 130065304 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 89786778 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15625548 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9512793 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7169302 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 93776538 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8349067 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1917366 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 99739394 # Type of FU issued +system.cpu.iq.rate 2.275395 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2384808 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023910 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 229942315 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 130052988 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 89783673 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15625533 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9511643 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7169331 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 93775141 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8349054 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1917494 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6916042 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11056 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 41363 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2208726 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6913956 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11070 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 41356 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2208032 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 42784 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1527 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 42783 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1512 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 953909 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3616734 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 464700 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 122788755 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 239982 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26912240 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8709829 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1283 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 38454 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 420547 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 41363 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 525246 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 502956 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1028202 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 98432500 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 24268972 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1310585 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 953950 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3617044 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 465078 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 122781228 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 240022 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 26910154 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8709135 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1284 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 38486 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 420890 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 41356 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 525280 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 502970 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1028250 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 98428862 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 24267391 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1310532 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10930351 # number of nop insts executed -system.cpu.iew.exec_refs 31432616 # number of memory reference insts executed -system.cpu.iew.exec_branches 12487704 # Number of branches executed -system.cpu.iew.exec_stores 7163644 # Number of stores executed -system.cpu.iew.exec_rate 2.245321 # Inst execution rate -system.cpu.iew.wb_sent 97645732 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 96956080 # cumulative count of insts written-back -system.cpu.iew.wb_producers 66985594 # num instructions producing a value -system.cpu.iew.wb_consumers 95002941 # num instructions consuming a value +system.cpu.iew.exec_nop 10929555 # number of nop insts executed +system.cpu.iew.exec_refs 31430926 # number of memory reference insts executed +system.cpu.iew.exec_branches 12487406 # Number of branches executed +system.cpu.iew.exec_stores 7163535 # Number of stores executed +system.cpu.iew.exec_rate 2.245497 # Inst execution rate +system.cpu.iew.wb_sent 97642114 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 96953004 # cumulative count of insts written-back +system.cpu.iew.wb_producers 66984387 # num instructions producing a value +system.cpu.iew.wb_consumers 95000699 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.211642 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.705090 # average fanout of values written-back +system.cpu.iew.wb_rate 2.211828 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.705094 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 30887581 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 30880053 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 914614 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 39095972 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.350704 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.921132 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 914663 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 39095166 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.350752 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.921213 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 14698430 37.60% 37.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8547015 21.86% 59.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3864183 9.88% 69.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1929221 4.93% 74.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1372371 3.51% 77.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1004316 2.57% 80.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 690404 1.77% 82.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 733733 1.88% 84.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6256299 16.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 14698751 37.60% 37.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8546224 21.86% 59.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3864207 9.88% 69.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1928510 4.93% 74.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1372257 3.51% 77.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1004424 2.57% 80.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 690640 1.77% 82.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 733325 1.88% 84.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6256828 16.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 39095972 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 39095166 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -570,118 +570,118 @@ system.cpu.commit.op_class_0::MemWrite 6501103 7.07% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction -system.cpu.commit.bw_lim_events 6256299 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 155629269 # The number of ROB reads -system.cpu.rob.rob_writes 250130763 # The number of ROB writes -system.cpu.timesIdled 4629 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 249017 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 6256828 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 155620406 # The number of ROB reads +system.cpu.rob.rob_writes 250114778 # The number of ROB writes +system.cpu.timesIdled 4635 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 245690 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.520778 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.520778 # CPI: Total CPI of All Threads -system.cpu.ipc 1.920204 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.920204 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 132982273 # number of integer regfile reads -system.cpu.int_regfile_writes 72919705 # number of integer regfile writes -system.cpu.fp_regfile_reads 6252521 # number of floating regfile reads -system.cpu.fp_regfile_writes 6155462 # number of floating regfile writes -system.cpu.misc_regfile_reads 719143 # number of misc regfile reads +system.cpu.cpi 0.520718 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.520718 # CPI: Total CPI of All Threads +system.cpu.ipc 1.920426 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.920426 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 132978272 # number of integer regfile reads +system.cpu.int_regfile_writes 72916434 # number of integer regfile writes +system.cpu.fp_regfile_reads 6252591 # number of floating regfile reads +system.cpu.fp_regfile_writes 6155476 # number of floating regfile writes +system.cpu.misc_regfile_reads 719142 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 158 # number of replacements -system.cpu.dcache.tags.tagsinuse 1457.350779 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28592916 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1457.328310 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28591208 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2244 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12741.941176 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12741.180036 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1457.350779 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.355799 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.355799 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1457.328310 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.355793 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.355793 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2086 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 542 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1389 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.509277 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 57207152 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 57207152 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22099846 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22099846 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492613 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492613 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 57203742 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 57203742 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22098137 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22098137 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492614 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492614 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 457 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 457 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28592459 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28592459 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28592459 # number of overall hits -system.cpu.dcache.overall_hits::total 28592459 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1047 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1047 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8490 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8490 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 28590751 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28590751 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28590751 # number of overall hits +system.cpu.dcache.overall_hits::total 28590751 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1051 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1051 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8489 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8489 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9537 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9537 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9537 # number of overall misses -system.cpu.dcache.overall_misses::total 9537 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 69532500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 69532500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 543709251 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 543709251 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9540 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9540 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9540 # number of overall misses +system.cpu.dcache.overall_misses::total 9540 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 72374000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 72374000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 544060252 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 544060252 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 85000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 85000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 613241751 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 613241751 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 613241751 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 613241751 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22100893 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22100893 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 616434252 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 616434252 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 616434252 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 616434252 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22099188 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22099188 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 458 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 458 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28601996 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28601996 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28601996 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28601996 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000047 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000047 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 28600291 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28600291 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28600291 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28600291 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000048 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000048 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001306 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001306 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002183 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002183 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000333 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000333 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000333 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000333 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66411.174785 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66411.174785 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64041.136749 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64041.136749 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.000334 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000334 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000334 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000334 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68862.036156 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68862.036156 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64090.028507 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64090.028507 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64301.326518 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64301.326518 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64301.326518 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64301.326518 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32746 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64615.749686 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64615.749686 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64615.749686 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64615.749686 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32998 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 127 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 389 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 378 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 84.179949 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 87.296296 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 63.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 108 # number of writebacks system.cpu.dcache.writebacks::total 108 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 540 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 540 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6754 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6754 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7294 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7294 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7294 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7294 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 544 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 544 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6753 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6753 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7297 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7297 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7297 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7297 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 507 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 507 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1736 # number of WriteReq MSHR misses @@ -692,16 +692,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2243 system.cpu.dcache.demand_mshr_misses::total 2243 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2243 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2243 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39700000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 39700000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 135151495 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 135151495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40562000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 40562000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 135653495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 135653495 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 84000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 84000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 174851495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 174851495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 174851495 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 174851495 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 176215495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 176215495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 176215495 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 176215495 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000267 # mshr miss rate for WriteReq accesses @@ -712,134 +712,138 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000078 system.cpu.dcache.demand_mshr_miss_rate::total 0.000078 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000078 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78303.747535 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78303.747535 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77852.243664 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77852.243664 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80003.944773 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80003.944773 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78141.414171 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78141.414171 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 84000 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 84000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77954.300045 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77954.300045 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77954.300045 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77954.300045 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78562.414177 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78562.414177 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78562.414177 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78562.414177 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 9477 # number of replacements -system.cpu.icache.tags.tagsinuse 1601.339074 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 15910864 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 11414 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1393.977922 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 9476 # number of replacements +system.cpu.icache.tags.tagsinuse 1601.325936 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 15910465 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 11413 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1394.065101 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1601.339074 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.781904 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.781904 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1601.325936 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.781897 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.781897 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 181 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 752 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 944 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 31862226 # Number of tag accesses -system.cpu.icache.tags.data_accesses 31862226 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 15910864 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 15910864 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 15910864 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 15910864 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 15910864 # number of overall hits -system.cpu.icache.overall_hits::total 15910864 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14542 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14542 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14542 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14542 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14542 # number of overall misses -system.cpu.icache.overall_misses::total 14542 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 447928500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 447928500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 447928500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 447928500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 447928500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 447928500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 15925406 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 15925406 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 15925406 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 15925406 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 15925406 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 15925406 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000913 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000913 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000913 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000913 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000913 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000913 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30802.399945 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 30802.399945 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 30802.399945 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 30802.399945 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 30802.399945 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 30802.399945 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 837 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 31861405 # Number of tag accesses +system.cpu.icache.tags.data_accesses 31861405 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 15910465 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 15910465 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 15910465 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 15910465 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 15910465 # 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number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 444593500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 15924996 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 15924996 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 15924996 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 15924996 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 15924996 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 15924996 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000912 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000912 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000912 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000912 # 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number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 11414 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 11414 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 11414 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 11414 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 11414 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 338490500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 338490500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 338490500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 338490500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 338490500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 338490500 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 9476 # number of writebacks +system.cpu.icache.writebacks::total 9476 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3118 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3118 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3118 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3118 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3118 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3118 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11413 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 11413 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 11413 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 11413 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 11413 # 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mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000717 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000717 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29655.729806 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29655.729806 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29655.729806 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 29655.729806 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29655.729806 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 29655.729806 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29438.315955 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29438.315955 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29438.315955 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 29438.315955 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29438.315955 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 29438.315955 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2397.609271 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 17951 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3579 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 5.015647 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2397.525400 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 17950 # 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Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2421 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.109222 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 191659 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 191659 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 108 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 108 # number of Writeback hits +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.109192 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 191642 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 191642 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 108 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 108 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 9476 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 9476 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8355 # number of ReadCleanReq hits @@ -854,66 +858,68 @@ system.cpu.l2cache.overall_hits::cpu.data 80 # n system.cpu.l2cache.overall_hits::total 8435 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 1710 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 1710 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3059 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3059 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3058 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 3058 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 454 # 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number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 233633500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 233633500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 38438500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 38438500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 233633500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 170571000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 404204500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 233633500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 170571000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 404204500 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 108 # 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number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 230850500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 171935000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 402785500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 108 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 108 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 9476 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 9476 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1736 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1736 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 11414 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 11414 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 11413 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 11413 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 508 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 508 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 11414 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 11413 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 2244 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 13658 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 11414 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 13657 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 11413 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2244 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 13658 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 13657 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985023 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.985023 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.268004 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.268004 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.267940 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.267940 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.893701 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.893701 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.268004 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.267940 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.964349 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.382413 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.268004 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.382368 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.267940 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964349 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.382413 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77270.467836 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77270.467836 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76375.776398 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76375.776398 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84666.299559 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84666.299559 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76375.776398 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78822.088725 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77389.335631 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76375.776398 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78822.088725 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77389.335631 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.382368 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77564.035088 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77564.035088 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75490.680183 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75490.680183 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86564.977974 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86564.977974 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75490.680183 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79452.402957 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77132.420529 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75490.680183 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79452.402957 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77132.420529 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -924,112 +930,113 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1710 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1710 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3059 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3059 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3058 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3058 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 454 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 454 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3059 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3058 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 2164 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5223 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3059 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5222 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3058 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2164 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5223 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 115032500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 115032500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 203043500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 203043500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 33898500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 33898500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 203043500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 148931000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 351974500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 203043500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 148931000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 351974500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 5222 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 115534500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 115534500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 200270500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 200270500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 34760500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 34760500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 200270500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 150295000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 350565500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 200270500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 150295000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 350565500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985023 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985023 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.268004 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.268004 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.267940 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.267940 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.893701 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.893701 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.268004 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.267940 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964349 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.382413 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.268004 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.382368 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.267940 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964349 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.382413 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67270.467836 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67270.467836 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66375.776398 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66375.776398 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74666.299559 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74666.299559 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66375.776398 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68822.088725 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67389.335631 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66375.776398 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68822.088725 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67389.335631 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.382368 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67564.035088 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67564.035088 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65490.680183 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65490.680183 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76564.977974 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76564.977974 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65490.680183 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69452.402957 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67132.420529 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65490.680183 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69452.402957 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67132.420529 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 23293 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9635 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 23291 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9634 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 11922 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 108 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 9527 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 11921 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 108 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 9476 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1736 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1736 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 11414 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 11413 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 508 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32305 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32302 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4646 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 36951 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730496 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 36948 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1336896 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 881024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1487424 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 23293 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 13657 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 23293 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 13657 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 23293 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 11754500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 13657 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 21229500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 17121000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 17119500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3366000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3513 # Transaction distribution +system.membus.trans_dist::ReadResp 3512 # Transaction distribution system.membus.trans_dist::ReadExReq 1710 # Transaction distribution system.membus.trans_dist::ReadExResp 1710 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3513 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10446 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10446 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334272 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 334272 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 3512 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10444 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10444 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334208 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 334208 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5223 # Request fanout histogram +system.membus.snoop_fanout::samples 5222 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5223 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5222 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5223 # Request fanout histogram -system.membus.reqLayer0.occupancy 6235500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5222 # Request fanout histogram +system.membus.reqLayer0.occupancy 6271000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 27428750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 27427000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |