diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
| commit | fda338f8d3ba6f6cb271e2c10cb880ff064edb61 (patch) | |
| tree | 20a91f6acacb2cb40967ce56a539d8444b744b9e /tests/long/se/70.twolf/ref/alpha | |
| parent | b265d9925c123f0df50db98cf56dab6a3596b54b (diff) | |
| download | gem5-fda338f8d3ba6f6cb271e2c10cb880ff064edb61.tar.xz | |
Stats: Updates due to bus changes
This patch bumps all the stats to reflect the bus changes, i.e. the
introduction of the state variable, the division into a request and
response layer, and the new default bus width of 8 bytes.
Diffstat (limited to 'tests/long/se/70.twolf/ref/alpha')
9 files changed, 922 insertions, 916 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini index 4aef8f4de..db2911eab 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini @@ -181,7 +181,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -213,7 +213,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout index 926d51412..b50317767 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:37:18 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 10:35:16 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing +Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sav +Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -21,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 42005374000 because target called exit() +122 123 124 Exiting @ tick 42012413000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 60e11bdef..c057cfc04 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.042005 # Number of seconds simulated -sim_ticks 42005374000 # Number of ticks simulated -final_tick 42005374000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.042012 # Number of seconds simulated +sim_ticks 42012413000 # Number of ticks simulated +final_tick 42012413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 160903 # Simulator instruction rate (inst/s) -host_op_rate 160903 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 73542430 # Simulator tick rate (ticks/s) -host_mem_usage 222752 # Number of bytes of host memory used -host_seconds 571.17 # Real time elapsed on the host +host_inst_rate 107145 # Simulator instruction rate (inst/s) +host_op_rate 107145 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48980163 # Simulator tick rate (ticks/s) +host_mem_usage 222716 # Number of bytes of host memory used +host_seconds 857.74 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory @@ -19,34 +19,34 @@ system.physmem.bytes_inst_read::total 178816 # Nu system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 4256979 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3266630 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7523609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4256979 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4256979 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4256979 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3266630 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7523609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 4256266 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3266082 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7522348 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4256266 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4256266 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4256266 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3266082 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7522348 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 19996214 # DTB read hits +system.cpu.dtb.read_hits 19996215 # DTB read hits system.cpu.dtb.read_misses 10 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 19996224 # DTB read accesses -system.cpu.dtb.write_hits 6501905 # DTB write hits +system.cpu.dtb.read_accesses 19996225 # DTB read accesses +system.cpu.dtb.write_hits 6501907 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6501928 # DTB write accesses -system.cpu.dtb.data_hits 26498119 # DTB hits +system.cpu.dtb.write_accesses 6501930 # DTB write accesses +system.cpu.dtb.data_hits 26498122 # DTB hits system.cpu.dtb.data_misses 33 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 26498152 # DTB accesses -system.cpu.itb.fetch_hits 10037351 # ITB hits +system.cpu.dtb.data_accesses 26498155 # DTB accesses +system.cpu.itb.fetch_hits 10034924 # ITB hits system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 10037400 # ITB accesses +system.cpu.itb.fetch_accesses 10034973 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,42 +60,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 84010749 # number of cpu cycles simulated +system.cpu.numCycles 84024827 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 13563923 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 9779691 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 4496836 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 7950423 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 3848158 # Number of BTB hits +system.cpu.branch_predictor.lookups 13564834 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 9782438 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 4497092 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 7991226 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 3849853 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target. -system.cpu.branch_predictor.RASInCorrect 123 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 48.401928 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 5997418 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 7566505 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 73742077 # Number of Reads from Int. Register File +system.cpu.branch_predictor.RASInCorrect 121 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 48.176000 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 5999065 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 7565769 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 73744929 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 136317549 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 2206798 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 136320401 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 2206799 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 8058686 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 38530251 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 26765541 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 3521133 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 974845 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4495978 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 5744724 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 43.903025 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 57471384 # Number of Instructions Executed. -system.cpu.mult_div_unit.multiplies 458266 # Number of Multipy Operations Executed +system.cpu.regfile_manager.floatRegFileAccesses 8058687 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 38529057 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 26768938 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 3519911 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 976323 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4496234 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 5744468 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 43.905525 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 57470438 # Number of Instructions Executed. +system.cpu.mult_div_unit.multiplies 458258 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 83632403 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 83640241 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 11097 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7735993 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 76274756 # Number of cycles cpu stages are processed. -system.cpu.activity 90.791663 # Percentage of cycles cpu is active +system.cpu.timesIdled 11659 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7743859 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 76280968 # Number of cycles cpu stages are processed. +system.cpu.activity 90.783844 # Percentage of cycles cpu is active system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed @@ -107,144 +107,144 @@ system.cpu.committedInsts 91903056 # Nu system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) -system.cpu.cpi 0.914124 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.914277 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.914124 # CPI: Total CPI of All Threads -system.cpu.ipc 1.093944 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.914277 # CPI: Total CPI of All Threads +system.cpu.ipc 1.093761 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.093944 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 27790213 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 56220536 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 66.920646 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 34560671 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 49450078 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 58.861608 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 34032650 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 49978099 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 59.490124 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65981194 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 18029555 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.461010 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 30068425 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 53942324 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.208836 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 8111 # number of replacements -system.cpu.icache.tagsinuse 1492.322334 # Cycle average of tags in use -system.cpu.icache.total_refs 10025618 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 9996 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1002.962985 # Average number of references to valid blocks. +system.cpu.ipc_total 1.093761 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 27805541 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 56219286 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 66.907946 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 34577681 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 49447146 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 58.848257 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 34047365 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 49977462 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 59.479399 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65995198 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 18029629 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.457502 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 30080947 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 53943880 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.199930 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 8128 # number of replacements +system.cpu.icache.tagsinuse 1492.257079 # Cycle average of tags in use +system.cpu.icache.total_refs 10023168 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 10013 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1001.015480 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1492.322334 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.728673 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.728673 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10025618 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10025618 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10025618 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10025618 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10025618 # number of overall hits -system.cpu.icache.overall_hits::total 10025618 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11728 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11728 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11728 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11728 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11728 # number of overall misses -system.cpu.icache.overall_misses::total 11728 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 295393500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 295393500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 295393500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 295393500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 295393500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 295393500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 10037346 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 10037346 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 10037346 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 10037346 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 10037346 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 10037346 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001168 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001168 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001168 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001168 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001168 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001168 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25187.031037 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25187.031037 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25187.031037 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25187.031037 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25187.031037 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25187.031037 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1492.257079 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.728641 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.728641 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 10023168 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10023168 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10023168 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10023168 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10023168 # number of overall hits +system.cpu.icache.overall_hits::total 10023168 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11752 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11752 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11752 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11752 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11752 # number of overall misses +system.cpu.icache.overall_misses::total 11752 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 302404500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 302404500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 302404500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 302404500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 302404500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 302404500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 10034920 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 10034920 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 10034920 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 10034920 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 10034920 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 10034920 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001171 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001171 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001171 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001171 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001171 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001171 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25732.173247 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25732.173247 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25732.173247 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25732.173247 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25732.173247 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25732.173247 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 97000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 91000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 16166.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 15166.666667 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1732 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1732 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1732 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1732 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1732 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1732 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9996 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 9996 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 9996 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 9996 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 9996 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 9996 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 228898000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 228898000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 228898000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 228898000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 228898000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 228898000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000996 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000996 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000996 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000996 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000996 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000996 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22898.959584 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22898.959584 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22898.959584 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22898.959584 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22898.959584 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22898.959584 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1739 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1739 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1739 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1739 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1739 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1739 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10013 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 10013 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 10013 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 10013 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 10013 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 10013 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 234933000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 234933000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 234933000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 234933000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 234933000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 234933000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000998 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000998 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000998 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23462.798362 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23462.798362 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23462.798362 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 23462.798362 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23462.798362 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 23462.798362 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1441.511431 # Cycle average of tags in use -system.cpu.dcache.total_refs 26491208 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1441.425760 # Cycle average of tags in use +system.cpu.dcache.total_refs 26491190 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11916.872695 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11916.864597 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1441.511431 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.351932 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.351932 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 19995646 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 19995646 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6495562 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6495562 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26491208 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26491208 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26491208 # number of overall hits -system.cpu.dcache.overall_hits::total 26491208 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 552 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 552 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5541 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5541 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 6093 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 6093 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 6093 # number of overall misses -system.cpu.dcache.overall_misses::total 6093 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 28391500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 28391500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 303790500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 303790500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 332182000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 332182000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 332182000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 332182000 # number of overall miss cycles +system.cpu.dcache.occ_blocks::cpu.data 1441.425760 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.351911 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.351911 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 19995640 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 19995640 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6495550 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6495550 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26491190 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26491190 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26491190 # number of overall hits +system.cpu.dcache.overall_hits::total 26491190 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 558 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 558 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5553 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5553 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 6111 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 6111 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 6111 # number of overall misses +system.cpu.dcache.overall_misses::total 6111 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29911500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29911500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 335932500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 335932500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 365844000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 365844000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 365844000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 365844000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -255,38 +255,38 @@ system.cpu.dcache.overall_accesses::cpu.data 26497301 system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000852 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000852 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000230 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000230 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000230 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000230 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51433.876812 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51433.876812 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54825.933947 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54825.933947 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54518.627934 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54518.627934 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54518.627934 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54518.627934 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000854 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000854 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000231 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000231 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000231 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000231 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53604.838710 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 53604.838710 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60495.678012 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60495.678012 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59866.470299 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59866.470299 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59866.470299 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59866.470299 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 41043500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 41291000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 823 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 827 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 49870.595383 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 49928.657799 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 107 # number of writebacks system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 77 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3793 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3793 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3870 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3870 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3870 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3870 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3805 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3805 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3888 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3888 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3888 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3888 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses @@ -295,14 +295,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23216000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23216000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92995500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 92995500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 116211500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 116211500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 116211500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 116211500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24206500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24206500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 96919000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 96919000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 121125500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 121125500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 121125500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 121125500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -311,41 +311,41 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48875.789474 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48875.789474 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53201.086957 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53201.086957 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52276.878093 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52276.878093 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52276.878093 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52276.878093 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50961.052632 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50961.052632 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55445.652174 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55445.652174 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54487.404408 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 54487.404408 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54487.404408 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 54487.404408 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2189.730470 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7269 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2189.621103 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7286 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.214808 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.219988 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.847253 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1820.879596 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 351.003621 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 17.844366 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1820.786741 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 350.989996 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.055569 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.010712 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.066825 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 7202 # number of ReadReq hits +system.cpu.l2cache.occ_percent::cpu.inst 0.055566 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.010711 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.066822 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 7219 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 7255 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 7272 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 7202 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 7219 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7281 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 7202 # number of overall hits +system.cpu.l2cache.demand_hits::total 7298 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 7219 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits -system.cpu.l2cache.overall_hits::total 7281 # number of overall hits +system.cpu.l2cache.overall_hits::total 7298 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 2794 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 3216 # number of ReadReq misses @@ -357,52 +357,52 @@ system.cpu.l2cache.demand_misses::total 4938 # nu system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4938 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 146177000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22139000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 168316000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 90566000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 90566000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 146177000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 112705000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 258882000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 146177000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 112705000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 258882000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 9996 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 149287500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 23083500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 172371000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 94426500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 94426500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 149287500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 117510000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 266797500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 149287500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 117510000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 266797500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 10013 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 10471 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 10488 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 9996 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 10013 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 12219 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 9996 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 12236 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 10013 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 12219 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.279512 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 12236 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.279037 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.307134 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.306636 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.985126 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.279512 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.279037 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.404125 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.279512 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.403563 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.279037 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.404125 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52318.181818 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52462.085308 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52337.064677 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52593.495935 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52593.495935 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52318.181818 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52567.630597 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52426.488457 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52318.181818 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52567.630597 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52426.488457 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.403563 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53431.460272 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54700.236967 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 53597.947761 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54835.365854 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54835.365854 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53431.460272 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54808.768657 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 54029.465371 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53431.460272 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54808.768657 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 54029.465371 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -422,39 +422,39 @@ system.cpu.l2cache.demand_mshr_misses::total 4938 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 112070000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16981000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 129051000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69345500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69345500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 112070000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86326500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 198396500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 112070000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86326500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 198396500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.279512 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115196500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17936000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 133132500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 73235000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 73235000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115196500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 91171000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 206367500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115196500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 91171000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 206367500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.279037 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.307134 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.306636 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.279512 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.279037 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.404125 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.279512 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.403563 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.279037 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.404125 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40110.952040 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40239.336493 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40127.798507 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40270.325203 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40270.325203 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40110.952040 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40264.225746 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40177.501013 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40110.952040 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40264.225746 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40177.501013 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.403563 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41229.957051 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42502.369668 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41396.921642 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42529.036005 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42529.036005 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41229.957051 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42523.787313 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41791.717294 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41229.957051 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42523.787313 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41791.717294 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini index d1830cc83..064828e12 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -479,7 +479,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -511,7 +511,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout index 157ee9690..bbfeb5540 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:41:57 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 10:49:45 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing +Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav +Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -21,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 23635060000 because target called exit() +122 123 124 Exiting @ tick 23661066000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 42e01362d..dcc05c5e6 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023635 # Number of seconds simulated -sim_ticks 23635060000 # Number of ticks simulated -final_tick 23635060000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023661 # Number of seconds simulated +sim_ticks 23661066000 # Number of ticks simulated +final_tick 23661066000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 242450 # Simulator instruction rate (inst/s) -host_op_rate 242450 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 68072464 # Simulator tick rate (ticks/s) -host_mem_usage 223772 # Number of bytes of host memory used -host_seconds 347.20 # Real time elapsed on the host +host_inst_rate 163409 # Simulator instruction rate (inst/s) +host_op_rate 163409 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45930776 # Simulator tick rate (ticks/s) +host_mem_usage 223740 # Number of bytes of host memory used +host_seconds 515.15 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 197248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 197312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138432 # Number of bytes read from this memory system.physmem.bytes_read::total 335744 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 197248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 197248 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3082 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2164 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 197312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 197312 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3083 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2163 # Number of read requests responded to by this memory system.physmem.num_reads::total 5246 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8345568 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5859769 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14205337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8345568 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8345568 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8345568 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5859769 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 14205337 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 8339100 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5850624 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14189724 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8339100 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8339100 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8339100 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5850624 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 14189724 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 23228346 # DTB read hits -system.cpu.dtb.read_misses 200425 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 23428771 # DTB read accesses -system.cpu.dtb.write_hits 7078031 # DTB write hits -system.cpu.dtb.write_misses 1393 # DTB write misses -system.cpu.dtb.write_acv 5 # DTB write access violations -system.cpu.dtb.write_accesses 7079424 # DTB write accesses -system.cpu.dtb.data_hits 30306377 # DTB hits -system.cpu.dtb.data_misses 201818 # DTB misses +system.cpu.dtb.read_hits 23226472 # DTB read hits +system.cpu.dtb.read_misses 199471 # DTB read misses +system.cpu.dtb.read_acv 2 # DTB read access violations +system.cpu.dtb.read_accesses 23425943 # DTB read accesses +system.cpu.dtb.write_hits 7079215 # DTB write hits +system.cpu.dtb.write_misses 1341 # DTB write misses +system.cpu.dtb.write_acv 3 # DTB write access violations +system.cpu.dtb.write_accesses 7080556 # DTB write accesses +system.cpu.dtb.data_hits 30305687 # DTB hits +system.cpu.dtb.data_misses 200812 # DTB misses system.cpu.dtb.data_acv 5 # DTB access violations -system.cpu.dtb.data_accesses 30508195 # DTB accesses -system.cpu.itb.fetch_hits 14951144 # ITB hits +system.cpu.dtb.data_accesses 30506499 # DTB accesses +system.cpu.itb.fetch_hits 14950241 # ITB hits system.cpu.itb.fetch_misses 107 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14951251 # ITB accesses +system.cpu.itb.fetch_accesses 14950348 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,146 +60,146 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 47270121 # number of cpu cycles simulated +system.cpu.numCycles 47322133 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15030146 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 10897396 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 964237 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 8689796 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7074632 # Number of BTB hits +system.cpu.BPredUnit.lookups 15026940 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10894124 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 964629 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 8768677 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7072325 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1488592 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 3325 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 15628273 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 128247685 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15030146 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 8563224 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22387448 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4637135 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5522059 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1901 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14951144 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 336879 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 47178795 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.718333 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.372984 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1489344 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 3225 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15650036 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 128237375 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15026940 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 8561669 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22385381 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4637420 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5548184 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2165 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14950241 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 337394 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 47225069 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.715451 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.372476 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24791347 52.55% 52.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2391230 5.07% 57.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1207932 2.56% 60.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1776893 3.77% 63.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2805490 5.95% 69.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1170846 2.48% 72.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1228782 2.60% 74.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 789170 1.67% 76.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11017105 23.35% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24839688 52.60% 52.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2391446 5.06% 57.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1209126 2.56% 60.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1776446 3.76% 63.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2802962 5.94% 69.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1171165 2.48% 72.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1227887 2.60% 75.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 787448 1.67% 76.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11018901 23.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 47178795 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.317963 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.713081 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17466562 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4227162 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20770000 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1087804 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3627267 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2544055 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12184 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 125158453 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 31894 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3627267 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18628524 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 960250 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8367 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20673426 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3280961 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 122187472 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 13 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 401237 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2407508 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 89717314 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 158683253 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 148939266 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9743987 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 47225069 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.317546 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.709882 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17490874 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4250840 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20765641 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1090220 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3627494 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2542741 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12176 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 125152088 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 32110 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3627494 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18655906 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 966254 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8182 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20668416 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3298817 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 122169743 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 401900 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2424267 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 89702215 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 158657740 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 148914395 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9743345 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 21289953 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1139 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1148 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8701053 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 25559054 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8299979 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2600508 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 916071 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 106169681 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2314 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 96996119 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 187372 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21529768 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16156839 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1925 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 47178795 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.055926 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.875880 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 21274854 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1091 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1100 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8739612 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 25558040 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8300974 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2604808 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 921406 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 106164029 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2236 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 96990974 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 187003 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21520200 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16153199 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1847 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 47225069 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.053803 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.875376 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12439775 26.37% 26.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 9421207 19.97% 46.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8463269 17.94% 64.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6318044 13.39% 77.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4948438 10.49% 88.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2848262 6.04% 94.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1729160 3.67% 97.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 800900 1.70% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 209740 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12469931 26.41% 26.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9437048 19.98% 46.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8469534 17.93% 64.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6320288 13.38% 77.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4943441 10.47% 88.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2849790 6.03% 94.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1723941 3.65% 97.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 801134 1.70% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 209962 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 47178795 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 47225069 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 186062 11.86% 11.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 228 0.01% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 7118 0.45% 12.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 5890 0.38% 12.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 842932 53.71% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 447788 28.53% 94.94% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 79372 5.06% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 187127 11.94% 11.94% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.94% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 172 0.01% 11.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 7127 0.45% 12.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 5609 0.36% 12.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 843370 53.79% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.55% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 445220 28.40% 94.95% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 79228 5.05% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58995521 60.82% 60.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 480822 0.50% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58991306 60.82% 60.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 480706 0.50% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2802067 2.89% 64.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115555 0.12% 64.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2385721 2.46% 66.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 311403 0.32% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 759596 0.78% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2802495 2.89% 64.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115483 0.12% 64.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2386219 2.46% 66.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 311493 0.32% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 759735 0.78% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.89% # Type of FU issued @@ -221,86 +221,86 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.89% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23975443 24.72% 92.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7169665 7.39% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23972181 24.72% 92.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7171030 7.39% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 96996119 # Type of FU issued -system.cpu.iq.rate 2.051954 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1569390 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016180 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 227797779 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 118919368 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87372371 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15130016 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 8817376 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7067715 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90571077 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7994425 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1518936 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 96990974 # Type of FU issued +system.cpu.iq.rate 2.049590 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1567853 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016165 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 227829224 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 118898019 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87368354 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15132649 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 8823096 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7068677 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90563080 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7995740 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1518780 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5562856 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 19876 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 35099 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1798876 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5561842 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 19579 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34790 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1799871 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10509 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10514 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3627267 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 134249 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17377 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 116472912 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 393481 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 25559054 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8299979 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2314 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2868 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 32 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 35099 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 569232 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 508759 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1077991 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 95699624 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23429474 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1296495 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3627494 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 132338 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17118 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 116467170 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 392102 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 25558040 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8300974 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2236 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2929 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 49 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 34790 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 570155 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 508194 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1078349 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 95694648 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23426609 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1296326 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10300917 # number of nop insts executed -system.cpu.iew.exec_refs 30509089 # number of memory reference insts executed -system.cpu.iew.exec_branches 12078604 # Number of branches executed -system.cpu.iew.exec_stores 7079615 # Number of stores executed -system.cpu.iew.exec_rate 2.024527 # Inst execution rate -system.cpu.iew.wb_sent 94984897 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 94440086 # cumulative count of insts written-back -system.cpu.iew.wb_producers 64627368 # num instructions producing a value -system.cpu.iew.wb_consumers 90016132 # num instructions consuming a value +system.cpu.iew.exec_nop 10300905 # number of nop insts executed +system.cpu.iew.exec_refs 30507339 # number of memory reference insts executed +system.cpu.iew.exec_branches 12077728 # Number of branches executed +system.cpu.iew.exec_stores 7080730 # Number of stores executed +system.cpu.iew.exec_rate 2.022196 # Inst execution rate +system.cpu.iew.wb_sent 94980194 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 94437031 # cumulative count of insts written-back +system.cpu.iew.wb_producers 64621172 # num instructions producing a value +system.cpu.iew.wb_consumers 90003030 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.997881 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717953 # average fanout of values written-back +system.cpu.iew.wb_rate 1.995621 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717989 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions system.cpu.commit.commitCommittedOps 91903055 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 24570867 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 24565165 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 952438 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43551528 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.110214 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.736227 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 952869 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43597575 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.107985 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.734489 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 17031202 39.11% 39.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9950887 22.85% 61.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4509538 10.35% 72.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2291714 5.26% 77.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1611645 3.70% 81.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1125442 2.58% 83.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 722499 1.66% 85.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 819642 1.88% 87.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5488959 12.60% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 17052737 39.11% 39.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9973933 22.88% 61.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4509329 10.34% 72.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2295130 5.26% 77.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1618190 3.71% 81.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1123694 2.58% 83.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 722585 1.66% 85.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 817482 1.88% 87.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5484495 12.58% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43551528 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43597575 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -311,70 +311,70 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5488959 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5484495 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 154535451 # The number of ROB reads -system.cpu.rob.rob_writes 236599608 # The number of ROB writes +system.cpu.rob.rob_reads 154580260 # The number of ROB reads +system.cpu.rob.rob_writes 236588154 # The number of ROB writes system.cpu.timesIdled 2240 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 91326 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 97064 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.561538 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.561538 # CPI: Total CPI of All Threads -system.cpu.ipc 1.780823 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.780823 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 129477590 # number of integer regfile reads -system.cpu.int_regfile_writes 70782663 # number of integer regfile writes -system.cpu.fp_regfile_reads 6191536 # number of floating regfile reads -system.cpu.fp_regfile_writes 6049328 # number of floating regfile writes -system.cpu.misc_regfile_reads 714291 # number of misc regfile reads +system.cpu.cpi 0.562156 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.562156 # CPI: Total CPI of All Threads +system.cpu.ipc 1.778865 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.778865 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 129472042 # number of integer regfile reads +system.cpu.int_regfile_writes 70778136 # number of integer regfile writes +system.cpu.fp_regfile_reads 6192217 # number of floating regfile reads +system.cpu.fp_regfile_writes 6050128 # number of floating regfile writes +system.cpu.misc_regfile_reads 714420 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 10215 # number of replacements -system.cpu.icache.tagsinuse 1600.385722 # Cycle average of tags in use -system.cpu.icache.total_refs 14937616 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 12152 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1229.231073 # Average number of references to valid blocks. +system.cpu.icache.replacements 10236 # number of replacements +system.cpu.icache.tagsinuse 1604.355346 # Cycle average of tags in use +system.cpu.icache.total_refs 14936697 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 12175 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1226.833429 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1600.385722 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.781438 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.781438 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14937616 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14937616 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14937616 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14937616 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14937616 # number of overall hits -system.cpu.icache.overall_hits::total 14937616 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13528 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 13528 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 13528 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13528 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13528 # number of overall misses -system.cpu.icache.overall_misses::total 13528 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 201479500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 201479500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 201479500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 201479500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 201479500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 201479500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14951144 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14951144 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14951144 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14951144 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14951144 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14951144 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000905 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000905 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000905 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000905 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000905 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000905 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14893.517150 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14893.517150 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14893.517150 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14893.517150 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14893.517150 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14893.517150 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1604.355346 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.783377 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.783377 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14936697 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14936697 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14936697 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14936697 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14936697 # number of overall hits +system.cpu.icache.overall_hits::total 14936697 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 13544 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 13544 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 13544 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 13544 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 13544 # number of overall misses +system.cpu.icache.overall_misses::total 13544 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 214516500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 214516500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 214516500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 214516500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 214516500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 214516500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14950241 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14950241 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14950241 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14950241 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14950241 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14950241 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000906 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000906 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000906 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000906 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000906 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000906 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15838.489368 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15838.489368 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15838.489368 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15838.489368 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15838.489368 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15838.489368 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -383,300 +383,300 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1376 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1376 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1376 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1376 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1376 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1376 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12152 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 12152 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 12152 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 12152 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 12152 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 12152 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 130219500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 130219500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 130219500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 130219500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 130219500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 130219500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000813 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000813 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000813 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000813 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000813 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000813 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10715.890388 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10715.890388 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10715.890388 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 10715.890388 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10715.890388 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 10715.890388 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1369 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1369 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1369 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1369 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1369 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1369 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12175 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 12175 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 12175 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 12175 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 12175 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 12175 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 142455000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 142455000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 142455000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 142455000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 142455000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 142455000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000814 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000814 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000814 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000814 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000814 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000814 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11700.616016 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11700.616016 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11700.616016 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11700.616016 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11700.616016 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11700.616016 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 158 # number of replacements -system.cpu.dcache.tagsinuse 1459.321585 # Cycle average of tags in use -system.cpu.dcache.total_refs 28191010 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2244 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12562.838681 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 1456.192464 # Cycle average of tags in use +system.cpu.dcache.total_refs 28189208 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2243 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12567.636202 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1459.321585 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.356280 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.356280 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 21697441 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21697441 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6493044 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6493044 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 525 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 525 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28190485 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28190485 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28190485 # number of overall hits -system.cpu.dcache.overall_hits::total 28190485 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 934 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 934 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8059 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8059 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 1456.192464 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.355516 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.355516 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 21695723 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21695723 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6493020 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6493020 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 465 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 465 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28188743 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28188743 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28188743 # number of overall hits +system.cpu.dcache.overall_hits::total 28188743 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 984 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 984 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8083 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8083 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 8993 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 8993 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 8993 # number of overall misses -system.cpu.dcache.overall_misses::total 8993 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 27907000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 27907000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 290105500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 290105500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 38000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 38000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 318012500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 318012500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 318012500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 318012500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21698375 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21698375 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9067 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9067 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9067 # number of overall misses +system.cpu.dcache.overall_misses::total 9067 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32711000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32711000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 344620000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 344620000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 45000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 45000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 377331000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 377331000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 377331000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 377331000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21696707 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21696707 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 526 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 526 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28199478 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28199478 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28199478 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28199478 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000043 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000043 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001240 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001240 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001901 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001901 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000319 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000319 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000319 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000319 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 29879.014989 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 29879.014989 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35997.704430 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35997.704430 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35362.226176 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 35362.226176 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35362.226176 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35362.226176 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1000 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 466 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28197810 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28197810 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28197810 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28197810 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001243 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001243 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002146 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002146 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000322 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000322 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000322 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000322 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33242.886179 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33242.886179 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42635.160213 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42635.160213 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 45000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 45000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41615.859711 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41615.859711 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41615.859711 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41615.859711 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 12500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 1000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12500 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 108 # number of writebacks system.cpu.dcache.writebacks::total 108 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 421 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 421 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6329 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6329 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6750 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6750 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6750 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6750 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 513 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 513 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1730 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1730 # number of WriteReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 474 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 474 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6351 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6351 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6825 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6825 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6825 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6825 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 510 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 510 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1732 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1732 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2243 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2243 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2243 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2243 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16519000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 16519000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61611500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 61611500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 35000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 35000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78130500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 78130500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78130500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 78130500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2242 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2242 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2242 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2242 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18104500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 18104500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 68881000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 68881000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 42000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 42000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 86985500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 86985500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 86985500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 86985500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.001901 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.001901 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.002146 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.002146 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32200.779727 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32200.779727 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35613.583815 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35613.583815 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 35000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 35000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34833.036112 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34833.036112 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34833.036112 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34833.036112 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35499.019608 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35499.019608 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39769.630485 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39769.630485 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 42000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 42000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38798.171276 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 38798.171276 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38798.171276 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 38798.171276 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2418.588292 # Cycle average of tags in use -system.cpu.l2cache.total_refs 9138 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3608 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.532705 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2417.634669 # Cycle average of tags in use +system.cpu.l2cache.total_refs 9160 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3606 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.540211 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.698469 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2020.214461 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 380.675363 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 17.697335 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2024.265560 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 375.671774 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000540 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.061652 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.011617 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.073809 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 9070 # number of ReadReq hits +system.cpu.l2cache.occ_percent::cpu.inst 0.061776 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.011465 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.073780 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 9092 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 54 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 9124 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 9146 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 108 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 108 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 9070 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 9092 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 80 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 9150 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 9070 # number of overall hits +system.cpu.l2cache.demand_hits::total 9172 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 9092 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 80 # number of overall hits -system.cpu.l2cache.overall_hits::total 9150 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3082 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 460 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 3542 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 1704 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1704 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3082 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2164 # number of demand (read+write) misses +system.cpu.l2cache.overall_hits::total 9172 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3083 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 457 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 3540 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1706 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1706 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3083 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2163 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 5246 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3082 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2164 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 3083 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2163 # number of overall misses system.cpu.l2cache.overall_misses::total 5246 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 105790500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 15832500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 121623000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 59198500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 59198500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 105790500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 75031000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 180821500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 105790500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 75031000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 180821500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 12152 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 514 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 12666 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 108859500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17384500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 126244000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 66352500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 66352500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 108859500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 83737000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 192596500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 108859500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 83737000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 192596500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 12175 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 511 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 12686 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 108 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 108 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1730 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1730 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 12152 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2244 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 14396 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 12152 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2244 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 14396 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.253621 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.894942 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.279646 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.984971 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.984971 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.253621 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.964349 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.364407 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.253621 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.964349 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.364407 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34325.275795 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34418.478261 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34337.380011 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34740.903756 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34740.903756 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34325.275795 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34672.365989 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34468.452154 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34325.275795 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34672.365989 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34468.452154 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1732 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1732 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 12175 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2243 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 14418 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 12175 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2243 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 14418 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.253224 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.894325 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.279048 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.984988 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.984988 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.253224 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.964333 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.363851 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.253224 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.964333 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.363851 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35309.601038 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38040.481400 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 35662.146893 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38893.610785 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38893.610785 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35309.601038 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 38713.361073 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 36713.019443 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35309.601038 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38713.361073 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 36713.019443 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 7500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 7500 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3082 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 460 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3542 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1704 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1704 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3082 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2164 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3083 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 457 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3540 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1706 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1706 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3083 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2163 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 5246 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3082 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2164 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3083 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2163 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5246 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 95761000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14382500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 110143500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53772000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53772000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 95761000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 68154500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 163915500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 95761000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 68154500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 163915500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.253621 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.894942 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.279646 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984971 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984971 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.253621 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964349 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.364407 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.253621 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964349 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.364407 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31071.057755 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31266.304348 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31096.414455 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31556.338028 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31556.338028 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31071.057755 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31494.685767 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31245.806329 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31071.057755 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31494.685767 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31245.806329 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 98880000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15955500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 114835500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60925000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60925000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 98880000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 76880500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 175760500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 98880000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 76880500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 175760500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.253224 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.894325 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.279048 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984988 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984988 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.253224 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964333 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.363851 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.253224 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964333 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.363851 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32072.656503 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34913.566740 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32439.406780 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35712.192263 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35712.192263 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32072.656503 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35543.458160 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33503.717118 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32072.656503 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35543.458160 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33503.717118 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini index 7fbc3a2c7..218e77206 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -148,7 +148,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -180,7 +180,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout index 0bb9be5b6..86e423df3 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:47:30 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 10:59:12 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing +Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing/smred.sav +Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -21,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 118740049000 because target called exit() +122 123 124 Exiting @ tick 118779533000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index b947ca514..d3e99f110 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.118740 # Number of seconds simulated -sim_ticks 118740049000 # Number of ticks simulated -final_tick 118740049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.118780 # Number of seconds simulated +sim_ticks 118779533000 # Number of ticks simulated +final_tick 118779533000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2205371 # Simulator instruction rate (inst/s) -host_op_rate 2205370 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2849367775 # Simulator tick rate (ticks/s) -host_mem_usage 222752 # Number of bytes of host memory used -host_seconds 41.67 # Real time elapsed on the host +host_inst_rate 1503058 # Simulator instruction rate (inst/s) +host_op_rate 1503057 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1942616372 # Simulator tick rate (ticks/s) +host_mem_usage 222720 # Number of bytes of host memory used +host_seconds 61.14 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 167744 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 167744 # Nu system.physmem.num_reads::cpu.inst 2621 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::total 4765 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1412699 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1155600 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2568299 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1412699 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1412699 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1412699 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1155600 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2568299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1412230 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1155216 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2567446 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1412230 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1412230 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1412230 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1155216 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2567446 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -60,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 237480098 # number of cpu cycles simulated +system.cpu.numCycles 237559066 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 91903056 # Number of instructions committed @@ -79,18 +79,18 @@ system.cpu.num_mem_refs 26497334 # nu system.cpu.num_load_insts 19996208 # Number of load instructions system.cpu.num_store_insts 6501126 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 237480098 # Number of busy cycles +system.cpu.num_busy_cycles 237559066 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 6681 # number of replacements -system.cpu.icache.tagsinuse 1418.037996 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1417.992791 # Cycle average of tags in use system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 10798.423032 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1418.037996 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.692401 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.692401 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1417.992791 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.692379 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.692379 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 91894580 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 91894580 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 91894580 # number of demand (read+write) hits @@ -103,12 +103,12 @@ system.cpu.icache.demand_misses::cpu.inst 8510 # n system.cpu.icache.demand_misses::total 8510 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 8510 # number of overall misses system.cpu.icache.overall_misses::total 8510 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 229222000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 229222000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 229222000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 229222000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 229222000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 229222000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 229226000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 229226000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 229226000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 229226000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 229226000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 229226000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 91903090 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 91903090 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 91903090 # number of demand (read+write) accesses @@ -121,12 +121,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26935.605170 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 26935.605170 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 26935.605170 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 26935.605170 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 26935.605170 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 26935.605170 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26936.075206 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 26936.075206 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 26936.075206 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 26936.075206 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 26936.075206 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 26936.075206 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -141,34 +141,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 8510 system.cpu.icache.demand_mshr_misses::total 8510 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 8510 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 8510 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 203692000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 203692000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 203692000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 203692000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 203692000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 203692000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 203696000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 203696000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 203696000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 203696000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 203696000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 203696000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000093 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000093 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23935.605170 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23935.605170 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23936.075206 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23936.075206 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23936.075206 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 23936.075206 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23936.075206 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 23936.075206 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1442.028823 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1441.982871 # Cycle average of tags in use system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1442.028823 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.352058 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.352058 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 1441.982871 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.352047 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.352047 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits @@ -185,14 +185,14 @@ system.cpu.dcache.demand_misses::cpu.data 2223 # n system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses system.cpu.dcache.overall_misses::total 2223 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24374000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24374000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24380000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24380000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 96796000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 96796000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 121170000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 121170000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 121170000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 121170000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 121176000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 121176000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 121176000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 121176000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -209,14 +209,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51313.684211 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51313.684211 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51326.315789 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51326.315789 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55375.286041 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 55375.286041 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54507.422402 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54507.422402 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54507.422402 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54507.422402 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54510.121457 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54510.121457 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54510.121457 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54510.121457 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -235,14 +235,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22949000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 22949000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22955000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 22955000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 91552000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 91552000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114501000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 114501000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114501000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 114501000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114507000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 114507000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114507000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 114507000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -251,28 +251,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48313.684211 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48313.684211 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48326.315789 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48326.315789 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52375.286041 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52375.286041 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51510.121457 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51510.121457 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51510.121457 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51510.121457 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2074.048594 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2073.981313 # Cycle average of tags in use system.cpu.l2cache.total_refs 5956 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3109 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 1.915729 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.795183 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1704.999565 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 351.253845 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 17.795350 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1704.943449 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 351.242515 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.052032 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.052031 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.010719 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.063295 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.063293 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 5889 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 5942 # number of ReadReq hits |