diff options
author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-20 17:18:53 -0400 |
---|---|---|
committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-20 17:18:53 -0400 |
commit | c4e91289ae8806eb051fb1f41ece8be308f0ff85 (patch) | |
tree | 6f35a7725cfd4072c8516ee0bb2ae799d48ce896 /tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt | |
parent | cc6523e2d686447f90acccac20c0fb2940dc3e3b (diff) | |
download | gem5-c4e91289ae8806eb051fb1f41ece8be308f0ff85.tar.xz |
stats: Bump stats for filter, crossbar and config changes
This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.
Diffstat (limited to 'tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt')
-rw-r--r-- | tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt | 277 |
1 files changed, 149 insertions, 128 deletions
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index 414b5b5a9..997617f78 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.131652 # Nu sim_ticks 131652469500 # Number of ticks simulated final_tick 131652469500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 235317 # Simulator instruction rate (inst/s) -host_op_rate 248063 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 179784828 # Simulator tick rate (ticks/s) -host_mem_usage 321352 # Number of bytes of host memory used -host_seconds 732.28 # Real time elapsed on the host +host_inst_rate 246188 # Simulator instruction rate (inst/s) +host_op_rate 259522 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 188090070 # Simulator tick rate (ticks/s) +host_mem_usage 311300 # Number of bytes of host memory used +host_seconds 699.94 # Real time elapsed on the host sim_insts 172317809 # Number of instructions simulated sim_ops 181650742 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -86,8 +86,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3617 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 240 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3616 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 241 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -182,26 +182,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 903 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 272.372093 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.073064 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 280.203163 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 262 29.01% 29.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 352 38.98% 68.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 86 9.52% 77.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 48 5.32% 82.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 35 3.88% 86.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 23 2.55% 89.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 17 1.88% 91.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 16 1.77% 92.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 64 7.09% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 903 # Bytes accessed per row activation -system.physmem.totQLat 27589000 # Total ticks spent queuing -system.physmem.totMemAccLat 100132750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 904 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 272.070796 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.793599 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 280.048713 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 264 29.20% 29.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 351 38.83% 68.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 86 9.51% 77.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 48 5.31% 82.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 35 3.87% 86.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 23 2.54% 89.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 17 1.88% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 16 1.77% 92.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 64 7.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 904 # Bytes accessed per row activation +system.physmem.totQLat 27698500 # Total ticks spent queuing +system.physmem.totMemAccLat 100242250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 19345000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7130.78 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7159.09 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25880.78 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25909.09 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s @@ -212,31 +212,39 @@ system.physmem.busUtilRead 0.01 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 2961 # Number of row buffer hits during reads +system.physmem.readRowHits 2960 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.53 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.51 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 34027495.86 # Average gap between requests -system.physmem.pageHitRate 76.53 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 125800689500 # Time in different power states +system.physmem.pageHitRate 76.51 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 125800686500 # Time in different power states system.physmem.memoryStateTime::REF 4396080000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1453432500 # Time in different power states +system.physmem.memoryStateTime::ACT 1453435500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1880831 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 2779 # Transaction distribution system.membus.trans_dist::ReadResp 2779 # Transaction distribution system.membus.trans_dist::ReadExReq 1090 # Transaction distribution system.membus.trans_dist::ReadExResp 1090 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7738 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 7738 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247616 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 247616 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 247616 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 247616 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 3869 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 3869 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 3869 # Request fanout histogram system.membus.reqLayer0.occupancy 4528000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 36223250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 36225250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 49915423 # Number of BP lookups @@ -345,12 +353,12 @@ system.cpu.ipc 0.654442 # IP system.cpu.tickCycles 255940225 # Number of cycles that the object actually ticked system.cpu.idleCycles 7364714 # Total number of cycles that the object has spent stopped system.cpu.icache.tags.replacements 2881 # number of replacements -system.cpu.icache.tags.tagsinuse 1424.983797 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1424.983856 # Cycle average of tags in use system.cpu.icache.tags.total_refs 71509873 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4678 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 15286.420051 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1424.983797 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1424.983856 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.695793 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.695793 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id @@ -374,12 +382,12 @@ system.cpu.icache.demand_misses::cpu.inst 4679 # n system.cpu.icache.demand_misses::total 4679 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 4679 # number of overall misses system.cpu.icache.overall_misses::total 4679 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 184764496 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 184764496 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 184764496 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 184764496 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 184764496 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 184764496 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 184816496 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 184816496 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 184816496 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 184816496 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 184816496 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 184816496 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 71514552 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 71514552 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 71514552 # number of demand (read+write) accesses @@ -392,12 +400,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000065 system.cpu.icache.demand_miss_rate::total 0.000065 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000065 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000065 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39488.030776 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 39488.030776 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 39488.030776 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 39488.030776 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 39488.030776 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 39488.030776 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39499.144262 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 39499.144262 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 39499.144262 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 39499.144262 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 39499.144262 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 39499.144262 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -412,26 +420,25 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4679 system.cpu.icache.demand_mshr_misses::total 4679 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4679 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4679 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 174487504 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 174487504 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 174487504 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 174487504 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 174487504 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 174487504 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 174539504 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 174539504 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 174539504 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 174539504 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 174539504 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 174539504 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000065 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000065 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000065 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37291.622996 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37291.622996 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37291.622996 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37291.622996 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37291.622996 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37291.622996 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37302.736482 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37302.736482 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37302.736482 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 37302.736482 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37302.736482 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 37302.736482 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 3161293 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 5390 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 5389 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution @@ -440,11 +447,25 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9357 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3634 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 12991 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 299392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116800 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 416192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 416192 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 299392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116800 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 416192 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 6504 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 6504 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 6504 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 3268000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 7477496 # Layer occupancy (ticks) @@ -452,13 +473,13 @@ system.cpu.toL2Bus.respLayer0.utilization 0.0 # L system.cpu.toL2Bus.respLayer1.occupancy 2996735 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2001.642880 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2001.642948 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2592 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2787 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.930032 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 3.028976 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1998.613905 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1998.613972 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.060993 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.061085 # Average percentage of cache occupancy @@ -489,14 +510,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 3889 # system.cpu.l2cache.demand_misses::total 3889 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 3889 # number of overall misses system.cpu.l2cache.overall_misses::total 3889 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 190654250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 190654250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 75964500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 75964500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 266618750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 266618750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 266618750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 266618750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 190706250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 190706250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 75951500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 75951500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 266657750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 266657750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 266657750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 266657750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 5390 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 5390 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) @@ -515,14 +536,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.599414 system.cpu.l2cache.demand_miss_rate::total 0.599414 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.599414 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.599414 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68115.130404 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68115.130404 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69692.201835 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69692.201835 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68557.148367 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68557.148367 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68557.148367 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68557.148367 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68133.708467 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68133.708467 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69680.275229 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69680.275229 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68567.176652 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68567.176652 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68567.176652 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68567.176652 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -545,14 +566,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 3870 system.cpu.l2cache.demand_mshr_misses::total 3870 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 3870 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3870 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 154631750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 154631750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 62298500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62298500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 216930250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 216930250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 216930250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 216930250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 154681250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 154681250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 62286000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62286000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 216967250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 216967250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 216967250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 216967250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.515770 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.515770 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.992714 # mshr miss rate for ReadExReq accesses @@ -561,22 +582,22 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.596486 system.cpu.l2cache.demand_mshr_miss_rate::total 0.596486 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.596486 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.596486 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55622.931655 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55622.931655 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57154.587156 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57154.587156 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56054.328165 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56054.328165 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56054.328165 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56054.328165 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55640.737410 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55640.737410 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57143.119266 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57143.119266 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56063.888889 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56063.888889 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56063.888889 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56063.888889 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1376.810162 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1376.810186 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 40745471 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1809 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 22523.754008 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 1376.810162 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 1376.810186 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.336135 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.336135 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1767 # Occupied blocks per task id @@ -610,12 +631,12 @@ system.cpu.dcache.overall_misses::cpu.inst 2411 # system.cpu.dcache.overall_misses::total 2411 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.inst 52005983 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 52005983 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 115778750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 115778750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 167784733 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 167784733 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 167784733 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 167784733 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 115743750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 115743750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 167749733 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 167749733 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 167749733 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 167749733 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 28338781 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 28338781 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 12364287 # number of WriteReq accesses(hits+misses) @@ -638,12 +659,12 @@ system.cpu.dcache.overall_miss_rate::cpu.inst 0.000059 system.cpu.dcache.overall_miss_rate::total 0.000059 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 67804.410691 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 67804.410691 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70425.030414 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70425.030414 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69591.345085 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69591.345085 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69591.345085 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69591.345085 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70403.740876 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70403.740876 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69576.828287 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69576.828287 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69576.828287 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69576.828287 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -672,12 +693,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.inst 1809 system.cpu.dcache.overall_mshr_misses::total 1809 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 47475265 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 47475265 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77144500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 77144500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 124619765 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 124619765 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 124619765 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 124619765 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77131500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 77131500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 124606765 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 124606765 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 124606765 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 124606765 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000089 # mshr miss rate for WriteReq accesses @@ -688,12 +709,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000044 system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66772.524613 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66772.524613 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70259.107468 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70259.107468 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68888.758983 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68888.758983 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68888.758983 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68888.758983 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70247.267760 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70247.267760 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68881.572692 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68881.572692 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68881.572692 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68881.572692 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |