diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-10-19 06:20:04 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-10-19 06:20:04 -0400 |
| commit | 607c2772915628c2c67c1c5bfdefaa33ae66a06e (patch) | |
| tree | f8f23fd4012f9a0053d65ac91792a7dc61d6baff /tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt | |
| parent | 71c982ff708cc3adc7c0eccf536fea34c20cc5f0 (diff) | |
| download | gem5-607c2772915628c2c67c1c5bfdefaa33ae66a06e.tar.xz | |
stats: Update stats to reflect recent changes to floats
Mostly just splitting out the floats ops and corresponding
reads/writes.
Diffstat (limited to 'tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt')
| -rw-r--r-- | tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt | 18 |
1 files changed, 11 insertions, 7 deletions
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index 26e7200e9..f4cf26547 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.132539 # Nu sim_ticks 132538562500 # Number of ticks simulated final_tick 132538562500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 171463 # Simulator instruction rate (inst/s) -host_op_rate 180750 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 131881088 # Simulator tick rate (ticks/s) -host_mem_usage 273644 # Number of bytes of host memory used -host_seconds 1004.99 # Real time elapsed on the host +host_inst_rate 360845 # Simulator instruction rate (inst/s) +host_op_rate 380389 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 277544932 # Simulator tick rate (ticks/s) +host_mem_usage 274852 # Number of bytes of host memory used +host_seconds 477.54 # Real time elapsed on the host sim_insts 172317810 # Number of instructions simulated sim_ops 181650743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -415,7 +415,9 @@ system.cpu.op_class_0::FloatAdd 0 0.00% 77.01% # Cl system.cpu.op_class_0::FloatCmp 0 0.00% 77.01% # Class of committed instruction system.cpu.op_class_0::FloatCvt 0 0.00% 77.01% # Class of committed instruction system.cpu.op_class_0::FloatMult 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 77.01% # Class of committed instruction system.cpu.op_class_0::FloatDiv 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 77.01% # Class of committed instruction system.cpu.op_class_0::FloatSqrt 0 0.00% 77.01% # Class of committed instruction system.cpu.op_class_0::SimdAdd 0 0.00% 77.01% # Class of committed instruction system.cpu.op_class_0::SimdAddAcc 0 0.00% 77.01% # Class of committed instruction @@ -437,8 +439,10 @@ system.cpu.op_class_0::SimdFloatMisc 437591 0.24% 77.53% # Cl system.cpu.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction -system.cpu.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction -system.cpu.op_class_0::MemWrite 12644635 6.96% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemRead 27348059 15.06% 92.74% # Class of committed instruction +system.cpu.op_class_0::MemWrite 12498389 6.88% 99.62% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 548085 0.30% 99.92% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 146246 0.08% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 181650743 # Class of committed instruction |