diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
| commit | 25e1b1c1f5f4e0ad3976c88998161700135f4aae (patch) | |
| tree | 36e668b99a36c3dfcfefc157d7bd6b102b8f8af6 /tests/long/se/70.twolf/ref/arm/linux/minor-timing | |
| parent | 7e711c98f8fcd949b9430bbf243d60348d0ef28b (diff) | |
| download | gem5-25e1b1c1f5f4e0ad3976c88998161700135f4aae.tar.xz | |
stats: Update stats for cache, crossbar and DRAM changes
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.
Needless to say, almost every regression is affected.
Diffstat (limited to 'tests/long/se/70.twolf/ref/arm/linux/minor-timing')
| -rw-r--r-- | tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt | 563 |
1 files changed, 288 insertions, 275 deletions
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index d21841628..f9aa76ee3 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.131586 # Number of seconds simulated -sim_ticks 131586268500 # Number of ticks simulated -final_tick 131586268500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.131585 # Number of seconds simulated +sim_ticks 131584694500 # Number of ticks simulated +final_tick 131584694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 246297 # Simulator instruction rate (inst/s) -host_op_rate 259636 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 188078312 # Simulator tick rate (ticks/s) -host_mem_usage 317920 # Number of bytes of host memory used -host_seconds 699.64 # Real time elapsed on the host +host_inst_rate 242795 # Simulator instruction rate (inst/s) +host_op_rate 255945 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 185402255 # Simulator tick rate (ticks/s) +host_mem_usage 318276 # Number of bytes of host memory used +host_seconds 709.73 # Real time elapsed on the host sim_insts 172317810 # Number of instructions simulated sim_ops 181650743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 138368 # Nu system.physmem.num_reads::cpu.inst 2162 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory system.physmem.num_reads::total 3870 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1051538 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 830725 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1882263 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1051538 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1051538 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1051538 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 830725 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1882263 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1051551 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 830735 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1882286 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1051551 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1051551 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1051551 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 830735 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1882286 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 3870 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 3870 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 131586174000 # Total gap between requests +system.physmem.totGap 131584601000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 901 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 272.834628 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 180.187503 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 278.027106 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 257 28.52% 28.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 352 39.07% 67.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 83 9.21% 76.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 53 5.88% 82.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 41 4.55% 87.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 20 2.22% 89.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 17 1.89% 91.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 20 2.22% 93.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 58 6.44% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 901 # Bytes accessed per row activation -system.physmem.totQLat 26462250 # Total ticks spent queuing -system.physmem.totMemAccLat 99024750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 912 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 269.614035 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.051598 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 274.679496 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 270 29.61% 29.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 347 38.05% 67.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 87 9.54% 77.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 54 5.92% 83.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 40 4.39% 87.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 20 2.19% 89.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 18 1.97% 91.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 19 2.08% 93.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 57 6.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 912 # Bytes accessed per row activation +system.physmem.totQLat 27229750 # Total ticks spent queuing +system.physmem.totMemAccLat 99792250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 19350000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6837.79 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7036.11 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25587.79 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25786.11 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s @@ -216,47 +216,47 @@ system.physmem.busUtilRead 0.01 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 2963 # Number of row buffer hits during reads +system.physmem.readRowHits 2952 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.56 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.28 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34001595.35 # Average gap between requests -system.physmem.pageHitRate 76.56 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3107160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1695375 # Energy for precharge commands per rank (pJ) +system.physmem.avgGap 34001188.89 # Average gap between requests +system.physmem.pageHitRate 76.28 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3129840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1707750 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 16177200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 8594155440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3588895845 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 75799905000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 88003936020 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.824061 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 126101706500 # Time in different power states +system.physmem_0.actBackEnergy 3579629355 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 75808025250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 88002824835 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.815686 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 126113612750 # Time in different power states system.physmem_0.memoryStateTime::REF 4393740000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1088502500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1075043250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3689280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2013000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 13767000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3749760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2046000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13774800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 8594155440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3567061710 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 75819057750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 87999744180 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.792204 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 126130418250 # Time in different power states +system.physmem_1.actBackEnergy 3571830900 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 75814874250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 88000431150 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.797424 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 126123074750 # Time in different power states system.physmem_1.memoryStateTime::REF 4393740000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1056288250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1063297750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 49889699 # Number of BP lookups -system.cpu.branchPred.condPredicted 39633555 # Number of conditional branches predicted +system.cpu.branchPred.lookups 49889701 # Number of BP lookups +system.cpu.branchPred.condPredicted 39633557 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 5745356 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24337780 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 24337782 # Number of BTB lookups system.cpu.branchPred.BTBHits 23279998 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.653745 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 95.653737 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1903300 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 140 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -377,26 +377,26 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 263172537 # number of cpu cycles simulated +system.cpu.numCycles 263169389 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 172317810 # Number of instructions committed system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed -system.cpu.discardedOps 11983755 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 11983759 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.527251 # CPI: cycles per instruction -system.cpu.ipc 0.654771 # IPC: instructions per cycle -system.cpu.tickCycles 256740434 # Number of cycles that the object actually ticked -system.cpu.idleCycles 6432103 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.527233 # CPI: cycles per instruction +system.cpu.ipc 0.654779 # IPC: instructions per cycle +system.cpu.tickCycles 256740818 # Number of cycles that the object actually ticked +system.cpu.idleCycles 6428571 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1377.700648 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40793912 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1377.711326 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40793911 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22538.072928 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22538.072376 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1377.700648 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.336353 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.336353 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1377.711326 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.336355 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.336355 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id @@ -408,36 +408,36 @@ system.cpu.dcache.tags.tag_accesses 81594514 # Nu system.cpu.dcache.tags.data_accesses 81594514 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 28385993 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 28385993 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12362641 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12362641 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12362640 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12362640 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 464 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 464 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40748634 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40748634 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40749098 # number of overall hits -system.cpu.dcache.overall_hits::total 40749098 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 40748633 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40748633 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40749097 # number of overall hits +system.cpu.dcache.overall_hits::total 40749097 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 793 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 793 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1646 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1646 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1647 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1647 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 2439 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2439 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2440 # number of overall misses -system.cpu.dcache.overall_misses::total 2440 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57815734 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57815734 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 126489000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 126489000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 184304734 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 184304734 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 184304734 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 184304734 # number of overall miss cycles +system.cpu.dcache.demand_misses::cpu.data 2440 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2440 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2441 # number of overall misses +system.cpu.dcache.overall_misses::total 2441 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57382000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57382000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 126740000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 126740000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 184122000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 184122000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 184122000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 184122000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 28386786 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 28386786 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) @@ -462,14 +462,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72907.609079 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72907.609079 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76846.294046 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76846.294046 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 75565.696597 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 75565.696597 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 75534.727049 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 75534.727049 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72360.655738 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72360.655738 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76952.034001 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76952.034001 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 75459.836066 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 75459.836066 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 75428.922573 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 75428.922573 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -482,12 +482,12 @@ system.cpu.dcache.writebacks::writebacks 16 # nu system.cpu.dcache.writebacks::total 16 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 82 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 548 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 548 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 630 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 630 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 630 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 630 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 549 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 549 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 631 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 631 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 631 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 631 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1098 # number of WriteReq MSHR misses @@ -498,16 +498,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1809 system.cpu.dcache.demand_mshr_misses::total 1809 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1810 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51168764 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 51168764 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84319000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 84319000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 69500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 69500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 135487764 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 135487764 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 135557264 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 135557264 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51034000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 51034000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85245500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85245500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 70000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 70000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136279500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 136279500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136349500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 136349500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses @@ -518,26 +518,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71967.319269 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71967.319269 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76793.260474 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76793.260474 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 69500 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 69500 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74896.497512 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74896.497512 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74893.516022 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74893.516022 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71777.777778 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71777.777778 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77637.067395 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77637.067395 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75334.162521 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75334.162521 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75331.215470 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75331.215470 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2889 # number of replacements -system.cpu.icache.tags.tagsinuse 1425.913177 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 71538503 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1425.919952 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 71538505 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4687 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 15263.175379 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 15263.175805 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1425.913177 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.696247 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.696247 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1425.919952 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.696250 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.696250 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1798 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id @@ -545,44 +545,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 493 system.cpu.icache.tags.age_task_id_blocks_1024::3 125 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1069 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.877930 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 143091069 # Number of tag accesses -system.cpu.icache.tags.data_accesses 143091069 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 71538503 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 71538503 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 71538503 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 71538503 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 71538503 # number of overall hits -system.cpu.icache.overall_hits::total 71538503 # number of overall hits +system.cpu.icache.tags.tag_accesses 143091073 # Number of tag accesses +system.cpu.icache.tags.data_accesses 143091073 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 71538505 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 71538505 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 71538505 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 71538505 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 71538505 # number of overall hits +system.cpu.icache.overall_hits::total 71538505 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 4688 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 4688 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 4688 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 4688 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 4688 # number of overall misses system.cpu.icache.overall_misses::total 4688 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 200735747 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 200735747 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 200735747 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 200735747 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 200735747 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 200735747 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 71543191 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 71543191 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 71543191 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 71543191 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 71543191 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 71543191 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 199914000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 199914000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 199914000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 199914000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 199914000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 199914000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 71543193 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 71543193 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 71543193 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 71543193 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 71543193 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 71543193 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42819.058660 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42819.058660 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42819.058660 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42819.058660 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42819.058660 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42819.058660 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42643.771331 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42643.771331 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42643.771331 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42643.771331 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42643.771331 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42643.771331 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -597,117 +597,123 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4688 system.cpu.icache.demand_mshr_misses::total 4688 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4688 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4688 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192780753 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 192780753 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192780753 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 192780753 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192780753 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 192780753 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 195227000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 195227000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 195227000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 195227000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 195227000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 195227000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41122.174275 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41122.174275 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41122.174275 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 41122.174275 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41122.174275 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 41122.174275 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41643.984642 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41643.984642 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41643.984642 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 41643.984642 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41643.984642 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 41643.984642 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2002.534339 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2603 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2002.545063 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5192 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2788 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.933644 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.862267 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 3.029198 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1508.688891 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 490.816250 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 3.029187 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1508.695895 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 490.819981 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046042 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.014979 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.061112 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.061113 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 2788 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 522 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 155 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 523 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 154 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2006 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.085083 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 55998 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 55998 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2522 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 80 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2602 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 76702 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 76702 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2522 # number of demand (read+write) hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2523 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 2523 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 80 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 80 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2523 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 88 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2610 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2522 # number of overall hits +system.cpu.l2cache.demand_hits::total 2611 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2523 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 88 # number of overall hits -system.cpu.l2cache.overall_hits::total 2610 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2166 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 632 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 2798 # number of ReadReq misses +system.cpu.l2cache.overall_hits::total 2611 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 1090 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 1090 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2166 # number of demand (read+write) misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2165 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2165 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 632 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 632 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2165 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 1722 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 3888 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2166 # number of overall misses +system.cpu.l2cache.demand_misses::total 3887 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2165 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1722 # number of overall misses -system.cpu.l2cache.overall_misses::total 3888 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 161612750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 49681750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 211294500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 83135500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 83135500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 161612750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 132817250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 294430000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 161612750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 132817250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 294430000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 4688 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 712 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 5400 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 3887 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 83513000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 83513000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 161704000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 161704000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49184000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 49184000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 161704000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 132697000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 294401000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 161704000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 132697000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 294401000 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1098 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1098 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4688 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 4688 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 712 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 4688 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 1810 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 6498 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 4688 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 1810 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 6498 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.462031 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.887640 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.518148 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992714 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.992714 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.462031 # miss rate for demand accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.461817 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.461817 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.887640 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.887640 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.461817 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.951381 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.598338 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.462031 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.598184 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461817 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.951381 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.598338 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74613.457987 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78610.363924 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75516.261615 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76271.100917 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76271.100917 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74613.457987 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77129.645761 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75727.880658 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74613.457987 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77129.645761 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75727.880658 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.598184 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76617.431193 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76617.431193 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74690.069284 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74690.069284 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77822.784810 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77822.784810 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74690.069284 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77059.814170 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75739.902238 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74690.069284 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77059.814170 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75739.902238 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -716,93 +722,100 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 14 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 14 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 14 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2163 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 618 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2781 # number of ReadReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1090 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1090 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2163 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2163 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 618 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 618 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2163 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 1708 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 3871 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2163 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3871 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134379750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 40985000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 175364750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69507000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69507000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134379750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 110492000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 244871750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134379750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 110492000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 244871750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.461391 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867978 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.515000 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 72613000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 72613000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 139936000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 139936000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 42042000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 42042000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 139936000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 114655000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 254591000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139936000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 114655000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 254591000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992714 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.461391 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.461391 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.867978 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.867978 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461391 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.595722 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461391 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.595722 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62126.560333 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66318.770227 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63058.162531 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63767.889908 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63767.889908 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62126.560333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64690.866511 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63258.008267 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62126.560333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64690.866511 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63258.008267 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66617.431193 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66617.431193 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64695.330559 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64695.330559 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68029.126214 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68029.126214 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64695.330559 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67128.220141 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65768.793593 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64695.330559 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67128.220141 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65768.793593 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 5400 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 5399 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2588 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9375 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3636 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 13011 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 4688 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 712 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11943 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3656 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 15599 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 299968 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 416832 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6514 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 9429 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 6514 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 9429 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6514 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3273000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 9429 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4730500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7492747 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7031498 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3019736 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2721986 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 2780 # Transaction distribution system.membus.trans_dist::ReadResp 2780 # Transaction distribution system.membus.trans_dist::ReadExReq 1090 # Transaction distribution system.membus.trans_dist::ReadExResp 1090 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 2780 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7740 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 7740 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247680 # Cumulative packet size per connected master and slave (bytes) @@ -818,9 +831,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 3870 # Request fanout histogram -system.membus.reqLayer0.occupancy 4535500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4532500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 20561750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20566750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |