diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
| commit | 8909843a76c723cb9d8a0b1394eeeba4d7abadb1 (patch) | |
| tree | 446fe188000e814cbc7d23075428cab7f44868d1 /tests/long/se/70.twolf/ref/arm/linux/minor-timing | |
| parent | fc315901ff4aaae0f56c4c1b1c50ffe9bd70b4d6 (diff) | |
| download | gem5-8909843a76c723cb9d8a0b1394eeeba4d7abadb1.tar.xz | |
stats: Update stats to reflect cache and interconnect changes
This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
Diffstat (limited to 'tests/long/se/70.twolf/ref/arm/linux/minor-timing')
| -rw-r--r-- | tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt | 720 |
1 files changed, 359 insertions, 361 deletions
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index c2d632546..f13570e98 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.131746 # Number of seconds simulated -sim_ticks 131745950000 # Number of ticks simulated -final_tick 131745950000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.131756 # Number of seconds simulated +sim_ticks 131756455500 # Number of ticks simulated +final_tick 131756455500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 165378 # Simulator instruction rate (inst/s) -host_op_rate 174335 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 126440065 # Simulator tick rate (ticks/s) -host_mem_usage 304748 # Number of bytes of host memory used -host_seconds 1041.96 # Real time elapsed on the host +host_inst_rate 249754 # Simulator instruction rate (inst/s) +host_op_rate 263281 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 190965456 # Simulator tick rate (ticks/s) +host_mem_usage 316672 # Number of bytes of host memory used +host_seconds 689.95 # Real time elapsed on the host sim_insts 172317809 # Number of instructions simulated sim_ops 181650742 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 138176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 138304 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory -system.physmem.bytes_read::total 247488 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 138176 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 138176 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2159 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 247616 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 138304 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 138304 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2161 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3867 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1048806 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 829718 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1878525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1048806 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1048806 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1048806 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 829718 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1878525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3867 # Number of read requests accepted +system.physmem.num_reads::total 3869 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1049694 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 829652 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1879346 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1049694 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1049694 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1049694 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 829652 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1879346 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3869 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 3867 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 3869 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 247488 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 247616 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 247488 # Total read bytes from the system interface side +system.physmem.bytesReadSys 247616 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -45,18 +45,18 @@ system.physmem.perBankRdBursts::0 305 # Pe system.physmem.perBankRdBursts::1 217 # Per bank write bursts system.physmem.perBankRdBursts::2 135 # Per bank write bursts system.physmem.perBankRdBursts::3 313 # Per bank write bursts -system.physmem.perBankRdBursts::4 308 # Per bank write bursts +system.physmem.perBankRdBursts::4 307 # Per bank write bursts system.physmem.perBankRdBursts::5 305 # Per bank write bursts system.physmem.perBankRdBursts::6 273 # Per bank write bursts system.physmem.perBankRdBursts::7 222 # Per bank write bursts system.physmem.perBankRdBursts::8 249 # Per bank write bursts system.physmem.perBankRdBursts::9 218 # Per bank write bursts system.physmem.perBankRdBursts::10 295 # Per bank write bursts -system.physmem.perBankRdBursts::11 199 # Per bank write bursts +system.physmem.perBankRdBursts::11 201 # Per bank write bursts system.physmem.perBankRdBursts::12 183 # Per bank write bursts system.physmem.perBankRdBursts::13 218 # Per bank write bursts system.physmem.perBankRdBursts::14 224 # Per bank write bursts -system.physmem.perBankRdBursts::15 203 # Per bank write bursts +system.physmem.perBankRdBursts::15 204 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 131745861500 # Total gap between requests +system.physmem.totGap 131756361000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 3867 # Read request sizes (log2) +system.physmem.readPktSize::6 3869 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,7 +90,7 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3616 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3618 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 238 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 912 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 269.543860 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 178.691365 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 273.658023 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 266 29.17% 29.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 353 38.71% 67.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 82 8.99% 76.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 61 6.69% 83.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 33 3.62% 87.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 27 2.96% 90.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 14 1.54% 91.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 19 2.08% 93.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 57 6.25% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 912 # Bytes accessed per row activation -system.physmem.totQLat 28130750 # Total ticks spent queuing -system.physmem.totMemAccLat 100637000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 19335000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7274.57 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 895 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 274.663687 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.028895 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 274.690311 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 245 27.37% 27.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 357 39.89% 67.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 81 9.05% 76.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 51 5.70% 82.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 43 4.80% 86.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 26 2.91% 89.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 22 2.46% 92.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 16 1.79% 93.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 54 6.03% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 895 # Bytes accessed per row activation +system.physmem.totQLat 26801000 # Total ticks spent queuing +system.physmem.totMemAccLat 99344750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 19345000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6927.11 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26024.57 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25677.11 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s @@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.01 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 2950 # Number of row buffer hits during reads +system.physmem.readRowHits 2968 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.29 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.71 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34069268.55 # Average gap between requests -system.physmem.pageHitRate 76.29 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3092040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1687125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 16177200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 34054370.90 # Average gap between requests +system.physmem.pageHitRate 76.71 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3069360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1674750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16169400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 8604835200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3575900700 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 75909402750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 88111095015 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.807422 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 126280313250 # Time in different power states -system.physmem_0.memoryStateTime::REF 4399200000 # Time in different power states +system.physmem_0.refreshEnergy 8605343760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3539588850 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 75945927000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 88111773120 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.773044 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 126343733250 # Time in different power states +system.physmem_0.memoryStateTime::REF 4399460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1064296750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1010942750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3787560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2066625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 13767000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3681720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2008875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13774800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 8604835200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3595739265 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 75892008750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 88112204400 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.815773 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 126251429250 # Time in different power states -system.physmem_1.memoryStateTime::REF 4399200000 # Time in different power states +system.physmem_1.refreshEnergy 8605343760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3587668065 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 75903760500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 88116237720 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.806861 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 126271447000 # Time in different power states +system.physmem_1.memoryStateTime::REF 4399460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1093059250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1080937500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 49935043 # Number of BP lookups -system.cpu.branchPred.condPredicted 39664695 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5744224 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24405530 # Number of BTB lookups -system.cpu.branchPred.BTBHits 23309445 # Number of BTB hits +system.cpu.branchPred.lookups 49934480 # Number of BP lookups +system.cpu.branchPred.condPredicted 39666708 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5743450 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 24374232 # Number of BTB lookups +system.cpu.branchPred.BTBHits 23299942 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.508866 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1908457 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 95.592518 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1908561 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 139 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -377,75 +377,75 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 263491900 # number of cpu cycles simulated +system.cpu.numCycles 263512911 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 172317809 # Number of instructions committed system.cpu.committedOps 181650742 # Number of ops (including micro ops) committed -system.cpu.discardedOps 11758002 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 11759003 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.529104 # CPI: cycles per instruction -system.cpu.ipc 0.653978 # IPC: instructions per cycle -system.cpu.tickCycles 257145198 # Number of cycles that the object actually ticked -system.cpu.idleCycles 6346702 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.529226 # CPI: cycles per instruction +system.cpu.ipc 0.653925 # IPC: instructions per cycle +system.cpu.tickCycles 257129924 # Number of cycles that the object actually ticked +system.cpu.idleCycles 6382987 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1377.772724 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40762987 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1377.698544 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40765677 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22520.987293 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22522.473481 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1377.772724 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.336370 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.336370 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1377.698544 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.336352 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.336352 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1358 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.431641 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 81532656 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 81532656 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 28355530 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28355530 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12362643 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12362643 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 81538036 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 81538036 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28358222 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28358222 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12362641 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12362641 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40718173 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40718173 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40718173 # number of overall hits -system.cpu.dcache.overall_hits::total 40718173 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 792 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 792 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1644 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1644 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 40720863 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40720863 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40720863 # number of overall hits +system.cpu.dcache.overall_hits::total 40720863 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 790 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 790 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1646 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1646 # number of WriteReq misses system.cpu.dcache.demand_misses::cpu.data 2436 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 2436 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2436 # number of overall misses system.cpu.dcache.overall_misses::total 2436 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 54011984 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 54011984 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 115610250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 115610250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 169622234 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 169622234 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 169622234 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 169622234 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28356322 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28356322 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57599734 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57599734 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 127302750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 127302750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 184902484 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 184902484 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 184902484 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 184902484 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28359012 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28359012 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 40720609 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 40720609 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 40720609 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 40720609 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 40723299 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 40723299 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 40723299 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 40723299 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses @@ -454,14 +454,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68196.949495 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68196.949495 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70322.536496 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70322.536496 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 69631.458949 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69631.458949 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 69631.458949 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69631.458949 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72911.055696 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72911.055696 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77340.674362 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77340.674362 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 75904.139573 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 75904.139573 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 75904.139573 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 75904.139573 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -472,10 +472,10 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 16 # number of writebacks system.cpu.dcache.writebacks::total 16 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 80 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 546 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 546 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 548 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 548 # number of WriteReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 626 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 626 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 626 # number of overall MSHR hits @@ -488,14 +488,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1810 system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1810 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47293264 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 47293264 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 76508500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 76508500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 123801764 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 123801764 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 123801764 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 123801764 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51193764 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 51193764 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85249250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85249250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136443014 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 136443014 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136443014 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 136443014 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses @@ -504,69 +504,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66423.123596 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66423.123596 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69679.872495 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69679.872495 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68398.764641 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68398.764641 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68398.764641 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68398.764641 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71901.353933 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71901.353933 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77640.482696 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77640.482696 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75382.880663 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75382.880663 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75382.880663 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75382.880663 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 2909 # number of replacements -system.cpu.icache.tags.tagsinuse 1424.880841 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 71614329 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4705 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 15220.898831 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2891 # number of replacements +system.cpu.icache.tags.tagsinuse 1424.909254 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 71597357 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4688 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 15272.473763 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1424.880841 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.695743 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.695743 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1796 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1424.909254 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.695756 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.695756 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 492 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 125 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1068 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.876953 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 143242775 # Number of tag accesses -system.cpu.icache.tags.data_accesses 143242775 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 71614329 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 71614329 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 71614329 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 71614329 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 71614329 # number of overall hits -system.cpu.icache.overall_hits::total 71614329 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4706 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4706 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4706 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4706 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4706 # number of overall misses -system.cpu.icache.overall_misses::total 4706 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 186377497 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 186377497 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 186377497 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 186377497 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 186377497 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 186377497 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 71619035 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 71619035 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 71619035 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 71619035 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 71619035 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 71619035 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39604.228007 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 39604.228007 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 39604.228007 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 39604.228007 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 39604.228007 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 39604.228007 # average overall miss latency +system.cpu.icache.tags.age_task_id_blocks_1024::2 490 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 129 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1067 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.877441 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 143208780 # Number of tag accesses +system.cpu.icache.tags.data_accesses 143208780 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 71597357 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 71597357 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 71597357 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 71597357 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 71597357 # number of overall hits +system.cpu.icache.overall_hits::total 71597357 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4689 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4689 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4689 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4689 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4689 # number of overall misses +system.cpu.icache.overall_misses::total 4689 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 200362248 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 200362248 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 200362248 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 200362248 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 200362248 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 200362248 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 71602046 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 71602046 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 71602046 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 71602046 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 71602046 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 71602046 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000065 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000065 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000065 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000065 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000065 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000065 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42730.272553 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42730.272553 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42730.272553 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42730.272553 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42730.272553 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42730.272553 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -575,123 +575,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4706 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4706 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4706 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4706 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4706 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4706 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 176047503 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 176047503 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 176047503 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 176047503 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 176047503 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 176047503 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 40696500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 174705000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70436750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70436750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134008500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 111133250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 245141750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134008500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 111133250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 245141750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867978 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.512735 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.514719 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992714 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.458989 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.593616 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.458989 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.595476 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.593616 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54889.814815 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60239.482201 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56079.913607 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56423.394495 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56423.394495 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54889.814815 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57804.156909 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56176.706308 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54889.814815 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57804.156909 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56176.706308 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.595476 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61983.580019 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65851.941748 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62843.525180 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64620.871560 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64620.871560 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61983.580019 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65066.305621 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63344.121447 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61983.580019 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65066.305621 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63344.121447 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 5418 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5417 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 5401 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5400 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9411 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9377 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3636 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 13047 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 301120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 13013 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300032 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 417984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 416896 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6532 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 6515 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 6532 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 6515 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6532 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3282000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 6515 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3273500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7517497 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7496248 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2996736 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3020486 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 2777 # Transaction distribution -system.membus.trans_dist::ReadResp 2777 # Transaction distribution +system.membus.trans_dist::ReadReq 2779 # Transaction distribution +system.membus.trans_dist::ReadResp 2779 # Transaction distribution system.membus.trans_dist::ReadExReq 1090 # Transaction distribution system.membus.trans_dist::ReadExResp 1090 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7734 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7734 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247488 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 247488 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7738 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7738 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 247616 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3867 # Request fanout histogram +system.membus.snoop_fanout::samples 3869 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3867 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3869 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3867 # Request fanout histogram -system.membus.reqLayer0.occupancy 4723500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3869 # Request fanout histogram +system.membus.reqLayer0.occupancy 4526500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 36361000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20559250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |