stats: updates due to changes to ticksToCycles()

1 files changed, 75 insertions, 2 deletions

diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
index d981a43f0..90382fb26 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -64,6 +68,8 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
+fetchBufferSize=64
 fetchToDecodeDelay=1
 fetchTrapLatency=1
 fetchWidth=8
@@ -128,6 +134,7 @@ BTBTagSize=16
 RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
+eventq_index=0
 globalCtrBits=2
 globalPredictorSize=8192
 instShiftAmt=2
@@ -143,6 +150,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -165,18 +173,21 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
 size=262144
 
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
@@ -185,15 +196,18 @@ port=system.cpu.toL2Bus.slave[3]
 type=FUPool
 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+eventq_index=0
 
 [system.cpu.fuPool.FUList0]
 type=FUDesc
 children=opList
 count=6
+eventq_index=0
 opList=system.cpu.fuPool.FUList0.opList
 
 [system.cpu.fuPool.FUList0.opList]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=IntAlu
 opLat=1
@@ -202,16 +216,19 @@ opLat=1
 type=FUDesc
 children=opList0 opList1
 count=2
+eventq_index=0
 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 
 [system.cpu.fuPool.FUList1.opList0]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=IntMult
 opLat=3
 
 [system.cpu.fuPool.FUList1.opList1]
 type=OpDesc
+eventq_index=0
 issueLat=19
 opClass=IntDiv
 opLat=20
@@ -220,22 +237,26 @@ opLat=20
 type=FUDesc
 children=opList0 opList1 opList2
 count=4
+eventq_index=0
 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 
 [system.cpu.fuPool.FUList2.opList0]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=FloatAdd
 opLat=2
 
 [system.cpu.fuPool.FUList2.opList1]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=FloatCmp
 opLat=2
 
 [system.cpu.fuPool.FUList2.opList2]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=FloatCvt
 opLat=2
@@ -244,22 +265,26 @@ opLat=2
 type=FUDesc
 children=opList0 opList1 opList2
 count=2
+eventq_index=0
 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 
 [system.cpu.fuPool.FUList3.opList0]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=FloatMult
 opLat=4
 
 [system.cpu.fuPool.FUList3.opList1]
 type=OpDesc
+eventq_index=0
 issueLat=12
 opClass=FloatDiv
 opLat=12
 
 [system.cpu.fuPool.FUList3.opList2]
 type=OpDesc
+eventq_index=0
 issueLat=24
 opClass=FloatSqrt
 opLat=24
@@ -268,10 +293,12 @@ opLat=24
 type=FUDesc
 children=opList
 count=0
+eventq_index=0
 opList=system.cpu.fuPool.FUList4.opList
 
 [system.cpu.fuPool.FUList4.opList]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=MemRead
 opLat=1
@@ -280,124 +307,145 @@ opLat=1
 type=FUDesc
 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 count=4
+eventq_index=0
 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 
 [system.cpu.fuPool.FUList5.opList00]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdAdd
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList01]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdAddAcc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList02]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdAlu
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList03]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdCmp
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList04]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdCvt
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList05]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdMisc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList06]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdMult
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList07]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdMultAcc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList08]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdShift
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList09]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdShiftAcc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList10]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdSqrt
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList11]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatAdd
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList12]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatAlu
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList13]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatCmp
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList14]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatCvt
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList15]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatDiv
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList16]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatMisc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList17]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatMult
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList18]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList19]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatSqrt
 opLat=1
@@ -406,10 +454,12 @@ opLat=1
 type=FUDesc
 children=opList
 count=0
+eventq_index=0
 opList=system.cpu.fuPool.FUList6.opList
 
 [system.cpu.fuPool.FUList6.opList]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=MemWrite
 opLat=1
@@ -418,16 +468,19 @@ opLat=1
 type=FUDesc
 children=opList0 opList1
 count=4
+eventq_index=0
 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 
 [system.cpu.fuPool.FUList7.opList0]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=MemRead
 opLat=1
 
 [system.cpu.fuPool.FUList7.opList1]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=MemWrite
 opLat=1
@@ -436,10 +489,12 @@ opLat=1
 type=FUDesc
 children=opList
 count=1
+eventq_index=0
 opList=system.cpu.fuPool.FUList8.opList
 
 [system.cpu.fuPool.FUList8.opList]
 type=OpDesc
+eventq_index=0
 issueLat=3
 opClass=IprAccess
 opLat=3
@@ -450,6 +505,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -472,14 +528,17 @@ type=LRU
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
 size=131072
 
 [system.cpu.interrupts]
 type=ArmInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+eventq_index=0
 fpsid=1090793632
 id_isar0=34607377
 id_isar1=34677009
@@ -498,12 +557,14 @@ midr=890224640
 [system.cpu.itb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
@@ -514,6 +575,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -536,12 +598,14 @@ type=LRU
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -551,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -560,7 +625,8 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
+eventq_index=0
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -574,11 +640,13 @@ uid=100
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -598,6 +666,7 @@ conf_table_reported=true
 device_bus_width=8
 device_rowbuffer_size=1024
 devices_per_rank=8
+eventq_index=0
 in_addr_map=true
 mem_sched_policy=frfcfs
 null=false
@@ -609,17 +678,21 @@ static_backend_latency=10000
 static_frontend_latency=10000
 tBURST=5000
 tCL=13750
+tRAS=35000
 tRCD=13750
 tREFI=7800000
 tRFC=300000
 tRP=13750
+tRRD=6250
 tWTR=7500
 tXAW=40000
 write_buffer_size=32
-write_thresh_perc=70
+write_high_thresh_perc=70
+write_low_thresh_perc=0
 port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000