diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
| commit | 3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0 (patch) | |
| tree | 63ce098bc690eb5b58b3297b747794d623cface4 /tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt | |
| parent | af2b14a362281f36347728e13dcd6b2c4d3c4991 (diff) | |
| download | gem5-3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0.tar.xz | |
Stats: Update stats for RAS and LRU fixes.
Diffstat (limited to 'tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt | 1087 |
1 files changed, 546 insertions, 541 deletions
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 15323b4b4..a9dc709bb 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.076323 # Number of seconds simulated -sim_ticks 76322764500 # Number of ticks simulated -final_tick 76322764500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.076050 # Number of seconds simulated +sim_ticks 76049800000 # Number of ticks simulated +final_tick 76049800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95790 # Simulator instruction rate (inst/s) -host_op_rate 104880 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42423254 # Simulator tick rate (ticks/s) -host_mem_usage 235620 # Number of bytes of host memory used -host_seconds 1799.08 # Real time elapsed on the host -sim_insts 172333279 # Number of instructions simulated -sim_ops 188686762 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 133376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 113216 # Number of bytes read from this memory -system.physmem.bytes_read::total 246592 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 133376 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 133376 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2084 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1769 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3853 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1747526 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1483384 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3230910 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1747526 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1747526 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1747526 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1483384 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3230910 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 156056 # Simulator instruction rate (inst/s) +host_op_rate 170865 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68866655 # Simulator tick rate (ticks/s) +host_mem_usage 238096 # Number of bytes of host memory used +host_seconds 1104.31 # Real time elapsed on the host +sim_insts 172333196 # Number of instructions simulated +sim_ops 188686678 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 132416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 112128 # Number of bytes read from this memory +system.physmem.bytes_read::total 244544 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 132416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 132416 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2069 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1752 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3821 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1741175 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1474402 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3215577 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1741175 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1741175 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1741175 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1474402 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3215577 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,141 +70,142 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 152645530 # number of cpu cycles simulated +system.cpu.numCycles 152099601 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 97143446 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 76317615 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 6623022 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 46654244 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 44354550 # Number of BTB hits +system.cpu.BPredUnit.lookups 96837963 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 76071776 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 6557528 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 46441082 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 44202196 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 4440290 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 115738 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 40856932 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 389909160 # Number of instructions fetch has processed -system.cpu.fetch.Branches 97143446 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48794840 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 82559996 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 28665024 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7154273 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 8876 # Number of stall cycles due to pending traps +system.cpu.BPredUnit.usedRAS 4477911 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 89401 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 40623947 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 388565051 # Number of instructions fetch has processed +system.cpu.fetch.Branches 96837963 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48680107 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 82289244 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 28490098 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7220589 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 9 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 8612 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.CacheLines 37841460 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1897566 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 152586857 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.799629 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.155476 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 37659031 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1889609 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 152039589 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.799223 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.154384 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 70197419 46.00% 46.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5514909 3.61% 49.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10699531 7.01% 56.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10457896 6.85% 63.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8809329 5.77% 69.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6861836 4.50% 73.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6316245 4.14% 77.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8382546 5.49% 83.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 25347146 16.61% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 69920012 45.99% 45.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5487559 3.61% 49.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10685692 7.03% 56.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10438123 6.87% 63.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8795207 5.78% 69.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6832085 4.49% 73.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6301825 4.14% 77.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8365502 5.50% 83.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 25213584 16.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 152586857 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.636399 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.554344 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 46935408 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5876258 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 76807695 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1114753 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 21852743 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14847820 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 163458 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 403001894 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 745204 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 21852743 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 52498514 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 705487 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 794640 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 72299255 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4436218 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 380239935 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 319922 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3547314 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 643715569 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1619843514 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1602242427 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 17601087 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 298092552 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 345623017 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 60567 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 60564 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12828776 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 44110344 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16988908 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5691426 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3676812 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 335623795 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 80679 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 253280777 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 910888 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 145778004 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 375851378 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 29413 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 152586857 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.659912 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.759603 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 152039589 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.636675 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.554675 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 46670430 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5932664 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 76574160 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1118361 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 21743974 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14821262 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 162795 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 401681988 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 736800 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 21743974 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 52193760 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 715909 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 791714 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 72108942 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4485290 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 379159906 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 316677 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3600241 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 642535255 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1615137204 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1597539210 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 17597994 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 298092419 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 344442836 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 52681 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 52677 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12879836 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 44010443 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16892323 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5849879 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3738879 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 334925831 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 74527 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 252866200 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 897062 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 145077714 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 374156671 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 23276 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 152039589 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.663160 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.758894 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 58969897 38.65% 38.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23051369 15.11% 53.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25143684 16.48% 70.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20551680 13.47% 83.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12918795 8.47% 92.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6596322 4.32% 96.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4048422 2.65% 99.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1113826 0.73% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 192862 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 58521655 38.49% 38.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23034636 15.15% 53.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25191735 16.57% 70.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20480082 13.47% 83.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12877411 8.47% 92.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6577788 4.33% 96.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4065173 2.67% 99.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1110646 0.73% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 180463 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 152586857 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 152039589 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 968336 37.79% 37.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5589 0.22% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 91 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 33 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.01% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1185185 46.25% 84.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 403164 15.73% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 967418 37.56% 37.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5599 0.22% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 37.78% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 146 0.01% 37.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 37.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 37.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 37.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 37.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 21 0.00% 37.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 37.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 37.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 37.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1198100 46.52% 84.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 404230 15.70% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 197697657 78.05% 78.05% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 995408 0.39% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 197377765 78.06% 78.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 996285 0.39% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.45% # Type of FU issued @@ -223,169 +224,169 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.45% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33135 0.01% 78.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33143 0.01% 78.46% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 164107 0.06% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 254969 0.10% 78.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76438 0.03% 78.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 467546 0.18% 78.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206313 0.08% 78.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71855 0.03% 78.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 78.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 39090450 15.43% 94.38% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 14222579 5.62% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 164246 0.06% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 255557 0.10% 78.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76455 0.03% 78.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 467877 0.19% 78.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206463 0.08% 78.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71866 0.03% 78.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 39025783 15.43% 94.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 14190441 5.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 253280777 # Type of FU issued -system.cpu.iq.rate 1.659274 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2562398 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010117 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 658846824 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 479250938 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 240868765 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3774873 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2250330 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1852271 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 253948063 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1895112 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2034666 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 252866200 # Type of FU issued +system.cpu.iq.rate 1.662504 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2575514 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010185 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 657470724 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 477849498 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 240611060 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3773841 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2247636 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1852910 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 253547208 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1894506 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2021626 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14254809 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 18806 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19550 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4338224 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14154924 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 16760 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 19840 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4241654 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 46 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 11 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 21852743 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 13300 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 608 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 335763367 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 963800 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 44110344 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16988908 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 58117 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 150 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 281 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 19550 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4170846 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3956659 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8127505 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 246138856 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 37439094 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7141921 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 21743974 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 13418 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 622 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 335058586 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 832362 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 44010443 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16892323 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 51985 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 162 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 263 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 19840 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4108839 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3946041 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8054880 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 245860683 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 37402341 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7005517 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 58893 # number of nop insts executed -system.cpu.iew.exec_refs 51255438 # number of memory reference insts executed -system.cpu.iew.exec_branches 54101167 # Number of branches executed -system.cpu.iew.exec_stores 13816344 # Number of stores executed -system.cpu.iew.exec_rate 1.612486 # Inst execution rate -system.cpu.iew.wb_sent 243866975 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 242721036 # cumulative count of insts written-back -system.cpu.iew.wb_producers 150184249 # num instructions producing a value -system.cpu.iew.wb_consumers 269391648 # num instructions consuming a value +system.cpu.iew.exec_nop 58228 # number of nop insts executed +system.cpu.iew.exec_refs 51211338 # number of memory reference insts executed +system.cpu.iew.exec_branches 54022808 # Number of branches executed +system.cpu.iew.exec_stores 13808997 # Number of stores executed +system.cpu.iew.exec_rate 1.616445 # Inst execution rate +system.cpu.iew.wb_sent 243598204 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 242463970 # cumulative count of insts written-back +system.cpu.iew.wb_producers 150083518 # num instructions producing a value +system.cpu.iew.wb_consumers 269173561 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.590096 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.557494 # average fanout of values written-back +system.cpu.iew.wb_rate 1.594113 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.557572 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 172347667 # The number of committed instructions -system.cpu.commit.commitCommittedOps 188701150 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 147062192 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 51266 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6488296 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 130734115 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.443396 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.157229 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 172347584 # The number of committed instructions +system.cpu.commit.commitCommittedOps 188701066 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 146357504 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 51251 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 6423604 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 130295616 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.448253 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.160604 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 60440090 46.23% 46.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 32094015 24.55% 70.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14011020 10.72% 81.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7691837 5.88% 87.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4423613 3.38% 90.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1340820 1.03% 91.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1731909 1.32% 93.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1286910 0.98% 94.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7713901 5.90% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 60033353 46.07% 46.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 32093498 24.63% 70.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14006031 10.75% 81.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7653781 5.87% 87.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4421161 3.39% 90.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1332201 1.02% 91.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1737103 1.33% 93.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1282008 0.98% 94.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7736480 5.94% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 130734115 # Number of insts commited each cycle -system.cpu.commit.committedInsts 172347667 # Number of instructions committed -system.cpu.commit.committedOps 188701150 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 130295616 # Number of insts commited each cycle +system.cpu.commit.committedInsts 172347584 # Number of instructions committed +system.cpu.commit.committedOps 188701066 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 42506219 # Number of memory references committed -system.cpu.commit.loads 29855535 # Number of loads committed +system.cpu.commit.refs 42506188 # Number of memory references committed +system.cpu.commit.loads 29855519 # Number of loads committed system.cpu.commit.membars 22408 # Number of memory barriers committed -system.cpu.commit.branches 40287733 # Number of branches committed +system.cpu.commit.branches 40287717 # Number of branches committed system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. -system.cpu.commit.int_insts 150130425 # Number of committed integer instructions. +system.cpu.commit.int_insts 150130357 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 7713901 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 7736480 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 458778355 # The number of ROB reads -system.cpu.rob.rob_writes 693498788 # The number of ROB writes -system.cpu.timesIdled 1746 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 58673 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 172333279 # Number of Instructions Simulated -system.cpu.committedOps 188686762 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 172333279 # Number of Instructions Simulated -system.cpu.cpi 0.885758 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.885758 # CPI: Total CPI of All Threads -system.cpu.ipc 1.128977 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.128977 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1093182861 # number of integer regfile reads -system.cpu.int_regfile_writes 388952433 # number of integer regfile writes -system.cpu.fp_regfile_reads 2911975 # number of floating regfile reads -system.cpu.fp_regfile_writes 2511798 # number of floating regfile writes -system.cpu.misc_regfile_reads 476343702 # number of misc regfile reads -system.cpu.misc_regfile_writes 832136 # number of misc regfile writes -system.cpu.icache.replacements 2645 # number of replacements -system.cpu.icache.tagsinuse 1374.603363 # Cycle average of tags in use -system.cpu.icache.total_refs 37836261 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4394 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8610.892353 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 457612505 # The number of ROB reads +system.cpu.rob.rob_writes 691979598 # The number of ROB writes +system.cpu.timesIdled 1775 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 60012 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 172333196 # Number of Instructions Simulated +system.cpu.committedOps 188686678 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 172333196 # Number of Instructions Simulated +system.cpu.cpi 0.882590 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.882590 # CPI: Total CPI of All Threads +system.cpu.ipc 1.133029 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.133029 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1092071141 # number of integer regfile reads +system.cpu.int_regfile_writes 388656879 # number of integer regfile writes +system.cpu.fp_regfile_reads 2914235 # number of floating regfile reads +system.cpu.fp_regfile_writes 2512527 # number of floating regfile writes +system.cpu.misc_regfile_reads 474801777 # number of misc regfile reads +system.cpu.misc_regfile_writes 832106 # number of misc regfile writes +system.cpu.icache.replacements 2596 # number of replacements +system.cpu.icache.tagsinuse 1365.085421 # Cycle average of tags in use +system.cpu.icache.total_refs 37653918 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4338 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 8680.017981 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1374.603363 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.671193 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.671193 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 37836261 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 37836261 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 37836261 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 37836261 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 37836261 # number of overall hits -system.cpu.icache.overall_hits::total 37836261 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5199 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5199 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5199 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5199 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5199 # number of overall misses -system.cpu.icache.overall_misses::total 5199 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 112756500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 112756500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 112756500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 112756500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 112756500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 112756500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 37841460 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 37841460 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 37841460 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 37841460 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 37841460 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 37841460 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000137 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000137 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000137 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000137 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000137 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000137 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21688.113099 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21688.113099 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21688.113099 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21688.113099 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21688.113099 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21688.113099 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1365.085421 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.666546 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.666546 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 37653921 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 37653921 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 37653921 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 37653921 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 37653921 # number of overall hits +system.cpu.icache.overall_hits::total 37653921 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5110 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5110 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5110 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5110 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5110 # number of overall misses +system.cpu.icache.overall_misses::total 5110 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 111334000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 111334000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 111334000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 111334000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 111334000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 111334000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 37659031 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 37659031 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 37659031 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 37659031 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 37659031 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 37659031 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000136 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000136 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000136 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000136 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000136 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000136 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21787.475538 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21787.475538 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21787.475538 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21787.475538 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21787.475538 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21787.475538 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -394,246 +395,250 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 804 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 804 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 804 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 804 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 804 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 804 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4395 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4395 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4395 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4395 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4395 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4395 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 78893000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 78893000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 78893000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 78893000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 78893000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 78893000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000116 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000116 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000116 # 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number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 768 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4342 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4342 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4342 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4342 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4342 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4342 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 78323000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 78323000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 78323000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 78323000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 78323000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 78323000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000115 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000115 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000115 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000115 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000115 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000115 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18038.461538 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18038.461538 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18038.461538 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18038.461538 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18038.461538 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18038.461538 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 59 # number of replacements -system.cpu.dcache.tagsinuse 1421.643782 # Cycle average of tags in use -system.cpu.dcache.total_refs 47334662 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1881 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 25164.626263 # Average number of references to valid blocks. +system.cpu.dcache.replacements 58 # number of replacements +system.cpu.dcache.tagsinuse 1413.439257 # Cycle average of tags in use +system.cpu.dcache.total_refs 47316793 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1865 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 25370.934584 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1421.643782 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.347081 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.347081 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 34919209 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 34919209 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12356677 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12356677 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 30319 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 30319 # 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Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 34901837 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 34901837 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12356702 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12356702 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 29806 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 29806 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 28442 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 28442 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 47258539 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 47258539 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 47258539 # number of overall hits +system.cpu.dcache.overall_hits::total 47258539 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1853 # 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number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 30321 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 30321 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 28457 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 28457 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 47285356 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 47285356 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 47285356 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 47285356 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29808 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 29808 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 28442 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 28442 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 47267977 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 47267977 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 47267977 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 47267977 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000615 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000615 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000066 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000066 # miss rate for LoadLockedReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000613 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000613 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000067 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000067 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000200 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000200 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000200 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000200 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32575.806452 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32575.806452 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31186.530880 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31186.530880 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32324.608743 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32324.608743 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31300.593276 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31300.593276 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 32000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 32000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31459.398099 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31459.398099 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31459.398099 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31459.398099 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31501.642297 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31501.642297 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31501.642297 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31501.642297 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 19500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 10000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 9750 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 5000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 18 # number of writebacks system.cpu.dcache.writebacks::total 18 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1056 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1056 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6533 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6533 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1071 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1071 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6498 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6498 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7589 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7589 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7589 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7589 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 804 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 804 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1881 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1881 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1881 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1881 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25610500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 25610500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 37862500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 37862500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63473000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 63473000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63473000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 63473000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000087 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 7569 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7569 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7569 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7569 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 782 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1087 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1087 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1869 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1869 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1869 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1869 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24727500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24727500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 38087000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 38087000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62814500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 62814500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62814500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 62814500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31853.855721 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31853.855721 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35155.524605 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35155.524605 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33744.284955 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 33744.284955 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33744.284955 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 33744.284955 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31620.843990 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31620.843990 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35038.638454 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35038.638454 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33608.614232 # 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Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.857143 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 4.002094 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1457.512395 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 556.224996 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000122 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.044480 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.016975 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.061577 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 2308 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 88 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2396 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::writebacks 3.028951 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1438.887241 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 538.409312 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.043911 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.016431 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.060435 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 2267 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 92 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2359 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 18 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 18 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 9 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 9 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2308 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 97 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2405 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2308 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 97 # number of overall hits -system.cpu.l2cache.overall_hits::total 2405 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2087 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 716 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 2803 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 1068 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1068 # 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number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2267 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 101 # number of overall hits +system.cpu.l2cache.overall_hits::total 2368 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2073 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 689 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 2762 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1075 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1075 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2073 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1764 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 3837 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2073 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1764 # 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number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 4395 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1881 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 6276 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.474858 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.890547 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.539142 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.991643 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.991643 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.474858 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.948432 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.616794 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.474858 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.948432 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.616794 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34256.109248 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34321.229050 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34272.743489 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34368.913858 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34368.913858 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34256.109248 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34349.775785 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34299.276673 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34256.109248 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34349.775785 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34299.276673 # average overall miss latency +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 4 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1084 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1084 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 4340 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1865 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 6205 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4340 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34317.044566 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -642,59 +647,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 15 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 15 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64692000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 55013000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 119705000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871891 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.535680 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991643 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991643 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.940457 # 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average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31098.360656 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31067.998962 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31042.226488 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31098.360656 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31067.998962 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 12 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 12 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 12 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2069 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 677 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2746 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1075 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1075 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2069 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1752 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3821 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2069 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64256500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 54501000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 118757500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.476728 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.866837 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.536223 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991697 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991697 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.476728 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.939410 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.615794 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.476728 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.939410 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.615794 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31056.790720 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31202.363368 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31092.680262 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31048.372093 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31048.372093 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31056.790720 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31107.876712 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31080.214604 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31056.790720 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31107.876712 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31080.214604 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |