stats: update stats for insts/ops and master id changes

1 files changed, 282 insertions, 170 deletions

diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
index 83e315e2a..98dddaff0 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,13 @@ sim_seconds                                  0.105851                       # Nu
 sim_ticks                                105850842000                       # Number of ticks simulated
 final_tick                               105850842000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  46914                       # Simulator instruction rate (inst/s)
-host_tick_rate                               26320721                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 259812                       # Number of bytes of host memory used
-host_seconds                                  4021.58                       # Real time elapsed on the host
-sim_insts                                   188667627                       # Number of instructions simulated
+host_inst_rate                                 122767                       # Simulator instruction rate (inst/s)
+host_op_rate                                   134419                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               75414821                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 227032                       # Number of bytes of host memory used
+host_seconds                                  1403.58                       # Real time elapsed on the host
+sim_insts                                   172314144                       # Number of instructions simulated
+sim_ops                                     188667627                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                      239936                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 128320                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -280,7 +282,8 @@ system.cpu.iew.wb_penalized                         0                       # nu
 system.cpu.iew.wb_rate                       1.155893                       # insts written-back per cycle
 system.cpu.iew.wb_fanout                     0.599323                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts      188682015                       # The number of committed instructions
+system.cpu.commit.commitCommittedInsts      172328532                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps        188682015                       # The number of committed instructions
 system.cpu.commit.commitSquashedInsts       146244510                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls         1636018                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts           9791900                       # The number of times a branch was mispredicted
@@ -301,7 +304,8 @@ system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::total    188552607                       # Number of insts commited each cycle
-system.cpu.commit.count                     188682015                       # Number of instructions committed
+system.cpu.commit.committedInsts            172328532                       # Number of instructions committed
+system.cpu.commit.committedOps              188682015                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                       42498565                       # Number of memory references committed
 system.cpu.commit.loads                      29851708                       # Number of loads committed
@@ -316,12 +320,13 @@ system.cpu.rob.rob_reads                    519029825                       # Th
 system.cpu.rob.rob_writes                   693007050                       # The number of ROB writes
 system.cpu.timesIdled                            1719                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                           58483                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                   188667627                       # Number of Instructions Simulated
-system.cpu.committedInsts_total             188667627                       # Number of Instructions Simulated
-system.cpu.cpi                               1.122088                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.122088                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.891196                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.891196                       # IPC: Total IPC of All Threads
+system.cpu.committedInsts                   172314144                       # Number of Instructions Simulated
+system.cpu.committedOps                     188667627                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total             172314144                       # Number of Instructions Simulated
+system.cpu.cpi                               1.228580                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.228580                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.813948                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.813948                       # IPC: Total IPC of All Threads
 system.cpu.int_regfile_reads               1111988877                       # number of integer regfile reads
 system.cpu.int_regfile_writes               407368356                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                   2928539                       # number of floating regfile reads
@@ -334,26 +339,39 @@ system.cpu.icache.total_refs                 40615441                       # To
 system.cpu.icache.sampled_refs                   3640                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               11158.088187                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1329.301324                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.649073                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits               40615441                       # number of ReadReq hits
-system.cpu.icache.demand_hits                40615441                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits               40615441                       # number of overall hits
-system.cpu.icache.ReadReq_misses                 4234                       # number of ReadReq misses
-system.cpu.icache.demand_misses                  4234                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                 4234                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency      101275500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency       101275500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency      101275500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses           40619675                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses            40619675                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses           40619675                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000104                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000104                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000104                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 23919.579594                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 23919.579594                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 23919.579594                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1329.301324                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.649073                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.649073                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     40615441                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        40615441                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      40615441                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         40615441                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     40615441                       # number of overall hits
+system.cpu.icache.overall_hits::total        40615441                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         4234                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          4234                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         4234                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           4234                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         4234                       # number of overall misses
+system.cpu.icache.overall_misses::total          4234                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    101275500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    101275500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    101275500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    101275500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    101275500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    101275500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     40619675                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     40619675                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     40619675                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     40619675                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     40619675                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     40619675                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000104                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000104                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000104                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23919.579594                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 23919.579594                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 23919.579594                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -362,27 +380,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits               594                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                594                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits               594                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses            3640                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses             3640                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses            3640                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     74572500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     74572500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     74572500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000090                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000090                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000090                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 20486.950549                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 20486.950549                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 20486.950549                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          594                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          594                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          594                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          594                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          594                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          594                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         3640                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         3640                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         3640                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         3640                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         3640                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         3640                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     74572500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     74572500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     74572500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     74572500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     74572500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     74572500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000090                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000090                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000090                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20486.950549                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20486.950549                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20486.950549                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                     53                       # number of replacements
 system.cpu.dcache.tagsinuse               1403.723956                       # Cycle average of tags in use
@@ -390,40 +411,63 @@ system.cpu.dcache.total_refs                 48643693                       # To
 system.cpu.dcache.sampled_refs                   1846                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs               26350.862947                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           1403.723956                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.342706                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               36234545                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              12356727                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits            27791                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits             24630                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits                48591272                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits               48591272                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                 1808                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                7560                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses              2                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses                  9368                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                 9368                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency       59529000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency     237156500                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency        63500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency       296685500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency      296685500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           36236353                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses          12364287                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses        27793                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses         24630                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses            48600640                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses           48600640                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.000050                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.000611                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate     0.000072                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate           0.000193                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.000193                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 32925.331858                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 31369.907407                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency        31750                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 31670.100342                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 31670.100342                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    1403.723956                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.342706                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.342706                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     36234545                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        36234545                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     12356727                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       12356727                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        27791                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        27791                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data        24630                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total        24630                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      48591272                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         48591272                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     48591272                       # number of overall hits
+system.cpu.dcache.overall_hits::total        48591272                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         1808                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1808                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         7560                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         7560                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data         9368                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           9368                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         9368                       # number of overall misses
+system.cpu.dcache.overall_misses::total          9368                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     59529000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     59529000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    237156500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    237156500                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        63500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total        63500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    296685500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    296685500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    296685500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    296685500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     36236353                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     36236353                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        27793                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        27793                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data        24630                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total        24630                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     48600640                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     48600640                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     48600640                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     48600640                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000050                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000611                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000072                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000193                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000193                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32925.331858                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31369.907407                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        31750                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 31670.100342                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 31670.100342                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets        20000                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -432,33 +476,42 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets        20000                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                       18                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits              1053                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits             6469                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits               7522                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits              7522                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses             755                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses           1091                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses             1846                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses            1846                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency     24116500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency     38344000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency     62460500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency     62460500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.000021                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000088                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.000038                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.000038                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31942.384106                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35145.737855                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 33835.590466                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 33835.590466                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks           18                       # number of writebacks
+system.cpu.dcache.writebacks::total                18                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data         1053                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total         1053                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6469                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         6469                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         7522                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         7522                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         7522                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         7522                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          755                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          755                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1091                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         1091                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         1846                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         1846                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         1846                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         1846                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     24116500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     24116500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     38344000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     38344000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     62460500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     62460500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     62460500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     62460500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000021                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000088                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000038                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000038                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31942.384106                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35145.737855                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33835.590466                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33835.590466                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse              1923.480613                       # Cycle average of tags in use
@@ -466,36 +519,75 @@ system.cpu.l2cache.total_refs                    1714                       # To
 system.cpu.l2cache.sampled_refs                  2676                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.640508                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          1919.476269                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1             4.004344                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.058578                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.000122                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                  1714                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits                  18                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits                   9                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                   1723                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                  1723                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                2681                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses              1082                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                 3763                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                3763                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency      91922000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency     37184000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency      129106000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency     129106000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses              4395                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses              18                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses            1091                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses               5486                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses              5486                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.610011                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.991751                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.685928                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.685928                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34286.460276                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34365.988909                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34309.327664                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34309.327664                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks     4.004344                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   1392.392495                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    527.083774                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.000122                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.042492                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.016085                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.058700                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst         1633                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data           81                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total           1714                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks           18                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total           18                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data            9                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total            9                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         1633                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data           90                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total            1723                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         1633                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data           90                       # number of overall hits
+system.cpu.l2cache.overall_hits::total           1723                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         2007                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          674                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         2681                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data         1082                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         1082                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         2007                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         1756                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          3763                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2007                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         1756                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         3763                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     68771500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     23150500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     91922000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     37184000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     37184000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     68771500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     60334500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    129106000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     68771500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     60334500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    129106000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         3640                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data          755                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total         4395                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks           18                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total           18                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         1091                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         1091                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         3640                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         1846                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total         5486                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         3640                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         1846                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total         5486                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.551374                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.892715                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.991751                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.551374                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.951246                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.551374                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.951246                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34265.819631                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34347.922849                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34365.988909                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34265.819631                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34359.054670                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34265.819631                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34359.054670                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -504,31 +596,51 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits               14                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits                14                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits               14                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses           2667                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses         1082                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses            3749                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses           3749                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     82895000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency     33590000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency    116485000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency    116485000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.606826                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.991751                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.683376                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.683376                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.739783                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31044.362292                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31070.952254                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31070.952254                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            2                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           12                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           14                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           12                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           14                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data           12                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           14                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2005                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          662                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         2667                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1082                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         1082                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2005                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         1744                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         3749                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2005                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         1744                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         3749                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     62251500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     20643500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     82895000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     33590000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     33590000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     62251500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     54233500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    116485000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     62251500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     54233500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    116485000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.550824                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.876821                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.991751                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.550824                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.944745                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.550824                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.944745                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31048.129676                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31183.534743                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31044.362292                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31048.129676                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31097.190367                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31048.129676                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31097.190367                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------