diff options
author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-09-25 11:49:41 -0500 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-09-25 11:49:41 -0500 |
commit | 91e74beee60b2085d18dfbfd51018dce2c779d8d (patch) | |
tree | 96a71f2f316d24e9378bc3a68df207880e0eccca /tests/long/se/70.twolf/ref/arm/linux/simple-atomic | |
parent | 80a26a3e39874dab7c0b51cd5ce0258039494e30 (diff) | |
download | gem5-91e74beee60b2085d18dfbfd51018dce2c779d8d.tar.xz |
ARM: update stats for bp and squash fixes.
Diffstat (limited to 'tests/long/se/70.twolf/ref/arm/linux/simple-atomic')
3 files changed, 23 insertions, 20 deletions
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini index 337b40f6d..0be27d977 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -48,7 +49,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 simulate_data_stalls=false @@ -68,8 +68,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -84,8 +84,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -95,12 +95,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic +cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/twolf +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 @@ -117,14 +117,15 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 -master=system.physmem.port[0] +width=8 +master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout index 887de4fb8..9558000b2 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 01:29:40 -gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 12:39:32 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic +Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sav +Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index 0e78b9612..15db555ed 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.103107 # Nu sim_ticks 103106766000 # Number of ticks simulated final_tick 103106766000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3148564 # Simulator instruction rate (inst/s) -host_op_rate 3447371 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1883953687 # Simulator tick rate (ticks/s) -host_mem_usage 227464 # Number of bytes of host memory used -host_seconds 54.73 # Real time elapsed on the host +host_inst_rate 2085648 # Simulator instruction rate (inst/s) +host_op_rate 2283582 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1247954818 # Simulator tick rate (ticks/s) +host_mem_usage 222132 # Number of bytes of host memory used +host_seconds 82.62 # Real time elapsed on the host sim_insts 172317409 # Number of instructions simulated sim_ops 188670891 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 759440204 # Number of bytes read from this memory @@ -84,7 +84,7 @@ system.cpu.committedOps 188670891 # Nu system.cpu.num_int_alu_accesses 150106218 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses system.cpu.num_func_calls 3545028 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 32493890 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 32494341 # number of instructions that are conditional controls system.cpu.num_int_insts 150106218 # number of integer instructions system.cpu.num_fp_insts 1752310 # number of float instructions system.cpu.num_int_register_reads 809396612 # number of times the integer registers were read |