stats: Update the stats to reflect bus and memory changes

This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.

1 files changed, 40 insertions, 5 deletions

diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
index b91e59a80..6b5d6bef1 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.232072                       # Nu
 sim_ticks                                232072304000                       # Number of ticks simulated
 final_tick                               232072304000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 817822                       # Simulator instruction rate (inst/s)
-host_op_rate                                   895603                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1104464333                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 290584                       # Number of bytes of host memory used
-host_seconds                                   210.12                       # Real time elapsed on the host
+host_inst_rate                                1198657                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1312657                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1618778979                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 245268                       # Number of bytes of host memory used
+host_seconds                                   143.36                       # Real time elapsed on the host
 sim_insts                                   171842483                       # Number of instructions simulated
 sim_ops                                     188185920                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            110656                       # Number of bytes read from this memory
@@ -27,6 +27,21 @@ system.physmem.bw_inst_read::total             476817                       # In
 system.physmem.bw_total::cpu.inst              476817                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data              475438                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total                 952255                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                       952255                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                2361                       # Transaction distribution
+system.membus.trans_dist::ReadResp               2361                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              1092                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             1092                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side         6906                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count                          6906                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side       220992                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size                     220992                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                 220992                       # Total data (bytes)
+system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy             3453000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
+system.membus.respLayer1.occupancy           31077000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -414,5 +429,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 51474.007826
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51474.007826                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 51474.007826                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput                 1339169                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq           3740                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp          3740                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback           16                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         1100                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         1100                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side         6102                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side         3594                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count                     9696                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side       195264                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side       115520                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size                310784                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus            310784                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy        2444000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy       4576500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy       2683500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------