stats: Update stats for CPU and cache changes

This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.

1 files changed, 207 insertions, 189 deletions

diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
index 7e06925a9..6f9f28d30 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.232072                       # Number of seconds simulated
-sim_ticks                                232072304000                       # Number of ticks simulated
-final_tick                               232072304000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.230173                       # Number of seconds simulated
+sim_ticks                                230173357000                       # Number of ticks simulated
+final_tick                               230173357000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 924224                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1012125                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1248159761                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 313696                       # Number of bytes of host memory used
-host_seconds                                   185.93                       # Real time elapsed on the host
+host_inst_rate                                1246866                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1314511                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1670106565                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 319316                       # Number of bytes of host memory used
+host_seconds                                   137.82                       # Real time elapsed on the host
 sim_insts                                   171842483                       # Number of instructions simulated
-sim_ops                                     188185920                       # Number of ops (including micro ops) simulated
+sim_ops                                     181165370                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            110656                       # Number of bytes read from this memory
@@ -21,15 +21,15 @@ system.physmem.bytes_inst_read::total          110656                       # Nu
 system.physmem.num_reads::cpu.inst               1729                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               1724                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  3453                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst               476817                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               475438                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                  952255                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          476817                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             476817                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              476817                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              475438                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                 952255                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                       952255                       # Throughput (bytes/s)
+system.physmem.bw_read::cpu.inst               480751                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               479360                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                  960111                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          480751                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             480751                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              480751                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              479360                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                 960111                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                       960111                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                2361                       # Transaction distribution
 system.membus.trans_dist::ReadResp               2361                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              1092                       # Transaction distribution
@@ -40,9 +40,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
 system.membus.tot_pkt_size::total              220992                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus                 220992                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy             3453000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             3596000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           31077000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           31220000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
@@ -130,73 +130,75 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        464144608                       # number of cpu cycles simulated
+system.cpu.numCycles                        460346714                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   171842483                       # Number of instructions committed
-system.cpu.committedOps                     188185920                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             150106218                       # Number of integer alu accesses
+system.cpu.committedOps                     181165370                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             143085668                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                1752310                       # Number of float alu accesses
 system.cpu.num_func_calls                     3545028                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     32494341                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    150106218                       # number of integer instructions
+system.cpu.num_conditional_control_insts     32201008                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    143085668                       # number of integer instructions
 system.cpu.num_fp_insts                       1752310                       # number of float instructions
-system.cpu.num_int_register_reads           904571312                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          294073517                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           242291225                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           98192342                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads              2822225                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes             2378039                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      42494119                       # number of memory refs
-system.cpu.num_load_insts                    29849484                       # Number of load instructions
+system.cpu.num_cc_register_reads            626384527                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes           190815535                       # number of times the CC registers were written
+system.cpu.num_mem_refs                      40540779                       # number of memory refs
+system.cpu.num_load_insts                    27896144                       # Number of load instructions
 system.cpu.num_store_insts                   12644635                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  464144608                       # Number of busy cycles
+system.cpu.num_busy_cycles                  460346714                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          40300311                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                 144055422     76.35%     76.35% # Class of executed instruction
-system.cpu.op_class::IntMult                   908940      0.48%     76.83% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::FloatAdd                       0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     76.83% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd               32754      0.02%     76.85% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     76.85% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp              154829      0.08%     76.93% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt              238880      0.13%     77.06% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv               76016      0.04%     77.10% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc             437591      0.23%     77.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult             200806      0.11%     77.44% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc           71617      0.04%     77.48% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                318      0.00%     77.48% # Class of executed instruction
-system.cpu.op_class::MemRead                 29849484     15.82%     93.30% # Class of executed instruction
-system.cpu.op_class::MemWrite                12644635      6.70%    100.00% # Class of executed instruction
+system.cpu.op_class::IntAlu                 138988212     76.51%     76.51% # Class of executed instruction
+system.cpu.op_class::IntMult                   908940      0.50%     77.01% # Class of executed instruction
+system.cpu.op_class::IntDiv                         0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::FloatAdd                       0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::FloatCmp                       0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::FloatCvt                       0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::FloatMult                      0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::FloatDiv                       0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::FloatSqrt                      0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::SimdAdd                        0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc                     0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::SimdAlu                        0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::SimdCmp                        0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::SimdCvt                        0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::SimdMisc                       0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::SimdMult                       0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc                    0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::SimdShift                      0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc                   0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::SimdSqrt                       0      0.00%     77.01% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd               32754      0.02%     77.03% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu                   0      0.00%     77.03% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp              154829      0.09%     77.12% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt              238880      0.13%     77.25% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv               76016      0.04%     77.29% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc             437591      0.24%     77.53% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult             200806      0.11%     77.64% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc           71617      0.04%     77.68% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt                318      0.00%     77.68% # Class of executed instruction
+system.cpu.op_class::MemRead                 27896144     15.36%     93.04% # Class of executed instruction
+system.cpu.op_class::MemWrite                12644635      6.96%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  188671292                       # Class of executed instruction
+system.cpu.op_class::total                  181650742                       # Class of executed instruction
 system.cpu.icache.tags.replacements              1506                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1147.986161                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse          1147.992604                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           189857001                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs              3051                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          62227.794494                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1147.986161                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.560540                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.560540                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1147.992604                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.560543                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.560543                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1545                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
@@ -218,12 +220,12 @@ system.cpu.icache.demand_misses::cpu.inst         3051                       # n
 system.cpu.icache.demand_misses::total           3051                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst         3051                       # number of overall misses
 system.cpu.icache.overall_misses::total          3051                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    112281000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    112281000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    112281000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    112281000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    112281000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    112281000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    112370500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    112370500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    112370500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    112370500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    112370500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    112370500                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst    189860052                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    189860052                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst    189860052                       # number of demand (read+write) accesses
@@ -236,12 +238,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000016
 system.cpu.icache.demand_miss_rate::total     0.000016                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000016                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000016                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36801.376598                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 36801.376598                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 36801.376598                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 36801.376598                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 36801.376598                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 36801.376598                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36830.711242                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 36830.711242                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 36830.711242                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 36830.711242                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 36830.711242                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 36830.711242                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -256,34 +258,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst         3051
 system.cpu.icache.demand_mshr_misses::total         3051                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst         3051                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total         3051                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    106179000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    106179000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    106179000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    106179000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    106179000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    106179000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    106268500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    106268500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    106268500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    106268500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    106268500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    106268500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000016                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000016                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000016                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000016                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000016                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000016                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34801.376598                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34801.376598                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34801.376598                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 34801.376598                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34801.376598                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 34801.376598                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34830.711242                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34830.711242                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34830.711242                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 34830.711242                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34830.711242                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 34830.711242                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         1675.655740                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse         1675.663358                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs               1380                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             2369                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.582524                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks     3.038044                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1169.032828                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   503.584868                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks     3.037779                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1169.036759                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   503.588821                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.000093                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.035676                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.015368                       # Average percentage of cache occupancy
@@ -321,17 +323,17 @@ system.cpu.l2cache.demand_misses::total          3453                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst         1729                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         1724                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         3453                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     89908000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     32864000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    122772000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     56784000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     56784000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     89908000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     89648000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    179556000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     89908000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     89648000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    179556000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     89997500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     32887000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    122884500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     56814500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     56814500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     89997500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     89701500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    179699000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     89997500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     89701500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    179699000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst         3051                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data          689                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total         3740                       # number of ReadReq accesses(hits+misses)
@@ -356,17 +358,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.713430                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.566699                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.963667                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.713430                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52051.764025                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52036.392405                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52047.649301                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52027.930403                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52027.930403                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52051.764025                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52031.032483                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52041.413264                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52051.764025                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52031.032483                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52041.413264                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -421,14 +423,14 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                40                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1363.611259                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            42007358                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          1363.619284                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            40162626                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              1789                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          23480.915595                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          22449.762996                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1363.611259                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.332913                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.332913                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  1363.619284                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.332915                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.332915                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         1749                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           14                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
@@ -436,64 +438,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2           67
 system.cpu.dcache.tags.age_task_id_blocks_1024::3          302                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         1345                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.427002                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          84020083                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         84020083                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     29599357                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        29599357                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses          80330619                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         80330619                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     27754163                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        27754163                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     12363187                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total       12363187                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data          462                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total           462                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data        22407                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        22407                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        22407                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        22407                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      41962544                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         41962544                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     41962544                       # number of overall hits
-system.cpu.dcache.overall_hits::total        41962544                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          689                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           689                       # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data      40117350                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         40117350                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     40117812                       # number of overall hits
+system.cpu.dcache.overall_hits::total        40117812                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          688                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           688                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data         1100                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total         1100                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         1789                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           1789                       # number of demand (read+write) misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data            1                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total            1                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data         1788                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           1788                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data         1789                       # number of overall misses
 system.cpu.dcache.overall_misses::total          1789                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     35501000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     35501000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     60164000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     60164000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     95665000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     95665000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     95665000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     95665000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     29600046                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     29600046                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     35469000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     35469000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     60194500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     60194500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     95663500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     95663500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     95663500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     95663500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     27754851                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     27754851                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data          463                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total          463                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data        22407                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total        22407                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        22407                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        22407                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     41964333                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     41964333                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     41964333                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     41964333                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000023                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000023                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data     40119138                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     40119138                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     40119601                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     40119601                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000025                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000025                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000089                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.000089                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000043                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000043                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000043                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000043                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51525.399129                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 51525.399129                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54694.545455                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 54694.545455                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 53474.007826                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 53474.007826                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 53474.007826                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 53474.007826                       # average overall miss latency
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.002160                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.002160                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000045                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000045                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000045                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000045                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51553.779070                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 51553.779070                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54722.272727                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 54722.272727                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 53503.076063                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 53503.076063                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 53473.169368                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 53473.169368                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -504,40 +514,48 @@ system.cpu.dcache.fast_writes                       0                       # nu
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks           16                       # number of writebacks
 system.cpu.dcache.writebacks::total                16                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          689                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          689                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          688                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          688                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1100                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total         1100                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         1789                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         1789                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            1                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total            1                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         1788                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         1788                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         1789                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         1789                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     34123000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     34123000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     57964000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     57964000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     92087000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     92087000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     92087000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     92087000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000023                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000023                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     34093000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     34093000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     57994500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     57994500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        53000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        53000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     92087500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     92087500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     92140500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     92140500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000025                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000089                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000089                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000043                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.000043                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000043                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.000043                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49525.399129                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49525.399129                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52694.545455                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52694.545455                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51474.007826                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 51474.007826                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51474.007826                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 51474.007826                       # average overall mshr miss latency
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.002160                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.002160                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000045                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.000045                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000045                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.000045                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49553.779070                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49553.779070                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52722.272727                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52722.272727                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        53000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        53000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51503.076063                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 51503.076063                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51503.912800                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 51503.912800                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput                 1339169                       # Throughput (bytes/s)
+system.cpu.toL2Bus.throughput                 1350217                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq           3740                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp          3740                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback           16                       # Transaction distribution