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authorNilay Vaish <nilay@cs.wisc.edu>2013-01-04 19:00:48 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2013-01-04 19:00:48 -0600
commit5ebe3210d80d7f0226c33877d7200be8cb38d423 (patch)
tree27a31051c662fdc72623351a6806ba695eab28e0 /tests/long/se/70.twolf/ref/arm/linux
parente17c375ddd32fbbef55a96c446a4b98b20df2ad5 (diff)
downloadgem5-5ebe3210d80d7f0226c33877d7200be8cb38d423.tar.xz
regressions: stats update due to decoder changes
Diffstat (limited to 'tests/long/se/70.twolf/ref/arm/linux')
-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt264
1 files changed, 132 insertions, 132 deletions
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
index 341764510..144145b4f 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.074245 # Nu
sim_ticks 74245032000 # Number of ticks simulated
final_tick 74245032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 109443 # Simulator instruction rate (inst/s)
-host_op_rate 119829 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 47150577 # Simulator tick rate (ticks/s)
-host_mem_usage 234068 # Number of bytes of host memory used
-host_seconds 1574.64 # Real time elapsed on the host
+host_inst_rate 131550 # Simulator instruction rate (inst/s)
+host_op_rate 144033 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 56674428 # Simulator tick rate (ticks/s)
+host_mem_usage 280244 # Number of bytes of host memory used
+host_seconds 1310.03 # Real time elapsed on the host
sim_insts 172333441 # Number of instructions simulated
sim_ops 188686923 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 131008 # Number of bytes read from this memory
@@ -497,7 +497,7 @@ system.cpu.int_regfile_reads 1079711901 # nu
system.cpu.int_regfile_writes 384939818 # number of integer regfile writes
system.cpu.fp_regfile_reads 2913621 # number of floating regfile reads
system.cpu.fp_regfile_writes 2497505 # number of floating regfile writes
-system.cpu.misc_regfile_reads 464692735 # number of misc regfile reads
+system.cpu.misc_regfile_reads 54528814 # number of misc regfile reads
system.cpu.misc_regfile_writes 832204 # number of misc regfile writes
system.cpu.icache.replacements 2508 # number of replacements
system.cpu.icache.tagsinuse 1347.136586 # Cycle average of tags in use
@@ -583,6 +583,132 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 28969.199670
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28969.199670 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 28969.199670 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 57 # number of replacements
+system.cpu.dcache.tagsinuse 1406.445400 # Cycle average of tags in use
+system.cpu.dcache.total_refs 46805125 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 1854 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 25245.482740 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 1406.445400 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.343370 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.343370 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 34390274 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 34390274 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 12356568 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 12356568 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 29790 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 29790 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 28491 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 28491 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 46746842 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 46746842 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 46746842 # number of overall hits
+system.cpu.dcache.overall_hits::total 46746842 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1833 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1833 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 7719 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 7719 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 9552 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 9552 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 9552 # number of overall misses
+system.cpu.dcache.overall_misses::total 9552 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 82596000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 82596000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 292720496 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 292720496 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 102000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 102000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 375316496 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 375316496 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 375316496 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 375316496 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 34392107 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 34392107 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29792 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 29792 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 28491 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 28491 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 46756394 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 46756394 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 46756394 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 46756394 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000624 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000624 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000067 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000067 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.000204 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.000204 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.000204 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.000204 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45060.556465 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 45060.556465 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37922.074880 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 37922.074880 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 39291.927973 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 39291.927973 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 39291.927973 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 39291.927973 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 476 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 40 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 18 # number of writebacks
+system.cpu.dcache.writebacks::total 18 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1062 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 1062 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 7696 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 7696 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 7696 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 7696 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 771 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 771 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1085 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1085 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1856 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1856 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1856 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1856 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36781000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 36781000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 47410498 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 47410498 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 84191498 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 84191498 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 84191498 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 84191498 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47705.577173 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47705.577173 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43696.311521 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43696.311521 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45361.798491 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 45361.798491 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45361.798491 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 45361.798491 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 1961.084973 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2275 # Total number of references to valid blocks.
@@ -742,131 +868,5 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34368.847168
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33800.926648 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34107.570788 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 57 # number of replacements
-system.cpu.dcache.tagsinuse 1406.445400 # Cycle average of tags in use
-system.cpu.dcache.total_refs 46805125 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1854 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 25245.482740 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 1406.445400 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.343370 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.343370 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 34390274 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 34390274 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 12356568 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 12356568 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 29790 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 29790 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 28491 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 28491 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 46746842 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 46746842 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 46746842 # number of overall hits
-system.cpu.dcache.overall_hits::total 46746842 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1833 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1833 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 7719 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 7719 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 9552 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 9552 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 9552 # number of overall misses
-system.cpu.dcache.overall_misses::total 9552 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 82596000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 82596000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 292720496 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 292720496 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 102000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 102000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 375316496 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 375316496 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 375316496 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 375316496 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 34392107 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 34392107 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29792 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 29792 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 28491 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 28491 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 46756394 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 46756394 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 46756394 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 46756394 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000624 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000624 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000067 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000067 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000204 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.000204 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000204 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.000204 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45060.556465 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 45060.556465 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37922.074880 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 37922.074880 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 39291.927973 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 39291.927973 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 39291.927973 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 39291.927973 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 476 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 40 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 18 # number of writebacks
-system.cpu.dcache.writebacks::total 18 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1062 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 1062 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 7696 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 7696 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 7696 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 7696 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 771 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 771 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1085 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1085 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1856 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1856 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1856 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1856 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36781000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 36781000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 47410498 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 47410498 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 84191498 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 84191498 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 84191498 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 84191498 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47705.577173 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47705.577173 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43696.311521 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43696.311521 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45361.798491 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 45361.798491 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45361.798491 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 45361.798491 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------