diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-02 06:08:25 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-02 06:08:25 -0500 |
| commit | 6489598fb449531c34bfb25a52189196ee2b1086 (patch) | |
| tree | 5f8bb88862ffd187cb7b182f4a0d20599b4409bf /tests/long/se/70.twolf/ref/arm/linux | |
| parent | 966c3f4bc5581347a411c25db1440afb97f12dab (diff) | |
| download | gem5-6489598fb449531c34bfb25a52189196ee2b1086.tar.xz | |
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
Diffstat (limited to 'tests/long/se/70.twolf/ref/arm/linux')
| -rw-r--r-- | tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt | 862 |
1 files changed, 431 insertions, 431 deletions
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index 5a483b5e7..be651ff21 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.131652 # Number of seconds simulated -sim_ticks 131652469500 # Number of ticks simulated -final_tick 131652469500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.131746 # Number of seconds simulated +sim_ticks 131745950000 # Number of ticks simulated +final_tick 131745950000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 162179 # Simulator instruction rate (inst/s) -host_op_rate 170963 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 123906567 # Simulator tick rate (ticks/s) -host_mem_usage 259776 # Number of bytes of host memory used -host_seconds 1062.51 # Real time elapsed on the host +host_inst_rate 190259 # Simulator instruction rate (inst/s) +host_op_rate 200564 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 145463120 # Simulator tick rate (ticks/s) +host_mem_usage 256996 # Number of bytes of host memory used +host_seconds 905.70 # Real time elapsed on the host sim_insts 172317809 # Number of instructions simulated sim_ops 181650742 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 247616 # Number of bytes read from this memory -system.physmem.bytes_read::total 247616 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 138304 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 138304 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3869 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3869 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1880831 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1880831 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1050523 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1050523 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1880831 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1880831 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3869 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 247488 # Number of bytes read from this memory +system.physmem.bytes_read::total 247488 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 138176 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 138176 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3867 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3867 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1878525 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1878525 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1048806 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1048806 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1878525 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1878525 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3867 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 3869 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 3867 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 247616 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 247488 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 247616 # Total read bytes from the system interface side +system.physmem.bytesReadSys 247488 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -42,14 +42,14 @@ system.physmem.perBankRdBursts::1 217 # Pe system.physmem.perBankRdBursts::2 135 # Per bank write bursts system.physmem.perBankRdBursts::3 313 # Per bank write bursts system.physmem.perBankRdBursts::4 308 # Per bank write bursts -system.physmem.perBankRdBursts::5 306 # Per bank write bursts +system.physmem.perBankRdBursts::5 305 # Per bank write bursts system.physmem.perBankRdBursts::6 273 # Per bank write bursts system.physmem.perBankRdBursts::7 222 # Per bank write bursts system.physmem.perBankRdBursts::8 249 # Per bank write bursts system.physmem.perBankRdBursts::9 218 # Per bank write bursts system.physmem.perBankRdBursts::10 295 # Per bank write bursts -system.physmem.perBankRdBursts::11 201 # Per bank write bursts -system.physmem.perBankRdBursts::12 182 # Per bank write bursts +system.physmem.perBankRdBursts::11 199 # Per bank write bursts +system.physmem.perBankRdBursts::12 183 # Per bank write bursts system.physmem.perBankRdBursts::13 218 # Per bank write bursts system.physmem.perBankRdBursts::14 224 # Per bank write bursts system.physmem.perBankRdBursts::15 203 # Per bank write bursts @@ -71,14 +71,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 131652381500 # Total gap between requests +system.physmem.totGap 131745861500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 3869 # Read request sizes (log2) +system.physmem.readPktSize::6 3867 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -87,8 +87,8 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 3616 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 241 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 238 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -182,26 +182,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 904 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 272.070796 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 178.793599 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 280.048713 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 264 29.20% 29.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 351 38.83% 68.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 86 9.51% 77.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 48 5.31% 82.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 35 3.87% 86.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 23 2.54% 89.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 17 1.88% 91.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 16 1.77% 92.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 64 7.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 904 # Bytes accessed per row activation -system.physmem.totQLat 27698500 # Total ticks spent queuing -system.physmem.totMemAccLat 100242250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 19345000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7159.09 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 912 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 269.543860 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.691365 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 273.658023 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 266 29.17% 29.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 353 38.71% 67.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 82 8.99% 76.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 61 6.69% 83.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 33 3.62% 87.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 27 2.96% 90.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 14 1.54% 91.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 19 2.08% 93.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 57 6.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 912 # Bytes accessed per row activation +system.physmem.totQLat 28129500 # Total ticks spent queuing +system.physmem.totMemAccLat 100635750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 19335000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7274.24 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25909.09 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26024.24 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s @@ -212,68 +212,45 @@ system.physmem.busUtilRead 0.01 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 2960 # Number of row buffer hits during reads +system.physmem.readRowHits 2950 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.51 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.29 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34027495.86 # Average gap between requests -system.physmem.pageHitRate 76.51 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 125800686500 # Time in different power states -system.physmem.memoryStateTime::REF 4396080000 # Time in different power states +system.physmem.avgGap 34069268.55 # Average gap between requests +system.physmem.pageHitRate 76.29 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 125856871250 # Time in different power states +system.physmem.memoryStateTime::REF 4399200000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1453435500 # Time in different power states +system.physmem.memoryStateTime::ACT 1487617250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 3039120 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3780000 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1658250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 2062500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 16185000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 13774800 # Energy for read commands per rank (pJ) +system.physmem.actEnergy::0 3092040 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 3787560 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 1687125 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 2066625 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 16177200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 13767000 # Energy for read commands per rank (pJ) system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 8598732480 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 8598732480 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 3574139400 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 3578406705 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 75854895000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 75851151750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 88048649250 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 88047908235 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.807689 # Core power per rank (mW) -system.physmem.averagePower::1 668.802060 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 2779 # Transaction distribution -system.membus.trans_dist::ReadResp 2779 # Transaction distribution -system.membus.trans_dist::ReadExReq 1090 # Transaction distribution -system.membus.trans_dist::ReadExResp 1090 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7738 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7738 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247616 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 247616 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3869 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3869 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3869 # Request fanout histogram -system.membus.reqLayer0.occupancy 4528000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 36225250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 49915423 # Number of BP lookups -system.cpu.branchPred.condPredicted 39661220 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5747038 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24423675 # Number of BTB lookups -system.cpu.branchPred.BTBHits 23301282 # Number of BTB hits +system.physmem.refreshEnergy::0 8604835200 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 8604835200 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 3575888730 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 3595740120 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 75909421500 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 75892008000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 88111101795 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 88112204505 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.807404 # Core power per rank (mW) +system.physmem.averagePower::1 668.815774 # Core power per rank (mW) +system.cpu.branchPred.lookups 49935043 # Number of BP lookups +system.cpu.branchPred.condPredicted 39664695 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5744224 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 24405530 # Number of BTB lookups +system.cpu.branchPred.BTBHits 23309445 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.404488 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1905800 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 95.508866 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1908457 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 139 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -359,330 +336,91 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 263304939 # number of cpu cycles simulated +system.cpu.numCycles 263491900 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 172317809 # Number of instructions committed system.cpu.committedOps 181650742 # Number of ops (including micro ops) committed -system.cpu.discardedOps 11787313 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 11758002 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.528019 # CPI: cycles per instruction -system.cpu.ipc 0.654442 # IPC: instructions per cycle -system.cpu.tickCycles 255940225 # Number of cycles that the object actually ticked -system.cpu.idleCycles 7364714 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 2881 # number of replacements -system.cpu.icache.tags.tagsinuse 1424.983856 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 71509873 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4678 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 15286.420051 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1424.983856 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.695793 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.695793 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 503 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 114 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1069 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.877441 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 143033782 # Number of tag accesses -system.cpu.icache.tags.data_accesses 143033782 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 71509873 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 71509873 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 71509873 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 71509873 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 71509873 # number of overall hits -system.cpu.icache.overall_hits::total 71509873 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4679 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4679 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4679 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4679 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4679 # number of overall misses -system.cpu.icache.overall_misses::total 4679 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 184816496 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 184816496 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 184816496 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 184816496 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 184816496 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 184816496 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 71514552 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 71514552 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 71514552 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 71514552 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 71514552 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 71514552 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000065 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000065 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000065 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000065 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000065 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000065 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39499.144262 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 39499.144262 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 39499.144262 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 39499.144262 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 39499.144262 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 39499.144262 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4679 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4679 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4679 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4679 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4679 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4679 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 174539504 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 174539504 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 174539504 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 174539504 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 174539504 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 174539504 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000065 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000065 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000065 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37302.736482 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37302.736482 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37302.736482 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37302.736482 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37302.736482 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37302.736482 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 5390 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5389 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9357 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3634 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 12991 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 299392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116800 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 416192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6504 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 6504 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6504 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3268000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7477496 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2996735 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2001.642948 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2592 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2787 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.930032 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 3.028976 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1998.613972 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.060993 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.061085 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 2787 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 535 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 142 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2005 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.085052 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 55917 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 55917 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2591 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2591 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 8 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2599 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2599 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2599 # number of overall hits -system.cpu.l2cache.overall_hits::total 2599 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2799 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 2799 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 1090 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1090 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3889 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 3889 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3889 # number of overall misses -system.cpu.l2cache.overall_misses::total 3889 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 190706250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 190706250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 75951500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 75951500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 266657750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 266657750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 266657750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 266657750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 5390 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 5390 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1098 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1098 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 6488 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 6488 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 6488 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 6488 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.519295 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.519295 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.992714 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.992714 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.599414 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.599414 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.599414 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.599414 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68133.708467 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68133.708467 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69680.275229 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69680.275229 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68567.176652 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68567.176652 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68567.176652 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68567.176652 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 19 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 19 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 19 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 19 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 19 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 19 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2780 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2780 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 1090 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1090 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3870 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3870 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3870 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 3870 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 154681250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 154681250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 62286000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62286000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 216967250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 216967250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 216967250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 216967250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.515770 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.515770 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.992714 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.596486 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.596486 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.596486 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.596486 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55640.737410 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55640.737410 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57143.119266 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57143.119266 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56063.888889 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56063.888889 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56063.888889 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56063.888889 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.cpi 1.529104 # CPI: cycles per instruction +system.cpu.ipc 0.653978 # IPC: instructions per cycle +system.cpu.tickCycles 257145198 # Number of cycles that the object actually ticked +system.cpu.idleCycles 6346702 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1376.810186 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40745471 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1809 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22523.754008 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1377.772721 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40762987 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22520.987293 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 1376.810186 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.336135 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.336135 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1767 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.inst 1377.772721 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.336370 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.336370 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 269 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1357 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.431396 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 81497573 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 81497573 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 28338014 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28338014 # number of ReadReq hits +system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1358 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.431641 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 81532656 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 81532656 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 28355530 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28355530 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.inst 12362643 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 12362643 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.inst 22407 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.inst 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 40700657 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40700657 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 40700657 # number of overall hits -system.cpu.dcache.overall_hits::total 40700657 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 767 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 767 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.inst 40718173 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40718173 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 40718173 # number of overall hits +system.cpu.dcache.overall_hits::total 40718173 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 792 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 792 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.inst 1644 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 1644 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 2411 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2411 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 2411 # number of overall misses -system.cpu.dcache.overall_misses::total 2411 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 52005983 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 52005983 # 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mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37412.187208 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37412.187208 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37412.187208 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 37412.187208 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37412.187208 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 37412.187208 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2001.520468 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2624 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2785 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.942190 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 3.029184 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1998.491284 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.060989 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.061082 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 2785 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 522 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 153 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2005 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084991 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 56139 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 56139 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 2623 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2623 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 8 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2631 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2631 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2631 # number of overall hits +system.cpu.l2cache.overall_hits::total 2631 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2795 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 2795 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 1090 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1090 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3885 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 3885 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3885 # number of overall misses +system.cpu.l2cache.overall_misses::total 3885 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 191698500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 191698500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 75314000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 75314000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 267012500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 267012500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 267012500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 267012500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 5418 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 5418 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1098 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1098 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 6516 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 6516 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 6516 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 6516 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.515873 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.515873 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.992714 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.992714 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.596225 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.596225 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.596225 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.596225 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68586.225403 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68586.225403 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69095.412844 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69095.412844 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68729.086229 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68729.086229 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68729.086229 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68729.086229 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 17 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 17 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 17 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2778 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2778 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 1090 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1090 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3868 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3868 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3868 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 3868 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 155803750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 155803750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 61486500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61486500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 217290250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 217290250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 217290250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 217290250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.512735 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.512735 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.992714 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.593616 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.593616 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.593616 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.593616 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56084.863211 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56084.863211 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56409.633028 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56409.633028 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56176.383144 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56176.383144 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56176.383144 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56176.383144 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 5418 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5417 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9411 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3636 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 13047 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 301120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 417984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 6532 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 6532 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 6532 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3282000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 7517747 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2996736 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 2777 # Transaction distribution +system.membus.trans_dist::ReadResp 2777 # Transaction distribution +system.membus.trans_dist::ReadExReq 1090 # Transaction distribution +system.membus.trans_dist::ReadExResp 1090 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7734 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7734 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247488 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 247488 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 3867 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 3867 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 3867 # Request fanout histogram +system.membus.reqLayer0.occupancy 4723500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 36361250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |