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authorAli Saidi <saidi@eecs.umich.edu>2012-06-05 01:23:16 -0400
committerAli Saidi <saidi@eecs.umich.edu>2012-06-05 01:23:16 -0400
commitc49e739352b6d6bd665c78c560602d0cff1e6a1a (patch)
tree5d32efd82f884376573604727d971a80458ed04a /tests/long/se/70.twolf/ref/arm/linux
parente5f0d6016ba768c06b36d8b3d54f3ea700a4aa58 (diff)
downloadgem5-c49e739352b6d6bd665c78c560602d0cff1e6a1a.tar.xz
all: Update stats for memory per master and total fix.
Diffstat (limited to 'tests/long/se/70.twolf/ref/arm/linux')
-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini6
-rwxr-xr-xtests/long/se/70.twolf/ref/arm/linux/o3-timing/simout6
-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt81
-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini3
-rwxr-xr-xtests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout6
-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt42
-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini6
-rwxr-xr-xtests/long/se/70.twolf/ref/arm/linux/simple-timing/simout6
-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt79
9 files changed, 173 insertions, 62 deletions
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
index 0883e5a4a..292cbefed 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
@@ -492,9 +492,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
-type=Bus
+type=CoherentBus
block_size=64
-bus_id=0
clock=1000
header_cycles=1
use_default_range=false
@@ -525,9 +524,8 @@ system=system
uid=100
[system.membus]
-type=Bus
+type=CoherentBus
block_size=64
-bus_id=0
clock=1000
header_cycles=1
use_default_range=false
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
index 2311bc195..f8119727b 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 8 2012 15:17:37
-gem5 started May 8 2012 16:50:10
-gem5 executing on piton
+gem5 compiled Jun 4 2012 12:14:06
+gem5 started Jun 4 2012 18:52:11
+gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
index a127da205..15323b4b4 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
@@ -4,22 +4,29 @@ sim_seconds 0.076323 # Nu
sim_ticks 76322764500 # Number of ticks simulated
final_tick 76322764500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 57710 # Simulator instruction rate (inst/s)
-host_op_rate 63186 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 25558377 # Simulator tick rate (ticks/s)
-host_mem_usage 235176 # Number of bytes of host memory used
-host_seconds 2986.21 # Real time elapsed on the host
+host_inst_rate 95790 # Simulator instruction rate (inst/s)
+host_op_rate 104880 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 42423254 # Simulator tick rate (ticks/s)
+host_mem_usage 235620 # Number of bytes of host memory used
+host_seconds 1799.08 # Real time elapsed on the host
sim_insts 172333279 # Number of instructions simulated
sim_ops 188686762 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read 246592 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 133376 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 0 # Number of bytes written to this memory
-system.physmem.num_reads 3853 # Number of read requests responded to by this memory
-system.physmem.num_writes 0 # Number of write requests responded to by this memory
-system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 3230910 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 1747526 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total 3230910 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst 133376 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 113216 # Number of bytes read from this memory
+system.physmem.bytes_read::total 246592 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 133376 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 133376 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 2084 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1769 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 3853 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1747526 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1483384 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3230910 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1747526 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1747526 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1747526 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1483384 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3230910 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@@ -368,11 +375,17 @@ system.cpu.icache.demand_accesses::total 37841460 # nu
system.cpu.icache.overall_accesses::cpu.inst 37841460 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 37841460 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000137 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.000137 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000137 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.000137 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000137 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.000137 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21688.113099 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 21688.113099 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21688.113099 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 21688.113099 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21688.113099 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 21688.113099 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -400,11 +413,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 78893000
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 78893000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 78893000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000116 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.000116 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.000116 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17950.625711 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17950.625711 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17950.625711 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 17950.625711 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17950.625711 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 17950.625711 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 59 # number of replacements
system.cpu.dcache.tagsinuse 1421.643782 # Cycle average of tags in use
@@ -460,15 +479,25 @@ system.cpu.dcache.demand_accesses::total 47285356 # nu
system.cpu.dcache.overall_accesses::cpu.data 47285356 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 47285356 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000615 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000615 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000066 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000066 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000200 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.000200 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000200 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.000200 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32575.806452 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 32575.806452 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31186.530880 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 31186.530880 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 32000 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 32000 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31459.398099 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 31459.398099 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31459.398099 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 31459.398099 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 19500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -506,13 +535,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 63473000
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63473000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 63473000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000087 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31853.855721 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31853.855721 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35155.524605 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35155.524605 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33744.284955 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 33744.284955 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33744.284955 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 33744.284955 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 2017.739485 # Cycle average of tags in use
@@ -577,18 +614,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 1881
system.cpu.l2cache.overall_accesses::total 6276 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.474858 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.890547 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.539142 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.991643 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.991643 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.474858 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.948432 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.616794 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.474858 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.948432 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.616794 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34256.109248 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34321.229050 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 34272.743489 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34368.913858 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34368.913858 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34256.109248 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34349.775785 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34299.276673 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34256.109248 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34349.775785 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34299.276673 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -630,18 +675,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 55013000
system.cpu.l2cache.overall_mshr_miss_latency::total 119705000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871891 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.535680 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991643 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991643 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.940457 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.613926 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.474175 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.940457 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.613926 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31042.226488 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31179.743224 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31076.840215 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31044.943820 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31044.943820 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31042.226488 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31098.360656 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31067.998962 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31042.226488 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31098.360656 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31067.998962 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
index bd55e37b1..b72ac514a 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
@@ -112,9 +112,8 @@ system=system
uid=100
[system.membus]
-type=Bus
+type=CoherentBus
block_size=64
-bus_id=0
clock=1000
header_cycles=1
use_default_range=false
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout
index 1a4090c67..18d32cd6b 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 8 2012 15:17:37
-gem5 started May 8 2012 17:02:03
-gem5 executing on piton
+gem5 compiled Jun 4 2012 12:14:06
+gem5 started Jun 4 2012 18:53:41
+gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sav
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sv2
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
index 11a4c0835..bbd6c00f1 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
@@ -4,23 +4,35 @@ sim_seconds 0.103107 # Nu
sim_ticks 103106771000 # Number of ticks simulated
final_tick 103106771000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1081638 # Simulator instruction rate (inst/s)
-host_op_rate 1184289 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 647201988 # Simulator tick rate (ticks/s)
-host_mem_usage 224040 # Number of bytes of host memory used
-host_seconds 159.31 # Real time elapsed on the host
+host_inst_rate 2060024 # Simulator instruction rate (inst/s)
+host_op_rate 2255526 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1232622542 # Simulator tick rate (ticks/s)
+host_mem_usage 224496 # Number of bytes of host memory used
+host_seconds 83.65 # Real time elapsed on the host
sim_insts 172317417 # Number of instructions simulated
sim_ops 188670900 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read 869973902 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 759440240 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 45252940 # Number of bytes written to this memory
-system.physmem.num_reads 219482514 # Number of read requests responded to by this memory
-system.physmem.num_writes 12386694 # Number of write requests responded to by this memory
-system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 8437602047 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 7365570977 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 438893969 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 8876496016 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst 759440240 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 110533662 # Number of bytes read from this memory
+system.physmem.bytes_read::total 869973902 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 759440240 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 759440240 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data 45252940 # Number of bytes written to this memory
+system.physmem.bytes_written::total 45252940 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 189860060 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 29622454 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 219482514 # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data 12386694 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 12386694 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 7365570977 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1072031070 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 8437602047 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 7365570977 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 7365570977 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 438893969 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 438893969 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 7365570977 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1510925039 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 8876496016 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
index 98e25ecfe..3e3d3dcbe 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
@@ -161,9 +161,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
-type=Bus
+type=CoherentBus
block_size=64
-bus_id=0
clock=1000
header_cycles=1
use_default_range=false
@@ -194,9 +193,8 @@ system=system
uid=100
[system.membus]
-type=Bus
+type=CoherentBus
block_size=64
-bus_id=0
clock=1000
header_cycles=1
use_default_range=false
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
index 97209751d..08e4c719e 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 8 2012 15:17:37
-gem5 started May 8 2012 17:04:54
-gem5 executing on piton
+gem5 compiled Jun 4 2012 12:14:06
+gem5 started Jun 4 2012 18:54:15
+gem5 executing on zizzer
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sav
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sv2
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
index 5b0760555..1e695b431 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
@@ -4,22 +4,29 @@ sim_seconds 0.232077 # Nu
sim_ticks 232077154000 # Number of ticks simulated
final_tick 232077154000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 578450 # Simulator instruction rate (inst/s)
-host_op_rate 633465 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 781209577 # Simulator tick rate (ticks/s)
-host_mem_usage 233216 # Number of bytes of host memory used
-host_seconds 297.07 # Real time elapsed on the host
+host_inst_rate 665536 # Simulator instruction rate (inst/s)
+host_op_rate 728833 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 898821179 # Simulator tick rate (ticks/s)
+host_mem_usage 233632 # Number of bytes of host memory used
+host_seconds 258.20 # Real time elapsed on the host
sim_insts 171842491 # Number of instructions simulated
sim_ops 188185929 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read 220992 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 110656 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 0 # Number of bytes written to this memory
-system.physmem.num_reads 3453 # Number of read requests responded to by this memory
-system.physmem.num_writes 0 # Number of write requests responded to by this memory
-system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 952235 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 476807 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total 952235 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 110336 # Number of bytes read from this memory
+system.physmem.bytes_read::total 220992 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 110656 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 110656 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 1729 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1724 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 3453 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 476807 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 475428 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 952235 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 476807 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 476807 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 476807 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 475428 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 952235 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@@ -119,11 +126,17 @@ system.cpu.icache.demand_accesses::total 189860061 # nu
system.cpu.icache.overall_accesses::cpu.inst 189860061 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 189860061 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37801.376598 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 37801.376598 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 37801.376598 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 37801.376598 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 37801.376598 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 37801.376598 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -145,11 +158,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 106179000
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 106179000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 106179000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34801.376598 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34801.376598 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34801.376598 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 34801.376598 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34801.376598 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 34801.376598 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 40 # number of replacements
system.cpu.dcache.tagsinuse 1363.604315 # Cycle average of tags in use
@@ -201,13 +220,21 @@ system.cpu.dcache.demand_accesses::total 41964334 # nu
system.cpu.dcache.overall_accesses::cpu.data 41964334 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 41964334 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52525.399129 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 52525.399129 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55694.545455 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55694.545455 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54474.007826 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 54474.007826 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54474.007826 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 54474.007826 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -235,13 +262,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 92087000
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92087000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 92087000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.000043 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.000043 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49525.399129 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49525.399129 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52694.545455 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52694.545455 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 1675.648030 # Cycle average of tags in use
@@ -306,18 +341,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 1789
system.cpu.l2cache.overall_accesses::total 4840 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.566699 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.917271 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.631283 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992727 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.992727 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.566699 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.963667 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.713430 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.566699 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.963667 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.713430 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -350,18 +393,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 68960000
system.cpu.l2cache.overall_mshr_miss_latency::total 138120000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.917271 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.631283 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992727 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992727 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.713430 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.713430 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------