diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
| commit | 55ed9609f1056280404a8dc49e53e4ba33ae51dd (patch) | |
| tree | 6e50ced504e91a6d9dadff1b43b89a0911df3d7a /tests/long/se/70.twolf/ref/arm | |
| parent | ee7d8fdcb2226139fd1d6a6f0cde987721ea3699 (diff) | |
| download | gem5-55ed9609f1056280404a8dc49e53e4ba33ae51dd.tar.xz | |
stats: Update to match classic memory changes
Diffstat (limited to 'tests/long/se/70.twolf/ref/arm')
| -rw-r--r-- | tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt | 480 | ||||
| -rw-r--r-- | tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt | 1427 |
2 files changed, 957 insertions, 950 deletions
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index 91b6b6b0a..9382954d5 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.132486 # Number of seconds simulated -sim_ticks 132485848500 # Number of ticks simulated -final_tick 132485848500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.132488 # Number of seconds simulated +sim_ticks 132487590500 # Number of ticks simulated +final_tick 132487590500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 159309 # Simulator instruction rate (inst/s) -host_op_rate 167937 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 122483807 # Simulator tick rate (ticks/s) -host_mem_usage 270152 # Number of bytes of host memory used -host_seconds 1081.66 # Real time elapsed on the host +host_inst_rate 200266 # Simulator instruction rate (inst/s) +host_op_rate 211113 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 153975874 # Simulator tick rate (ticks/s) +host_mem_usage 275560 # Number of bytes of host memory used +host_seconds 860.44 # Real time elapsed on the host sim_insts 172317810 # Number of instructions simulated sim_ops 181650743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 138240 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory system.physmem.bytes_read::total 247552 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 138240 # Nu system.physmem.num_reads::cpu.inst 2160 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory system.physmem.num_reads::total 3868 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1043432 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 825084 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1868517 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1043432 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1043432 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1043432 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 825084 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1868517 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1043418 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 825073 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1868492 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1043418 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1043418 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1043418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 825073 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1868492 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 3868 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 3868 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 132485754500 # Total gap between requests +system.physmem.totGap 132487495500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,8 +91,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 238 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3626 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 233 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 929 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 264.680301 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 173.140302 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 275.634226 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 285 30.68% 30.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 355 38.21% 68.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 86 9.26% 78.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 48 5.17% 83.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 35 3.77% 87.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 24 2.58% 89.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 21 2.26% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 19 2.05% 93.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 56 6.03% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 929 # Bytes accessed per row activation -system.physmem.totQLat 30291250 # Total ticks spent queuing -system.physmem.totMemAccLat 102816250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 926 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 265.468683 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.726650 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 275.485307 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 276 29.81% 29.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 359 38.77% 68.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 87 9.40% 77.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 56 6.05% 84.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 31 3.35% 87.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 22 2.38% 89.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 18 1.94% 91.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 16 1.73% 93.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 61 6.59% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 926 # Bytes accessed per row activation +system.physmem.totQLat 28381250 # Total ticks spent queuing +system.physmem.totMemAccLat 100906250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 19340000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7831.24 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7337.45 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26581.24 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26087.45 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.87 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.87 # Average system read bandwidth in MiByte/s @@ -217,56 +217,56 @@ system.physmem.busUtilRead 0.01 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 2934 # Number of row buffer hits during reads +system.physmem.readRowHits 2936 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.85 # Row buffer hit rate for reads +system.physmem.readRowHitRate 75.90 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34251746.25 # Average gap between requests -system.physmem.pageHitRate 75.85 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3182760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1736625 # Energy for precharge commands per rank (pJ) +system.physmem.avgGap 34252196.35 # Average gap between requests +system.physmem.pageHitRate 75.90 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3190320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1740750 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 16161600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 8653148400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3626588520 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 76308756000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 88609573905 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.835850 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 126944435250 # Time in different power states +system.physmem_0.actBackEnergy 3615176835 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 76318766250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 88608184155 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.825360 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 126962854750 # Time in different power states system.physmem_0.memoryStateTime::REF 4423900000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1115186250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1098483750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3825360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2087250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 13790400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3795120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2070750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13782600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 8653148400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3635416395 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 76301020500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 88609288305 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.833625 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 126931702750 # Time in different power states +system.physmem_1.actBackEnergy 3628387440 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 76307186250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 88608370560 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.826698 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 126942838750 # Time in different power states system.physmem_1.memoryStateTime::REF 4423900000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1127787750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1117460750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 49693791 # Number of BP lookups -system.cpu.branchPred.condPredicted 39499604 # Number of conditional branches predicted +system.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 49693795 # Number of BP lookups +system.cpu.branchPred.condPredicted 39499605 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 5516746 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24160971 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 24160974 # Number of BTB lookups system.cpu.branchPred.BTBHits 22899506 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.778914 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1894448 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 94.778903 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1894449 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 142 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 213843 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 208090 # Number of indirect target hits. system.cpu.branchPred.indirectMisses 5753 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 40382 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -296,7 +296,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -326,7 +326,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -356,7 +356,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -387,16 +387,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 132485848500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 264971697 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 132487590500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 264975181 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 172317810 # Number of instructions committed system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed -system.cpu.discardedOps 11524051 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 11524054 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.537692 # CPI: cycles per instruction -system.cpu.ipc 0.650325 # IPC: instructions per cycle +system.cpu.cpi 1.537712 # CPI: cycles per instruction +system.cpu.ipc 0.650317 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 138988213 76.51% 76.51% # Class of committed instruction system.cpu.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction @@ -432,18 +432,18 @@ system.cpu.op_class_0::MemWrite 12644635 6.96% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 181650743 # Class of committed instruction -system.cpu.tickCycles 256731546 # Number of cycles that the object actually ticked -system.cpu.idleCycles 8240151 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 256731939 # Number of cycles that the object actually ticked +system.cpu.idleCycles 8243242 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1378.678714 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40755400 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1378.670840 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40755401 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1811 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22504.362231 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22504.362783 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1378.678714 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.336591 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.336591 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1378.670840 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.336590 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.336590 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1769 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id @@ -451,11 +451,11 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1359 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.431885 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 81517417 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 81517417 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 28347488 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28347488 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 81517419 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 81517419 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 28347489 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28347489 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 12362636 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 12362636 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits @@ -464,10 +464,10 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40710124 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40710124 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40710586 # number of overall hits -system.cpu.dcache.overall_hits::total 40710586 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 40710125 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40710125 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40710587 # number of overall hits +system.cpu.dcache.overall_hits::total 40710587 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 751 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 751 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1651 # number of WriteReq misses @@ -478,16 +478,16 @@ system.cpu.dcache.demand_misses::cpu.data 2402 # n system.cpu.dcache.demand_misses::total 2402 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2403 # number of overall misses system.cpu.dcache.overall_misses::total 2403 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 55315500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 55315500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 127182500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 127182500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 182498000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 182498000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 182498000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 182498000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28348239 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28348239 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 55860000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 55860000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 128578000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 128578000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 184438000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 184438000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 184438000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 184438000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28348240 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28348240 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses) @@ -496,10 +496,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 40712526 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 40712526 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 40712989 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 40712989 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 40712527 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 40712527 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 40712990 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 40712990 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000134 # miss rate for WriteReq accesses @@ -510,14 +510,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000059 system.cpu.dcache.demand_miss_rate::total 0.000059 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000059 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000059 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73655.792277 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 73655.792277 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77033.615990 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 77033.615990 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 75977.518734 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 75977.518734 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 75945.900957 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 75945.900957 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74380.825566 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 74380.825566 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77878.861296 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77878.861296 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76785.179017 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76785.179017 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76753.225135 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76753.225135 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -544,16 +544,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1810 system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1811 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1811 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52182500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 52182500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86133500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 86133500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 70000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 70000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 138316000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 138316000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138386000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 138386000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52704000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 52704000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 87045000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 87045000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 71000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 71000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 139749000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 139749000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 139820000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 139820000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses @@ -564,26 +564,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73393.108298 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73393.108298 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78374.431301 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78374.431301 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76417.679558 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76417.679558 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76414.135837 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76414.135837 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74126.582278 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74126.582278 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79203.821656 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79203.821656 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77209.392265 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77209.392265 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77205.963556 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77205.963556 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 2864 # number of replacements -system.cpu.icache.tags.tagsinuse 1424.966015 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1424.957423 # Cycle average of tags in use system.cpu.icache.tags.total_refs 70941364 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4663 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 15213.674459 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1424.966015 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.695784 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.695784 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1424.957423 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.695780 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.695780 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1799 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id @@ -593,7 +593,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1069 system.cpu.icache.tags.occ_task_id_percent::1024 0.878418 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 141896719 # Number of tag accesses system.cpu.icache.tags.data_accesses 141896719 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 70941364 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 70941364 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 70941364 # number of demand (read+write) hits @@ -606,12 +606,12 @@ system.cpu.icache.demand_misses::cpu.inst 4664 # n system.cpu.icache.demand_misses::total 4664 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 4664 # number of overall misses system.cpu.icache.overall_misses::total 4664 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 200959500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 200959500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 200959500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 200959500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 200959500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 200959500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 201505000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 201505000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 201505000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 201505000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 201505000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 201505000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 70946028 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 70946028 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 70946028 # number of demand (read+write) accesses @@ -624,12 +624,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43087.371355 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 43087.371355 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 43087.371355 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 43087.371355 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 43087.371355 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 43087.371355 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43204.331046 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 43204.331046 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 43204.331046 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 43204.331046 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 43204.331046 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 43204.331046 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -644,48 +644,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4664 system.cpu.icache.demand_mshr_misses::total 4664 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4664 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4664 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 196296500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 196296500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 196296500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 196296500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 196296500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 196296500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 196842000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 196842000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 196842000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 196842000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 196842000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 196842000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42087.585763 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42087.585763 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42087.585763 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 42087.585763 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42087.585763 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 42087.585763 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42204.545455 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42204.545455 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42204.545455 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 42204.545455 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42204.545455 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 42204.545455 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2000.553914 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5137 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2785 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.844524 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2835.484229 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5160 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3868 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.334023 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 3.029612 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.714154 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 489.810148 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046012 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.014948 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.061052 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 2785 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 520 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 156 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2004 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084991 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 76244 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 76244 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.704814 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1327.779416 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046011 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.040521 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.086532 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3868 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 533 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 366 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2841 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.118042 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 76228 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 76228 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 2534 # number of WritebackClean hits @@ -714,18 +712,18 @@ system.cpu.l2cache.demand_misses::total 3885 # nu system.cpu.l2cache.overall_misses::cpu.inst 2162 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1723 # number of overall misses system.cpu.l2cache.overall_misses::total 3885 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84399500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 84399500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 162646500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 162646500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 50260000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 50260000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 162646500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 134659500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 297306000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 162646500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 134659500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 297306000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 85311000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 85311000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 163192000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 163192000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 50782500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 50782500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 163192000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 136093500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 299285500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 163192000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 136093500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 299285500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 2534 # number of WritebackClean accesses(hits+misses) @@ -754,18 +752,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.600000 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463551 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.951408 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.600000 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77359.761687 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77359.761687 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75229.648474 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75229.648474 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79525.316456 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79525.316456 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75229.648474 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78154.091701 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76526.640927 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75229.648474 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78154.091701 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76526.640927 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78195.233731 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78195.233731 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75481.961147 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75481.961147 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80352.056962 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80352.056962 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75481.961147 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78986.360998 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77036.164736 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75481.961147 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78986.360998 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77036.164736 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -794,18 +792,18 @@ system.cpu.l2cache.demand_mshr_misses::total 3869 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2161 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3869 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 73489500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 73489500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 140980000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 140980000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 43051500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 43051500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 140980000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 116541000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 257521000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 140980000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 116541000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 257521000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 74401000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 74401000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 141524500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 141524500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 43559000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 43559000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 141524500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 117960000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 259484500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 141524500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 117960000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 259484500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992721 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992721 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for ReadCleanReq accesses @@ -818,25 +816,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.597529 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.597529 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67359.761687 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67359.761687 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65238.315595 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65238.315595 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69775.526742 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69775.526742 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65238.315595 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68232.435597 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66560.093047 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65238.315595 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68232.435597 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66560.093047 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68195.233731 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68195.233731 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65490.282277 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65490.282277 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70598.055105 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70598.055105 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65490.282277 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69063.231850 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67067.588524 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65490.282277 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69063.231850 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67067.588524 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 9381 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 3042 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 336 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 5375 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 2864 # Transaction distribution @@ -870,7 +868,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 6994999 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2723985 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 3868 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 2777 # Transaction distribution system.membus.trans_dist::ReadExReq 1091 # Transaction distribution system.membus.trans_dist::ReadExResp 1091 # Transaction distribution @@ -891,9 +895,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 3868 # Request fanout histogram -system.membus.reqLayer0.occupancy 4518000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4519500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 20557500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20563000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 46c589cfc..834ad990c 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.084938 # Number of seconds simulated -sim_ticks 84937723500 # Number of ticks simulated -final_tick 84937723500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.085052 # Number of seconds simulated +sim_ticks 85051506000 # Number of ticks simulated +final_tick 85051506000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 178410 # Simulator instruction rate (inst/s) -host_op_rate 188074 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 87948168 # Simulator tick rate (ticks/s) -host_mem_usage 268236 # Number of bytes of host memory used -host_seconds 965.77 # Real time elapsed on the host +host_inst_rate 137318 # Simulator instruction rate (inst/s) +host_op_rate 144756 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67782320 # Simulator tick rate (ticks/s) +host_mem_usage 272616 # Number of bytes of host memory used +host_seconds 1254.77 # Real time elapsed on the host sim_insts 172303022 # Number of instructions simulated sim_ops 181635954 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 587328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 132096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 70976 # Number of bytes read from this memory -system.physmem.bytes_read::total 790400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 587328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 587328 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 9177 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2064 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 1109 # Number of read requests responded to by this memory -system.physmem.num_reads::total 12350 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 6914807 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1555210 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 835624 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9305641 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6914807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6914807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6914807 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1555210 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 835624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9305641 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 12351 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 651584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 192256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 71040 # Number of bytes read from this memory +system.physmem.bytes_read::total 914880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 651584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 651584 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 10181 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3004 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 1110 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14295 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 7661052 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2260466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 835259 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10756776 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7661052 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7661052 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7661052 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2260466 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 835259 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10756776 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 14295 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 12351 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 14295 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 790464 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 914880 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 790464 # Total read bytes from the system interface side +system.physmem.bytesReadSys 914880 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1113 # Per bank write bursts -system.physmem.perBankRdBursts::1 381 # Per bank write bursts -system.physmem.perBankRdBursts::2 5089 # Per bank write bursts -system.physmem.perBankRdBursts::3 423 # Per bank write bursts -system.physmem.perBankRdBursts::4 1959 # Per bank write bursts +system.physmem.perBankRdBursts::0 1374 # Per bank write bursts +system.physmem.perBankRdBursts::1 495 # Per bank write bursts +system.physmem.perBankRdBursts::2 5094 # Per bank write bursts +system.physmem.perBankRdBursts::3 807 # Per bank write bursts +system.physmem.perBankRdBursts::4 2274 # Per bank write bursts system.physmem.perBankRdBursts::5 424 # Per bank write bursts -system.physmem.perBankRdBursts::6 265 # Per bank write bursts -system.physmem.perBankRdBursts::7 373 # Per bank write bursts -system.physmem.perBankRdBursts::8 266 # Per bank write bursts -system.physmem.perBankRdBursts::9 219 # Per bank write bursts -system.physmem.perBankRdBursts::10 295 # Per bank write bursts -system.physmem.perBankRdBursts::11 324 # Per bank write bursts -system.physmem.perBankRdBursts::12 199 # Per bank write bursts -system.physmem.perBankRdBursts::13 249 # Per bank write bursts -system.physmem.perBankRdBursts::14 229 # Per bank write bursts -system.physmem.perBankRdBursts::15 543 # Per bank write bursts +system.physmem.perBankRdBursts::6 384 # Per bank write bursts +system.physmem.perBankRdBursts::7 621 # Per bank write bursts +system.physmem.perBankRdBursts::8 270 # Per bank write bursts +system.physmem.perBankRdBursts::9 230 # Per bank write bursts +system.physmem.perBankRdBursts::10 354 # Per bank write bursts +system.physmem.perBankRdBursts::11 348 # Per bank write bursts +system.physmem.perBankRdBursts::12 319 # Per bank write bursts +system.physmem.perBankRdBursts::13 267 # Per bank write bursts +system.physmem.perBankRdBursts::14 239 # Per bank write bursts +system.physmem.perBankRdBursts::15 795 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -80,14 +80,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 84937714500 # Total gap between requests +system.physmem.totGap 85051447500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 12351 # Read request sizes (log2) +system.physmem.readPktSize::6 14295 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -95,15 +95,15 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 10935 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 975 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 12841 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1014 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 173 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 85 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see @@ -191,86 +191,86 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 7250 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 108.738207 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 85.269087 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 131.624325 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 5249 72.40% 72.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 1564 21.57% 93.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 167 2.30% 96.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 93 1.28% 97.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 42 0.58% 98.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 24 0.33% 98.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 18 0.25% 98.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 21 0.29% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 72 0.99% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 7250 # Bytes accessed per row activation -system.physmem.totQLat 171430514 # Total ticks spent queuing -system.physmem.totMemAccLat 403011764 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 61755000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13879.89 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 8758 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 104.242978 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 83.732821 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 121.093987 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 6415 73.25% 73.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 1879 21.45% 94.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 191 2.18% 96.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 97 1.11% 97.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 35 0.40% 98.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 31 0.35% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 21 0.24% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 17 0.19% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 72 0.82% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 8758 # Bytes accessed per row activation +system.physmem.totQLat 205669486 # Total ticks spent queuing +system.physmem.totMemAccLat 473700736 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 71475000 # Total ticks spent in databus transfers +system.physmem.avgQLat 14387.51 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32629.89 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 9.31 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 33137.51 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 10.76 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 9.31 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 10.76 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.07 # Data bus utilization in percentage -system.physmem.busUtilRead 0.07 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.08 # Data bus utilization in percentage +system.physmem.busUtilRead 0.08 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 5094 # Number of row buffer hits during reads +system.physmem.readRowHits 5530 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 41.24 # Row buffer hit rate for reads +system.physmem.readRowHitRate 38.68 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 6876990.89 # Average gap between requests -system.physmem.pageHitRate 41.24 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 48452040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 26437125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 78179400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 5949734.00 # Average gap between requests +system.physmem.pageHitRate 38.68 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 56571480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 30867375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 89442600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5547372480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 16645874445 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 36357960750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 58704276240 # Total energy per rank (pJ) -system.physmem_0.averagePower 691.186004 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 60381088491 # Time in different power states -system.physmem_0.memoryStateTime::REF 2836080000 # Time in different power states +system.physmem_0.refreshEnergy 5555000880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 17335593540 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 35823020250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 58890496125 # Total energy per rank (pJ) +system.physmem_0.averagePower 692.426384 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 59484367239 # Time in different power states +system.physmem_0.memoryStateTime::REF 2839980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 21718991509 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22725351261 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6335280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3456750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 17877600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 9616320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 5247000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 21801000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5547372480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3295031490 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 48069226500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 56939300100 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.405119 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 79958437412 # Time in different power states -system.physmem_1.memoryStateTime::REF 2836080000 # Time in different power states +system.physmem_1.refreshEnergy 5555000880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4216606920 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 47330903250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 57139175370 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.834595 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 78723898183 # Time in different power states +system.physmem_1.memoryStateTime::REF 2839980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2138239588 # Time in different power states +system.physmem_1.memoryStateTime::ACT 3485604317 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 85626366 # Number of BP lookups -system.cpu.branchPred.condPredicted 68177013 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5935452 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 39946926 # Number of BTB lookups -system.cpu.branchPred.BTBHits 38187698 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 85633597 # Number of BP lookups +system.cpu.branchPred.condPredicted 68181299 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5935035 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 39958046 # Number of BTB lookups +system.cpu.branchPred.BTBHits 38197568 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.596087 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3683716 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 81912 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 681689 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 653746 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 27943 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 40316 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 95.594184 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3683467 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 81914 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 681978 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 654112 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 27866 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 40296 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -300,7 +300,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -330,7 +330,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -360,7 +360,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -391,97 +391,97 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 84937723500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 169875448 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 85051506000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 170103013 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5671940 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 347162762 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85626366 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42525160 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 157499775 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 11884731 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 2609 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 5682904 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 347166765 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85633597 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42535147 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 157608501 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11884039 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2048 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 3808 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 78326624 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 18246 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 169120520 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.147875 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.049260 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3989 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 78333693 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 18018 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 169239484 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.146393 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.050401 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 17456404 10.32% 10.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30071791 17.78% 28.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31598997 18.68% 46.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 89993328 53.21% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 17572638 10.38% 10.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30072408 17.77% 28.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31601234 18.67% 46.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 89993204 53.18% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 169120520 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.504054 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.043631 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17509987 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 17244874 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 121866560 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6731455 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5767644 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11064434 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 189777 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 304997911 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27240618 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5767644 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37477523 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8502539 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 578983 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 108355768 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8438063 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 277420851 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13180734 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3058487 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 843003 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2280960 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 36243 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 27083 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 481449871 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1187780717 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 296461789 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3004325 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 169239484 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.503422 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.040921 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17519961 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 17356982 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 121861075 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6734206 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5767260 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11064637 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 189821 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 304987544 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27243895 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5767260 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37487022 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8574296 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 598391 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 108353196 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8459319 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 277412346 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13179472 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3059617 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 843440 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2298708 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 38369 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 27077 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 481431446 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1187749796 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 296450503 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3005240 # Number of floating rename lookups system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 188472942 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 23603 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23603 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13353784 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 33915046 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14407100 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2540378 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1803003 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 263798584 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 45955 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 214411803 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5187874 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 82208585 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 216955908 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 739 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 169120520 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.267805 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.017994 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 188454517 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 23636 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23644 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13356506 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 33916395 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14406588 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2541453 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1809916 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 263792468 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 45987 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 214404594 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5189732 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 82202501 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 216956580 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 771 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 169239484 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.266871 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.018138 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52408217 30.99% 30.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 35940187 21.25% 52.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 65510990 38.74% 90.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 13642635 8.07% 99.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1570936 0.93% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 47343 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 212 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52525006 31.04% 31.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 35947009 21.24% 52.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 65510390 38.71% 90.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13639375 8.06% 99.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1570056 0.93% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 47432 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 216 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 169120520 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 169239484 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35659439 66.16% 66.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 153265 0.28% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35663808 66.17% 66.17% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 153282 0.28% 66.45% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 66.45% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.45% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.45% # attempts to use FU when none available @@ -500,22 +500,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.45% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 66.45% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.45% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 1066 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 1064 0.00% 66.45% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 35730 0.07% 66.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 240 0.00% 66.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 35736 0.07% 66.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 239 0.00% 66.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.52% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 958 0.00% 66.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 34286 0.06% 66.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 14056522 26.08% 92.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3955910 7.34% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 34308 0.06% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 14056089 26.08% 92.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3953676 7.34% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 166992897 77.88% 77.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 919175 0.43% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 166984371 77.88% 77.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 919276 0.43% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.31% # Type of FU issued @@ -534,91 +534,91 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.31% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33015 0.02% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33022 0.02% 78.33% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 165179 0.08% 78.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 245702 0.11% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 460499 0.21% 78.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206683 0.10% 78.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 165180 0.08% 78.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 245718 0.11% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 460481 0.21% 78.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206631 0.10% 78.87% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.90% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 31868874 14.86% 93.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13371819 6.24% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 31870339 14.86% 93.76% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13371616 6.24% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 214411803 # Type of FU issued -system.cpu.iq.rate 1.262171 # Inst issue rate -system.cpu.iq.fu_busy_cnt 53897621 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.251374 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 653076785 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 344050437 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 204251594 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3952836 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2009578 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1806333 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266175663 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2133761 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1598827 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 214404594 # Type of FU issued +system.cpu.iq.rate 1.260440 # Inst issue rate +system.cpu.iq.fu_busy_cnt 53899365 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.251391 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 653186184 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 344036614 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 204245973 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3951585 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2011286 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1806392 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266171590 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2132369 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1599233 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6018902 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7447 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7034 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1762466 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6020251 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7425 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7087 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1761954 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 25527 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 769 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 25499 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 790 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5767644 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5618767 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 62916 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 263864756 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 5767260 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5621824 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 63176 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 263858489 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 33915046 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14407100 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23547 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3855 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 55872 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7034 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3149041 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3246654 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6395695 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 207125960 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 30633355 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7285843 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 33916395 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14406588 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23579 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3874 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 56135 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 7087 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3147809 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3246868 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6394677 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 207120469 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 30635063 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7284125 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 20217 # number of nop insts executed -system.cpu.iew.exec_refs 43771495 # number of memory reference insts executed -system.cpu.iew.exec_branches 44852998 # Number of branches executed -system.cpu.iew.exec_stores 13138140 # Number of stores executed -system.cpu.iew.exec_rate 1.219281 # Inst execution rate -system.cpu.iew.wb_sent 206368045 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 206057927 # cumulative count of insts written-back -system.cpu.iew.wb_producers 129397136 # num instructions producing a value -system.cpu.iew.wb_consumers 221651580 # num instructions consuming a value -system.cpu.iew.wb_rate 1.212994 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.583786 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 68672645 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 20034 # number of nop insts executed +system.cpu.iew.exec_refs 43773548 # number of memory reference insts executed +system.cpu.iew.exec_branches 44851099 # Number of branches executed +system.cpu.iew.exec_stores 13138485 # Number of stores executed +system.cpu.iew.exec_rate 1.217618 # Inst execution rate +system.cpu.iew.wb_sent 206362307 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 206052365 # cumulative count of insts written-back +system.cpu.iew.wb_producers 129396792 # num instructions producing a value +system.cpu.iew.wb_consumers 221653711 # num instructions consuming a value +system.cpu.iew.wb_rate 1.211339 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.583779 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 68665439 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5760731 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 157823719 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.150970 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.652577 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5760276 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 157944348 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.150091 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.652266 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 73232232 46.40% 46.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 41142749 26.07% 72.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 22534270 14.28% 86.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9514853 6.03% 92.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3552076 2.25% 95.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2143258 1.36% 96.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1327703 0.84% 97.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1008942 0.64% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3367636 2.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 73354007 46.44% 46.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 41142542 26.05% 72.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 22532573 14.27% 86.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9515365 6.02% 92.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3551587 2.25% 95.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2142504 1.36% 96.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1329210 0.84% 97.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1010049 0.64% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3366511 2.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 157823719 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 157944348 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317410 # Number of instructions committed system.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -664,83 +664,83 @@ system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 181650342 # Class of committed instruction -system.cpu.commit.bw_lim_events 3367636 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 404773869 # The number of ROB reads -system.cpu.rob.rob_writes 511956769 # The number of ROB writes -system.cpu.timesIdled 9030 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 754928 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3366511 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 404888417 # The number of ROB reads +system.cpu.rob.rob_writes 511940612 # The number of ROB writes +system.cpu.timesIdled 9843 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 863529 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303022 # Number of Instructions Simulated system.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.985911 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.985911 # CPI: Total CPI of All Threads -system.cpu.ipc 1.014290 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.014290 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 218725741 # number of integer regfile reads -system.cpu.int_regfile_writes 114168991 # number of integer regfile writes -system.cpu.fp_regfile_reads 2904222 # number of floating regfile reads -system.cpu.fp_regfile_writes 2441435 # number of floating regfile writes -system.cpu.cc_regfile_reads 708194084 # number of cc regfile reads -system.cpu.cc_regfile_writes 229512691 # number of cc regfile writes -system.cpu.misc_regfile_reads 57440842 # number of misc regfile reads +system.cpu.cpi 0.987232 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.987232 # CPI: Total CPI of All Threads +system.cpu.ipc 1.012933 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.012933 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 218721236 # number of integer regfile reads +system.cpu.int_regfile_writes 114166498 # number of integer regfile writes +system.cpu.fp_regfile_reads 2904044 # number of floating regfile reads +system.cpu.fp_regfile_writes 2441835 # number of floating regfile writes +system.cpu.cc_regfile_reads 708181937 # number of cc regfile reads +system.cpu.cc_regfile_writes 229500026 # number of cc regfile writes +system.cpu.misc_regfile_reads 57441519 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 72581 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.413915 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 41031177 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 73093 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 561.355766 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 508221500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.413915 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998855 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998855 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 72593 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.410345 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 41032184 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 73105 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 561.277396 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 509673500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.410345 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998848 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998848 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 229 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 160 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 230 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 44 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 82360603 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 82360603 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 28644947 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28644947 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12341311 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12341311 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 82362697 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 82362697 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 28645946 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28645946 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12341320 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12341320 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 364 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 364 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22148 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22148 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22147 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22147 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40986258 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40986258 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40986622 # number of overall hits -system.cpu.dcache.overall_hits::total 40986622 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89227 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89227 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 22976 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 22976 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 40987266 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40987266 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40987630 # number of overall hits +system.cpu.dcache.overall_hits::total 40987630 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89269 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89269 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 22967 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22967 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 116 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 116 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 259 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 259 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 112203 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 112203 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 112319 # number of overall misses -system.cpu.dcache.overall_misses::total 112319 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1066843000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1066843000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 241030499 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 241030499 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2297500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 2297500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1307873499 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1307873499 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1307873499 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1307873499 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28734174 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28734174 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_misses::cpu.data 260 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 260 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 112236 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 112236 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 112352 # number of overall misses +system.cpu.dcache.overall_misses::total 112352 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1192862000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1192862000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 244207999 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 244207999 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2309000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 2309000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1437069999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1437069999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1437069999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1437069999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28735215 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28735215 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 480 # number of SoftPFReq accesses(hits+misses) @@ -749,70 +749,70 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41098461 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41098461 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41098941 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41098941 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003105 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003105 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 41099502 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41099502 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41099982 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41099982 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003107 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003107 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001858 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001858 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.241667 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.241667 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011559 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011559 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002730 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002730 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002733 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002733 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11956.504197 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11956.504197 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10490.533557 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10490.533557 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8870.656371 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8870.656371 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 11656.314885 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 11656.314885 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 11644.276561 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 11644.276561 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 166 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 10738 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011604 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011604 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002731 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002731 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002734 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002734 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13362.555870 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13362.555870 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10632.995123 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10632.995123 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8880.769231 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8880.769231 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12804.002272 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12804.002272 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12790.782532 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12790.782532 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 168 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 10626 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 864 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 83 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 12.428241 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 72581 # number of writebacks -system.cpu.dcache.writebacks::total 72581 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24802 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 24802 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14421 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 14421 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 259 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 259 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 39223 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 39223 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 39223 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 39223 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64425 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64425 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8555 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 8555 # number of WriteReq MSHR misses +system.cpu.dcache.blocked::no_targets 868 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 84 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 12.241935 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 72593 # number of writebacks +system.cpu.dcache.writebacks::total 72593 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24834 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 24834 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14410 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 14410 # 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number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 739220499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 740182499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 740182499 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 72992 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 72992 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 73105 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 73105 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 724757000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 724757000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85765499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85765499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 963000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 963000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 810522499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 810522499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 811485499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 811485499 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002242 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002242 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000692 # mshr miss rate for WriteReq accesses @@ -821,370 +821,373 @@ system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.235417 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.235417 # 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Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 84288957500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.592571 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997251 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997251 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 51 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 278 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 49 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 156707315 # Number of tag accesses -system.cpu.icache.tags.data_accesses 156707315 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 78269055 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78269055 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78269055 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78269055 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78269055 # 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average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 73195 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 27 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3246 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21637.884494 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21637.884494 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21637.884494 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21637.884494 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21637.884494 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21637.884494 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 76503 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 31 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 199 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 957 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.007385 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.165161 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 4005348 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4005348 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 64707 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 64707 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 51067 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 51067 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 8388 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 220162000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 66910636 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1008008136 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027140 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027140 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.169536 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.169536 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.028385 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.028385 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.169536 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.028238 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.088360 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.169536 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.028238 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027365 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027365 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.188015 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.188015 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.042927 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.042927 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.188015 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.041092 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.103611 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.188015 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.041092 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.104135 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34294.294469 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 34294.294469 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70476.495726 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70476.495726 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69132.327304 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69132.327304 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71733.333333 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71733.333333 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69132.327304 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71590.843023 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69583.703967 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69132.327304 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71590.843023 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34294.294469 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64237.953732 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 253433 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 126224 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10473 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 11905 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3377 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 8528 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 118606 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 64698 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 61506 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 11007 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 2350 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 8622 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 8622 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 54136 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 64471 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 161894 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218767 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 380661 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6896512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9323136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 16219648 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 13357 # Total snoops (count) +system.cpu.l2cache.overall_mshr_miss_rate::total 0.119437 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33222.758689 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 33222.758689 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72811.440678 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72811.440678 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70811.855417 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70811.855417 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73330.382948 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73330.382948 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70811.855417 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73289.613848 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71376.374668 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70811.855417 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73289.613848 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33222.758689 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66320.687940 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 253485 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 126250 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10456 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 904 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 903 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 118630 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 64707 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 61523 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 2352 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 8624 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 8624 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 54150 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 64481 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 161936 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218803 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 380739 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6898304 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9324672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 16222976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2352 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 140586 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.219979 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.541213 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 129607 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.087812 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.283049 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 118188 84.07% 84.07% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 13870 9.87% 93.93% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 8528 6.07% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 118227 91.22% 91.22% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 11379 8.78% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 140586 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 252920500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 129607 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 252972500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 81207989 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 81228989 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 109644490 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 109661492 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 12116 # Transaction distribution -system.membus.trans_dist::ReadExReq 234 # Transaction distribution -system.membus.trans_dist::ReadExResp 234 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 12117 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 24701 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 24701 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 790400 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 790400 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 14295 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 10463 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 14059 # Transaction distribution +system.membus.trans_dist::ReadExReq 236 # Transaction distribution +system.membus.trans_dist::ReadExResp 236 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 14059 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 28590 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28590 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 914880 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 914880 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 12351 # Request fanout histogram +system.membus.snoop_fanout::samples 14295 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 12351 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 14295 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 12351 # Request fanout histogram -system.membus.reqLayer0.occupancy 15618188 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 14295 # Request fanout histogram +system.membus.reqLayer0.occupancy 18052130 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 66520835 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 77159307 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |