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authorAndreas Hansson <andreas.hansson@arm.com>2015-05-26 03:21:39 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2015-05-26 03:21:39 -0400
commit4bc7dfb697bd779b12f1fd95fbe72144ae134055 (patch)
tree532cea8e118ac27336792282c7023bb1b2d01be4 /tests/long/se/70.twolf/ref/arm
parentcea1d14a937f27fa49423bd01eb900e578993a43 (diff)
downloadgem5-4bc7dfb697bd779b12f1fd95fbe72144ae134055.tar.xz
stats: Update MinorCPU regressions after accounting fix
Diffstat (limited to 'tests/long/se/70.twolf/ref/arm')
-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt678
1 files changed, 339 insertions, 339 deletions
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
index da5e39914..d21841628 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
@@ -1,42 +1,42 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.131767 # Number of seconds simulated
-sim_ticks 131767151500 # Number of ticks simulated
-final_tick 131767151500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.131586 # Number of seconds simulated
+sim_ticks 131586268500 # Number of ticks simulated
+final_tick 131586268500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 244794 # Simulator instruction rate (inst/s)
-host_op_rate 258052 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 187187675 # Simulator tick rate (ticks/s)
-host_mem_usage 317932 # Number of bytes of host memory used
-host_seconds 703.93 # Real time elapsed on the host
+host_inst_rate 246297 # Simulator instruction rate (inst/s)
+host_op_rate 259636 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 188078312 # Simulator tick rate (ticks/s)
+host_mem_usage 317920 # Number of bytes of host memory used
+host_seconds 699.64 # Real time elapsed on the host
sim_insts 172317810 # Number of instructions simulated
sim_ops 181650743 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 138304 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 138368 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory
-system.physmem.bytes_read::total 247616 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 138304 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 138304 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 2161 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 247680 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 138368 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 138368 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 2162 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 3869 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1049609 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 829585 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1879194 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1049609 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1049609 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1049609 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 829585 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1879194 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 3869 # Number of read requests accepted
+system.physmem.num_reads::total 3870 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1051538 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 830725 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1882263 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1051538 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1051538 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1051538 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 830725 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1882263 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 3870 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 3869 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 3870 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 247616 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 247680 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 247616 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 247680 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
@@ -45,18 +45,18 @@ system.physmem.perBankRdBursts::0 305 # Pe
system.physmem.perBankRdBursts::1 217 # Per bank write bursts
system.physmem.perBankRdBursts::2 135 # Per bank write bursts
system.physmem.perBankRdBursts::3 313 # Per bank write bursts
-system.physmem.perBankRdBursts::4 307 # Per bank write bursts
+system.physmem.perBankRdBursts::4 308 # Per bank write bursts
system.physmem.perBankRdBursts::5 305 # Per bank write bursts
system.physmem.perBankRdBursts::6 273 # Per bank write bursts
system.physmem.perBankRdBursts::7 222 # Per bank write bursts
system.physmem.perBankRdBursts::8 249 # Per bank write bursts
system.physmem.perBankRdBursts::9 218 # Per bank write bursts
system.physmem.perBankRdBursts::10 295 # Per bank write bursts
-system.physmem.perBankRdBursts::11 200 # Per bank write bursts
+system.physmem.perBankRdBursts::11 201 # Per bank write bursts
system.physmem.perBankRdBursts::12 183 # Per bank write bursts
system.physmem.perBankRdBursts::13 218 # Per bank write bursts
system.physmem.perBankRdBursts::14 224 # Per bank write bursts
-system.physmem.perBankRdBursts::15 205 # Per bank write bursts
+system.physmem.perBankRdBursts::15 204 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 131767057000 # Total gap between requests
+system.physmem.totGap 131586174000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 3869 # Read request sizes (log2)
+system.physmem.readPktSize::6 3870 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
@@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 3619 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 237 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 3621 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 236 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
@@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 907 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 272.793826 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 180.627814 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 276.033343 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 260 28.67% 28.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 352 38.81% 67.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 83 9.15% 76.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 54 5.95% 82.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 42 4.63% 87.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 20 2.21% 89.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 22 2.43% 91.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 19 2.09% 93.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 55 6.06% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 907 # Bytes accessed per row activation
-system.physmem.totQLat 28218000 # Total ticks spent queuing
-system.physmem.totMemAccLat 100761750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 19345000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 7293.36 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 901 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 272.834628 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 180.187503 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 278.027106 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 257 28.52% 28.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 352 39.07% 67.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 83 9.21% 76.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 53 5.88% 82.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 41 4.55% 87.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 20 2.22% 89.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 17 1.89% 91.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 20 2.22% 93.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 58 6.44% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 901 # Bytes accessed per row activation
+system.physmem.totQLat 26462250 # Total ticks spent queuing
+system.physmem.totMemAccLat 99024750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 19350000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 6837.79 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 26043.36 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 25587.79 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s
@@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.01 # Da
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 2961 # Number of row buffer hits during reads
+system.physmem.readRowHits 2963 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 76.53 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 76.56 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 34057135.44 # Average gap between requests
-system.physmem.pageHitRate 76.53 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 3114720 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 1699500 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 16200600 # Energy for read commands per rank (pJ)
+system.physmem.avgGap 34001595.35 # Average gap between requests
+system.physmem.pageHitRate 76.56 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 3107160 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 1695375 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 16177200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 8606360880 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 3598001595 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 75904039500 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 88129416795 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.827838 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 126271035750 # Time in different power states
-system.physmem_0.memoryStateTime::REF 4399980000 # Time in different power states
+system.physmem_0.refreshEnergy 8594155440 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 3588895845 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 75799905000 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 88003936020 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.824061 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 126101706500 # Time in different power states
+system.physmem_0.memoryStateTime::REF 4393740000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 1095966750 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 1088502500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 3742200 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 2041875 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 13954200 # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy 3689280 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 2013000 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 13767000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 8606360880 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 3577878315 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 75921691500 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 88125668970 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.799395 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 126300767500 # Time in different power states
-system.physmem_1.memoryStateTime::REF 4399980000 # Time in different power states
+system.physmem_1.refreshEnergy 8594155440 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 3567061710 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 75819057750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 87999744180 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.792204 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 126130418250 # Time in different power states
+system.physmem_1.memoryStateTime::REF 4393740000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 1066235000 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 1056288250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 49934214 # Number of BP lookups
-system.cpu.branchPred.condPredicted 39669228 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 5745476 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 24397430 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 23302007 # Number of BTB hits
+system.cpu.branchPred.lookups 49889699 # Number of BP lookups
+system.cpu.branchPred.condPredicted 39633555 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 5745356 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 24337780 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 23279998 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 95.510089 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1908013 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 95.653745 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1903300 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 140 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
@@ -377,26 +377,26 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 400 # Number of system calls
-system.cpu.numCycles 263534303 # number of cpu cycles simulated
+system.cpu.numCycles 263172537 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 172317810 # Number of instructions committed
system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 11762366 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps 11983755 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 1.529350 # CPI: cycles per instruction
-system.cpu.ipc 0.653872 # IPC: instructions per cycle
-system.cpu.tickCycles 257146871 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 6387432 # Total number of cycles that the object has spent stopped
+system.cpu.cpi 1.527251 # CPI: cycles per instruction
+system.cpu.ipc 0.654771 # IPC: instructions per cycle
+system.cpu.tickCycles 256740434 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 6432103 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 42 # number of replacements
-system.cpu.dcache.tags.tagsinuse 1377.696434 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 40764379 # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 1377.700648 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 40793912 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 22521.756354 # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 22538.072928 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 1377.696434 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.336352 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.336352 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 1377.700648 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.336353 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.336353 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
@@ -404,10 +404,10 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 83
system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1358 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.431641 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 81535444 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 81535444 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 28356460 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 28356460 # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses 81594514 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 81594514 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 28385993 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 28385993 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 12362641 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 12362641 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 464 # number of SoftPFReq hits
@@ -416,30 +416,30 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407
system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 40719101 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 40719101 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 40719565 # number of overall hits
-system.cpu.dcache.overall_hits::total 40719565 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 791 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 791 # number of ReadReq misses
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+system.cpu.dcache.overall_hits::total 40749098 # number of overall hits
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system.cpu.dcache.WriteReq_misses::cpu.data 1646 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1646 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
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-system.cpu.dcache.demand_misses::total 2437 # number of demand (read+write) misses
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-system.cpu.dcache.overall_misses::total 2438 # number of overall misses
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-system.cpu.dcache.ReadReq_miss_latency::total 59434234 # number of ReadReq miss cycles
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-system.cpu.dcache.WriteReq_miss_latency::total 127677000 # number of WriteReq miss cycles
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-system.cpu.dcache.demand_miss_latency::total 187111234 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 187111234 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 187111234 # number of overall miss cycles
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-system.cpu.dcache.ReadReq_accesses::total 28357251 # number of ReadReq accesses(hits+misses)
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+system.cpu.dcache.demand_misses::total 2439 # number of demand (read+write) misses
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+system.cpu.dcache.overall_misses::total 2440 # number of overall misses
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+system.cpu.dcache.ReadReq_miss_latency::total 57815734 # number of ReadReq miss cycles
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+system.cpu.dcache.WriteReq_miss_latency::total 126489000 # number of WriteReq miss cycles
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+system.cpu.dcache.demand_miss_latency::total 184304734 # number of demand (read+write) miss cycles
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+system.cpu.dcache.overall_miss_latency::total 184304734 # number of overall miss cycles
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+system.cpu.dcache.ReadReq_accesses::total 28386786 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 465 # number of SoftPFReq accesses(hits+misses)
@@ -448,10 +448,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407
system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 40721538 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 40721538 # number of demand (read+write) accesses
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-system.cpu.dcache.overall_accesses::total 40722003 # number of overall (read+write) accesses
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+system.cpu.dcache.demand_accesses::total 40751073 # number of demand (read+write) accesses
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+system.cpu.dcache.overall_accesses::total 40751538 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses
@@ -462,14 +462,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000060
system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75138.096081 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 75138.096081 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77568.043742 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 77568.043742 # average WriteReq miss latency
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-system.cpu.dcache.demand_avg_miss_latency::total 76779.332786 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 76747.840033 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 76747.840033 # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72907.609079 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 72907.609079 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76846.294046 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 76846.294046 # average WriteReq miss latency
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+system.cpu.dcache.demand_avg_miss_latency::total 75565.696597 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 75534.727049 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 75534.727049 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -480,14 +480,14 @@ system.cpu.dcache.fast_writes 0 # nu
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 16 # number of writebacks
system.cpu.dcache.writebacks::total 16 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 80 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 82 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 548 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 548 # number of WriteReq MSHR hits
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-system.cpu.dcache.demand_mshr_hits::total 628 # number of demand (read+write) MSHR hits
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-system.cpu.dcache.overall_mshr_hits::total 628 # number of overall MSHR hits
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+system.cpu.dcache.overall_mshr_hits::total 630 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1098 # number of WriteReq MSHR misses
@@ -498,16 +498,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1809
system.cpu.dcache.demand_mshr_misses::total 1809 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1810 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses
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system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 69500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 69500 # number of SoftPFReq MSHR miss cycles
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-system.cpu.dcache.overall_mshr_miss_latency::total 138191264 # number of overall MSHR miss cycles
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+system.cpu.dcache.overall_mshr_miss_latency::total 135557264 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
@@ -518,71 +518,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044
system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses
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-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77605.191257 # average WriteReq mshr miss latency
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system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 69500 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 69500 # average SoftPFReq mshr miss latency
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements 2892 # number of replacements
-system.cpu.icache.tags.tagsinuse 1425.992142 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 71598587 # Total number of references to valid blocks.
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-system.cpu.icache.tags.avg_refs 15266.223241 # Average number of references to valid blocks.
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system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.tags.occ_task_id_blocks::1024 1798 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 490 # Occupied blocks per task id
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system.cpu.icache.tags.age_task_id_blocks_1024::4 1069 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.877930 # Percentage of cache occupancy per task id
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system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses
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-system.cpu.icache.ReadReq_avg_miss_latency::total 42643.412492 # average ReadReq miss latency
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+system.cpu.icache.overall_avg_miss_latency::cpu.inst 42819.058660 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -591,123 +591,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
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+system.cpu.l2cache.overall_mshr_miss_latency::total 244871750 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.461391 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867978 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.514529 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.515000 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992714 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.460883 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461391 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.595293 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.460883 # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.595722 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461391 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.595293 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61824.468085 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68751.618123 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63364.388489 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64585.321101 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64585.321101 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61824.468085 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66092.798595 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63708.268734 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61824.468085 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66092.798595 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63708.268734 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.595722 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62126.560333 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66318.770227 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63058.162531 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63767.889908 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63767.889908 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62126.560333 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64690.866511 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63258.008267 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62126.560333 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64690.866511 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63258.008267 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 5403 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 5402 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq 5400 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 5399 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9381 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9375 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3636 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 13017 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300160 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 13011 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 299968 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 417024 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 416832 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 6517 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 6514 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 6517 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 6514 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 6517 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 3274500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 6514 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 3273000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 7498748 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 7492747 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3019736 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.trans_dist::ReadReq 2779 # Transaction distribution
-system.membus.trans_dist::ReadResp 2779 # Transaction distribution
+system.membus.trans_dist::ReadReq 2780 # Transaction distribution
+system.membus.trans_dist::ReadResp 2780 # Transaction distribution
system.membus.trans_dist::ReadExReq 1090 # Transaction distribution
system.membus.trans_dist::ReadExResp 1090 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7738 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 7738 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247616 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 247616 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7740 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 7740 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247680 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 247680 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 3869 # Request fanout histogram
+system.membus.snoop_fanout::samples 3870 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 3869 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 3870 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 3869 # Request fanout histogram
-system.membus.reqLayer0.occupancy 4517000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 3870 # Request fanout histogram
+system.membus.reqLayer0.occupancy 4535500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 20556500 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 20561750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------