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authorPrakash Ramrakhyani <prakash.ramrakhyani@arm.com>2013-06-27 05:49:50 -0400
committerPrakash Ramrakhyani <prakash.ramrakhyani@arm.com>2013-06-27 05:49:50 -0400
commitac515d7a9b131ffc9e128bd209fcddb2f383808b (patch)
tree4a445dffeed869dac321abc09b04d7c3d65601fe /tests/long/se/70.twolf/ref/arm
parent0d68d36b9d12c36e6201fa8bc4bec34258c04eab (diff)
downloadgem5-ac515d7a9b131ffc9e128bd209fcddb2f383808b.tar.xz
mem: Reorganize cache tags and make them a SimObject
This patch reorganizes the cache tags to allow more flexibility to implement new replacement policies. The base tags class is now a clocked object so that derived classes can use a clock if they need one. Also having deriving from SimObject allows specialized Tag classes to be swapped in/out in .py files. The cache set is now templatized to allow it to contain customized cache blocks with additional informaiton. This involved moving code to the .hh file and removing cacheset.cc. The statistics belonging to the cache tags are now including ".tags" in their name. Hence, the stats need an update to reflect the change in naming.
Diffstat (limited to 'tests/long/se/70.twolf/ref/arm')
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