diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-04-09 12:13:40 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-04-09 12:13:40 -0400 |
| commit | d9193d1b2039739ef4fb264c742d37f9803817e5 (patch) | |
| tree | 7904829173102a8d8f654873d5cefb790e148298 /tests/long/se/70.twolf/ref/arm | |
| parent | 1d61224a8ba60a2c8cb06e9877b7e548d47bb99a (diff) | |
| download | gem5-d9193d1b2039739ef4fb264c742d37f9803817e5.tar.xz | |
stats: Match current behaviour
Small changes to the branch predictor and BTB caused stats changes
throughout.
Diffstat (limited to 'tests/long/se/70.twolf/ref/arm')
| -rw-r--r-- | tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt | 777 | ||||
| -rw-r--r-- | tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt | 1493 |
2 files changed, 1157 insertions, 1113 deletions
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index fae4160aa..21492b1f0 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.130773 # Number of seconds simulated -sim_ticks 130772642500 # Number of ticks simulated -final_tick 130772642500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.130383 # Number of seconds simulated +sim_ticks 130382890500 # Number of ticks simulated +final_tick 130382890500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 239563 # Simulator instruction rate (inst/s) -host_op_rate 252538 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 181805529 # Simulator tick rate (ticks/s) -host_mem_usage 322304 # Number of bytes of host memory used -host_seconds 719.30 # Real time elapsed on the host +host_inst_rate 248644 # Simulator instruction rate (inst/s) +host_op_rate 262111 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 188134778 # Simulator tick rate (ticks/s) +host_mem_usage 275596 # Number of bytes of host memory used +host_seconds 693.03 # Real time elapsed on the host sim_insts 172317810 # Number of instructions simulated sim_ops 181650743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 138112 # Nu system.physmem.num_reads::cpu.inst 2158 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory system.physmem.num_reads::total 3866 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1056123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 835893 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1892017 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1056123 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1056123 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1056123 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 835893 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1892017 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1059280 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 838392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1897672 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1059280 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1059280 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1059280 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 838392 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1897672 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 3866 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 3866 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 130772548000 # Total gap between requests +system.physmem.totGap 130382796000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3617 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3618 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 236 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 905 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 271.628729 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.806384 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 277.022098 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 259 28.62% 28.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 352 38.90% 67.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 86 9.50% 77.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 59 6.52% 83.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 34 3.76% 87.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 21 2.32% 89.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 17 1.88% 91.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 17 1.88% 93.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 60 6.63% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 905 # Bytes accessed per row activation -system.physmem.totQLat 27654500 # Total ticks spent queuing -system.physmem.totMemAccLat 100142000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 915 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 268.939891 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 176.781102 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 276.529935 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 273 29.84% 29.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 347 37.92% 67.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 83 9.07% 76.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 59 6.45% 83.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 35 3.83% 87.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 24 2.62% 89.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 16 1.75% 91.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 20 2.19% 93.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 58 6.34% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 915 # Bytes accessed per row activation +system.physmem.totQLat 27071500 # Total ticks spent queuing +system.physmem.totMemAccLat 99559000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 19330000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7153.26 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7002.46 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25903.26 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.89 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25752.46 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.89 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.90 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.01 # Data bus utilization in percentage @@ -216,49 +216,53 @@ system.physmem.busUtilRead 0.01 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 2957 # Number of row buffer hits during reads +system.physmem.readRowHits 2948 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.49 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.25 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 33826318.68 # Average gap between requests -system.physmem.pageHitRate 76.49 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3099600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1691250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 16161600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 33725503.36 # Average gap between requests +system.physmem.pageHitRate 76.25 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3144960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1716000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16192800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 8541265200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3568631490 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 75331810500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 87462659640 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.826558 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 125319167750 # Time in different power states -system.physmem_0.memoryStateTime::REF 4366700000 # Time in different power states +system.physmem_0.refreshEnergy 8515837200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3562127505 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 75103936500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 87202954965 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.831686 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 124939990750 # Time in different power states +system.physmem_0.memoryStateTime::REF 4353700000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1084461000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1087339250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3727080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2033625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 13782600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3764880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2054250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13790400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 8541265200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3564306900 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 75335612250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 87460727655 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.811714 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 125325942500 # Time in different power states -system.physmem_1.memoryStateTime::REF 4366700000 # Time in different power states +system.physmem_1.refreshEnergy 8515837200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3544157970 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 75119701500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 87199306200 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.803682 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 124966482000 # Time in different power states +system.physmem_1.memoryStateTime::REF 4353700000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1077991500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1060850750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 49732170 # Number of BP lookups -system.cpu.branchPred.condPredicted 39495980 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5592247 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24154061 # Number of BTB lookups -system.cpu.branchPred.BTBHits 23128262 # Number of BTB hits +system.cpu.branchPred.lookups 49622074 # Number of BP lookups +system.cpu.branchPred.condPredicted 39447439 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5514206 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 24092073 # Number of BTB lookups +system.cpu.branchPred.BTBHits 22843202 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.753099 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1888632 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 94.816258 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1888965 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 142 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 213748 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 207973 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5775 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 40452 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -377,69 +381,104 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 261545285 # number of cpu cycles simulated +system.cpu.numCycles 260765781 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 172317810 # Number of instructions committed system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed -system.cpu.discardedOps 11660914 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 11583006 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.517808 # CPI: cycles per instruction -system.cpu.ipc 0.658845 # IPC: instructions per cycle -system.cpu.tickCycles 255252020 # Number of cycles that the object actually ticked -system.cpu.idleCycles 6293265 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.513284 # CPI: cycles per instruction +system.cpu.ipc 0.660815 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.op_class_0::IntAlu 138988213 76.51% 76.51% # Class of committed instruction +system.cpu.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 32754 0.02% 77.03% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 77.03% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 154829 0.09% 77.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 238880 0.13% 77.25% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 76016 0.04% 77.29% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 437591 0.24% 77.53% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction +system.cpu.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction +system.cpu.op_class_0::MemWrite 12644635 6.96% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 181650743 # Class of committed instruction +system.cpu.tickCycles 254551967 # Number of cycles that the object actually ticked +system.cpu.idleCycles 6213814 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1377.707606 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40756382 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22517.338122 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1378.689350 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40754473 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1811 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22503.850359 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1377.707606 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.336354 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.336354 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1378.689350 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.336594 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.336594 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1769 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1358 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.431641 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 81519460 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 81519460 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 28348467 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28348467 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12362639 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12362639 # number of WriteReq hits +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1359 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.431885 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 81515639 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 81515639 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28346557 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28346557 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12362640 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12362640 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40711106 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40711106 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40711568 # number of overall hits -system.cpu.dcache.overall_hits::total 40711568 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 794 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 794 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1648 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1648 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 40709197 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40709197 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40709659 # number of overall hits +system.cpu.dcache.overall_hits::total 40709659 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 793 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 793 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1647 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1647 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 2442 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2442 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2443 # number of overall misses -system.cpu.dcache.overall_misses::total 2443 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 58082000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 58082000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 126294500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 126294500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 184376500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 184376500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 184376500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 184376500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28349261 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28349261 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2440 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2440 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2441 # number of overall misses +system.cpu.dcache.overall_misses::total 2441 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 59629000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 59629000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 126003000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 126003000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 185632000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 185632000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 185632000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 185632000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28347350 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28347350 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses) @@ -448,10 +487,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 40713548 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 40713548 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 40714011 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 40714011 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 40711637 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 40711637 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 40712100 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 40712100 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses @@ -462,14 +501,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73151.133501 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 73151.133501 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76635.012136 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76635.012136 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 75502.252252 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 75502.252252 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 75471.346705 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 75471.346705 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75194.199243 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 75194.199243 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76504.553734 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76504.553734 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76078.688525 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76078.688525 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76047.521508 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76047.521508 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -480,34 +519,34 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 16 # number of writebacks system.cpu.dcache.writebacks::total 16 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 550 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 550 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 633 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 633 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 633 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 633 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 82 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 548 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 548 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 630 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 630 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 630 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 630 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1098 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1098 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1099 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1099 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1809 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1809 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1810 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51822500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 51822500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85060000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 85060000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 1810 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1811 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1811 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52555500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 52555500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85213000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85213000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 70000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 70000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136882500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 136882500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136952500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 136952500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 137768500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 137768500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 137838500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 137838500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses @@ -518,71 +557,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72886.779184 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72886.779184 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77468.123862 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77468.123862 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73917.721519 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73917.721519 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77536.851683 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77536.851683 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75667.495854 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75667.495854 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75664.364641 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75664.364641 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76115.193370 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76115.193370 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76111.816676 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76111.816676 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 2888 # number of replacements -system.cpu.icache.tags.tagsinuse 1423.991712 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 71011798 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4684 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 15160.503416 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2881 # number of replacements +system.cpu.icache.tags.tagsinuse 1423.942746 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 70779397 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4677 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 15133.503742 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1423.991712 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.695308 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.695308 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1423.942746 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.695285 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.695285 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1796 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 123 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 496 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 122 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1068 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.876953 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 142037650 # Number of tag accesses -system.cpu.icache.tags.data_accesses 142037650 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 71011798 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 71011798 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 71011798 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 71011798 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 71011798 # number of overall hits -system.cpu.icache.overall_hits::total 71011798 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4685 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4685 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4685 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4685 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4685 # number of overall misses -system.cpu.icache.overall_misses::total 4685 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 199916500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 199916500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 199916500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 199916500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 199916500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 199916500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 71016483 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 71016483 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 71016483 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 71016483 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 71016483 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 71016483 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 141572827 # Number of tag accesses +system.cpu.icache.tags.data_accesses 141572827 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 70779397 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 70779397 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 70779397 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 70779397 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 70779397 # number of overall hits +system.cpu.icache.overall_hits::total 70779397 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4678 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4678 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4678 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4678 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4678 # 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number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 70784075 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 70784075 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42671.611526 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42671.611526 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42671.611526 # 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number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -591,135 +630,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 2888 # number of writebacks -system.cpu.icache.writebacks::total 2888 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4685 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4685 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4685 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4685 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4685 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4685 # 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number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1098 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1098 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4685 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 4685 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 2559 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 2559 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1099 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1099 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4678 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 4678 # 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miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.461259 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.887640 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.887640 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.461259 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.951381 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.597844 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461259 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.951381 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.597844 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76447.247706 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76447.247706 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74655.020824 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74655.020824 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78956.487342 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78956.487342 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74655.020824 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77368.176539 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75858.228174 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74655.020824 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77368.176539 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75858.228174 # average overall miss latency +system.cpu.l2cache.demand_accesses::cpu.inst 4678 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1811 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 6489 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4678 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1811 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 6489 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992721 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.992721 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.461950 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.461950 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.886236 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.886236 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.461950 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.950856 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.598397 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461950 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.950856 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.598397 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76516.040330 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76516.040330 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74010.874595 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74010.874595 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80225.039620 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80225.039620 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74010.874595 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77875.145180 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75724.568633 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74010.874595 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77875.145180 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75724.568633 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -738,97 +777,97 @@ system.cpu.l2cache.demand_mshr_hits::total 16 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1090 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1090 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1091 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1091 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2159 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2159 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 618 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 618 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 617 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 617 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2159 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 1708 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 3867 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2159 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3867 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 72427500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 72427500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 139601500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 139601500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 42758500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 42758500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 139601500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 115186000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 254787500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139601500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 115186000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 254787500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992714 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.460832 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.460832 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.867978 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.867978 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.460832 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.595381 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.460832 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.595381 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66447.247706 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66447.247706 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64660.259379 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64660.259379 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69188.511327 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69188.511327 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64660.259379 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67439.110070 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65887.638997 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64660.259379 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67439.110070 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65887.638997 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 72569000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 72569000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 138134000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 138134000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 43490000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 43490000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138134000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 116059000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 254193000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138134000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 116059000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 254193000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992721 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992721 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.461522 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.461522 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.866573 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.866573 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461522 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.595932 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461522 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.595932 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66516.040330 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66516.040330 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63980.546549 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63980.546549 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70486.223663 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70486.223663 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63980.546549 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67950.234192 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65733.902250 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63980.546549 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67950.234192 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65733.902250 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 9425 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 3064 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 9412 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 3057 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 328 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 5396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5389 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2888 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2881 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 26 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 4685 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1099 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1099 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 4678 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 712 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12257 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3662 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 15919 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 484608 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 601472 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12236 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3664 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 15900 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 483712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 600640 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6495 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.071132 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.257064 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 6489 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.071197 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.257174 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 6033 92.89% 92.89% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 462 7.11% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 6027 92.88% 92.88% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 462 7.12% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6495 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7616500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 6489 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7603000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7026998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7016498 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2721986 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2723486 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 2776 # Transaction distribution -system.membus.trans_dist::ReadExReq 1090 # Transaction distribution -system.membus.trans_dist::ReadExResp 1090 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 2776 # Transaction distribution +system.membus.trans_dist::ReadResp 2775 # Transaction distribution +system.membus.trans_dist::ReadExReq 1091 # Transaction distribution +system.membus.trans_dist::ReadExResp 1091 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 2775 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7732 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 7732 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247424 # Cumulative packet size per connected master and slave (bytes) @@ -844,9 +883,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 3866 # Request fanout histogram -system.membus.reqLayer0.occupancy 4535500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4516500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 20543250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20548250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 03798f86c..7b9f789c6 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,65 +1,65 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.085490 # Number of seconds simulated -sim_ticks 85490431000 # Number of ticks simulated -final_tick 85490431000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.084938 # Number of seconds simulated +sim_ticks 84937723500 # Number of ticks simulated +final_tick 84937723500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61561 # Simulator instruction rate (inst/s) -host_op_rate 64896 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 30544518 # Simulator tick rate (ticks/s) -host_mem_usage 301600 # Number of bytes of host memory used -host_seconds 2798.88 # Real time elapsed on the host +host_inst_rate 146803 # Simulator instruction rate (inst/s) +host_op_rate 154755 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 72367413 # Simulator tick rate (ticks/s) +host_mem_usage 271624 # Number of bytes of host memory used +host_seconds 1173.70 # Real time elapsed on the host sim_insts 172303022 # Number of instructions simulated sim_ops 181635954 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 587136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 132032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 70784 # Number of bytes read from this memory -system.physmem.bytes_read::total 789952 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 587136 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 587136 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 9174 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2063 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 1106 # Number of read requests responded to by this memory -system.physmem.num_reads::total 12343 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 6867856 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1544407 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 827976 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9240239 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6867856 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6867856 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6867856 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1544407 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 827976 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9240239 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 12344 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 587328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 132096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 70976 # Number of bytes read from this memory +system.physmem.bytes_read::total 790400 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 587328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 587328 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 9177 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2064 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 1109 # Number of read requests responded to by this memory +system.physmem.num_reads::total 12350 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 6914807 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1555210 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 835624 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9305641 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6914807 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6914807 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6914807 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1555210 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 835624 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9305641 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 12351 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 12344 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 12351 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 790016 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 790464 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 790016 # Total read bytes from the system interface side +system.physmem.bytesReadSys 790464 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1112 # Per bank write bursts -system.physmem.perBankRdBursts::1 371 # Per bank write bursts -system.physmem.perBankRdBursts::2 5091 # Per bank write bursts -system.physmem.perBankRdBursts::3 435 # Per bank write bursts -system.physmem.perBankRdBursts::4 1954 # Per bank write bursts -system.physmem.perBankRdBursts::5 426 # Per bank write bursts -system.physmem.perBankRdBursts::6 266 # Per bank write bursts -system.physmem.perBankRdBursts::7 369 # Per bank write bursts -system.physmem.perBankRdBursts::8 265 # Per bank write bursts -system.physmem.perBankRdBursts::9 221 # Per bank write bursts +system.physmem.perBankRdBursts::0 1113 # Per bank write bursts +system.physmem.perBankRdBursts::1 381 # Per bank write bursts +system.physmem.perBankRdBursts::2 5089 # Per bank write bursts +system.physmem.perBankRdBursts::3 423 # Per bank write bursts +system.physmem.perBankRdBursts::4 1959 # Per bank write bursts +system.physmem.perBankRdBursts::5 424 # Per bank write bursts +system.physmem.perBankRdBursts::6 265 # Per bank write bursts +system.physmem.perBankRdBursts::7 373 # Per bank write bursts +system.physmem.perBankRdBursts::8 266 # Per bank write bursts +system.physmem.perBankRdBursts::9 219 # Per bank write bursts system.physmem.perBankRdBursts::10 295 # Per bank write bursts -system.physmem.perBankRdBursts::11 323 # Per bank write bursts -system.physmem.perBankRdBursts::12 197 # Per bank write bursts +system.physmem.perBankRdBursts::11 324 # Per bank write bursts +system.physmem.perBankRdBursts::12 199 # Per bank write bursts system.physmem.perBankRdBursts::13 249 # Per bank write bursts -system.physmem.perBankRdBursts::14 227 # Per bank write bursts +system.physmem.perBankRdBursts::14 229 # Per bank write bursts system.physmem.perBankRdBursts::15 543 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 85490422000 # Total gap between requests +system.physmem.totGap 84937714500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 12344 # Read request sizes (log2) +system.physmem.readPktSize::6 12351 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,15 +94,15 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 10928 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 977 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 10935 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 975 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 83 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 37 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 85 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see @@ -190,29 +190,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 7242 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 108.822977 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 85.142878 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 132.567115 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 5271 72.78% 72.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 1523 21.03% 93.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 185 2.55% 96.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 87 1.20% 97.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 38 0.52% 98.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 26 0.36% 98.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 17 0.23% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 18 0.25% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 77 1.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 7242 # Bytes accessed per row activation -system.physmem.totQLat 167084529 # Total ticks spent queuing -system.physmem.totMemAccLat 398534529 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 61720000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13535.69 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 7250 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 108.738207 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 85.269087 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 131.624325 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 5249 72.40% 72.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 1564 21.57% 93.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 167 2.30% 96.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 93 1.28% 97.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 42 0.58% 98.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 24 0.33% 98.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 18 0.25% 98.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 21 0.29% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 72 0.99% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 7250 # Bytes accessed per row activation +system.physmem.totQLat 171430514 # Total ticks spent queuing +system.physmem.totMemAccLat 403011764 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 61755000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13879.89 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32285.69 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 9.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 32629.89 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 9.31 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 9.24 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 9.31 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.07 # Data bus utilization in percentage @@ -220,49 +220,53 @@ system.physmem.busUtilRead 0.07 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 5095 # Number of row buffer hits during reads +system.physmem.readRowHits 5094 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 41.28 # Row buffer hit rate for reads +system.physmem.readRowHitRate 41.24 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 6925666.07 # Average gap between requests -system.physmem.pageHitRate 41.28 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 48527640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 26478375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 78156000 # Energy for read commands per rank (pJ) +system.physmem.avgGap 6876990.89 # Average gap between requests +system.physmem.pageHitRate 41.24 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 48452040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 26437125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 78179400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5583480240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 17009559810 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 36370632750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 59116834815 # Total energy per rank (pJ) -system.physmem_0.averagePower 691.542258 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 60400646468 # Time in different power states -system.physmem_0.memoryStateTime::REF 2854540000 # Time in different power states +system.physmem_0.refreshEnergy 5547372480 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 16645874445 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 36357960750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 58704276240 # Total energy per rank (pJ) +system.physmem_0.averagePower 691.186004 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 60381088491 # Time in different power states +system.physmem_0.memoryStateTime::REF 2836080000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 22233687032 # Time in different power states +system.physmem_0.memoryStateTime::ACT 21718991509 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6199200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3382500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 17869800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 6335280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3456750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 17877600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5583480240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3325437855 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 48374248500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 57310618095 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.413332 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 80466021414 # Time in different power states -system.physmem_1.memoryStateTime::REF 2854540000 # Time in different power states +system.physmem_1.refreshEnergy 5547372480 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3295031490 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 48069226500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 56939300100 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.405119 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 79958437412 # Time in different power states +system.physmem_1.memoryStateTime::REF 2836080000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2165082586 # Time in different power states +system.physmem_1.memoryStateTime::ACT 2138239588 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 85927149 # Number of BP lookups -system.cpu.branchPred.condPredicted 68408695 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6018080 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 40104766 # Number of BTB lookups -system.cpu.branchPred.BTBHits 39018080 # Number of BTB hits +system.cpu.branchPred.lookups 85626366 # Number of BP lookups +system.cpu.branchPred.condPredicted 68177013 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5935452 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 39946926 # Number of BTB lookups +system.cpu.branchPred.BTBHits 38187698 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.290382 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3702096 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 81897 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 95.596087 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3683716 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 81912 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 681689 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 653746 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 27943 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 40316 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -381,233 +385,233 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 170980863 # number of cpu cycles simulated +system.cpu.numCycles 169875448 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5755157 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 349305240 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85927149 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42720176 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 158448180 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 12049937 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 2618 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 5671940 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 347162762 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85626366 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42525160 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 157499775 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11884731 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2609 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 3916 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 78960236 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 19348 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 170234862 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.146650 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.050166 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3808 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 78326624 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 18246 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 169120520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.147875 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.049260 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 17669518 10.38% 10.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30211265 17.75% 28.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31838913 18.70% 46.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 90515166 53.17% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 17456404 10.32% 10.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30071791 17.78% 28.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31598997 18.68% 46.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 89993328 53.21% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 170234862 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.502554 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.042949 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17700032 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 17289472 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 122672401 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6722857 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5850100 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11135652 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 190021 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 306632940 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27644957 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5850100 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37887834 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8551246 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 582035 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 108933106 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8430541 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 278671233 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13418761 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3051568 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 841704 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2280860 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 35921 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 27095 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 483139430 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1196998780 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 297599206 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3005965 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 169120520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.504054 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.043631 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17509987 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 17244874 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 121866560 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6731455 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5767644 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11064434 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 189777 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 304997911 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27240618 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5767644 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37477523 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8502539 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 578983 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 108355768 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8438063 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 277420851 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13180734 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3058487 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 843003 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2280960 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 36243 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 27083 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 481449871 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1191735135 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 296461789 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3004325 # Number of floating rename lookups system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 190162501 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 23526 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23429 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13338905 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 34139598 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14476816 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2548575 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1784456 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 264827834 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 45856 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 214914585 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5192491 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 83237736 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 219939522 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 640 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 170234862 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.262459 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.017804 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 188472942 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 23603 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23603 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13353784 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 33915046 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14407100 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2540378 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1803003 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 263798584 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 45955 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 214411803 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5187874 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 82208585 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 217092419 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 739 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 169120520 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.267805 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.017994 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 53140673 31.22% 31.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 36118420 21.22% 52.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 65796647 38.65% 91.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 13561298 7.97% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1570362 0.92% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 47243 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 219 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52408217 30.99% 30.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 35940187 21.25% 52.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 65510990 38.74% 90.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13642635 8.07% 99.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1570936 0.93% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 47343 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 212 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 170234862 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 169120520 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35603971 66.12% 66.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 152944 0.28% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 1066 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 35746 0.07% 66.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 240 0.00% 66.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 952 0.00% 66.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 34296 0.06% 66.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.54% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 14072260 26.13% 92.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3948482 7.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35659439 66.16% 66.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 153265 0.28% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 1066 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 35730 0.07% 66.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 240 0.00% 66.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 958 0.00% 66.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 34286 0.06% 66.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 14056522 26.08% 92.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3955910 7.34% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 167357330 77.87% 77.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 918980 0.43% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33017 0.02% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 165190 0.08% 78.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 245699 0.11% 78.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 460522 0.21% 78.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206694 0.10% 78.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 32005177 14.89% 93.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13374016 6.22% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 166992897 77.88% 77.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 919175 0.43% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33015 0.02% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 165179 0.08% 78.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 245702 0.11% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 460499 0.21% 78.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206683 0.10% 78.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 31868874 14.86% 93.76% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13371819 6.24% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 214914585 # Type of FU issued -system.cpu.iq.rate 1.256951 # Inst issue rate -system.cpu.iq.fu_busy_cnt 53850162 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.250565 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 655153476 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 346106935 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 204606292 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3953209 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2011310 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1806290 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266630626 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2134121 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1600828 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 214411803 # Type of FU issued +system.cpu.iq.rate 1.262171 # Inst issue rate +system.cpu.iq.fu_busy_cnt 53897621 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.251374 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 653076785 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 344050437 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 204251594 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3952836 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2009578 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1806333 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266175663 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2133761 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1598827 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6243454 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7546 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6949 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1832182 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6018902 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7447 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7034 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1762466 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 25935 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 794 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 25527 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 769 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5850100 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5682962 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 61282 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 264889651 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 5767644 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5618767 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 62916 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 263864756 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 34139598 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14476816 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23448 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3916 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 54251 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6949 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3234598 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3248118 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6482716 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 207529725 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 30719767 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7384860 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 33915046 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14407100 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23547 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3855 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 55872 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 7034 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3149041 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3246654 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6395695 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 207125960 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 30633355 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7285843 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 15961 # number of nop insts executed -system.cpu.iew.exec_refs 43859608 # number of memory reference insts executed -system.cpu.iew.exec_branches 44936158 # Number of branches executed -system.cpu.iew.exec_stores 13139841 # Number of stores executed -system.cpu.iew.exec_rate 1.213760 # Inst execution rate -system.cpu.iew.wb_sent 206746993 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 206412582 # cumulative count of insts written-back -system.cpu.iew.wb_producers 129474820 # num instructions producing a value -system.cpu.iew.wb_consumers 221691878 # num instructions consuming a value -system.cpu.iew.wb_rate 1.207226 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.584031 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 69543013 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 20217 # number of nop insts executed +system.cpu.iew.exec_refs 43771495 # number of memory reference insts executed +system.cpu.iew.exec_branches 44852998 # Number of branches executed +system.cpu.iew.exec_stores 13138140 # Number of stores executed +system.cpu.iew.exec_rate 1.219281 # Inst execution rate +system.cpu.iew.wb_sent 206368045 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 206057927 # cumulative count of insts written-back +system.cpu.iew.wb_producers 129397136 # num instructions producing a value +system.cpu.iew.wb_consumers 221651580 # num instructions consuming a value +system.cpu.iew.wb_rate 1.212994 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.583786 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 68672645 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5843212 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158791205 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.143957 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.645227 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5760731 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 157823719 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.150970 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.652577 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 73988497 46.59% 46.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 41295308 26.01% 72.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 22556711 14.21% 86.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9630949 6.07% 92.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3552216 2.24% 95.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2148211 1.35% 96.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1284578 0.81% 97.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 986502 0.62% 97.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3348233 2.11% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 73232232 46.40% 46.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 41142749 26.07% 72.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 22534270 14.28% 86.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9514853 6.03% 92.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3552076 2.25% 95.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2143258 1.36% 96.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1327703 0.84% 97.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1008942 0.64% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3367636 2.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158791205 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 157823719 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317410 # Number of instructions committed system.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -653,382 +657,383 @@ system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 181650342 # Class of committed instruction -system.cpu.commit.bw_lim_events 3348233 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 406631126 # The number of ROB reads -system.cpu.rob.rob_writes 513844376 # The number of ROB writes -system.cpu.timesIdled 8957 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 746001 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3367636 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 404773869 # The number of ROB reads +system.cpu.rob.rob_writes 511956769 # The number of ROB writes +system.cpu.timesIdled 9030 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 754928 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303022 # Number of Instructions Simulated system.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.992327 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.992327 # CPI: Total CPI of All Threads -system.cpu.ipc 1.007733 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.007733 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 218966992 # number of integer regfile reads -system.cpu.int_regfile_writes 114516229 # number of integer regfile writes -system.cpu.fp_regfile_reads 2904204 # number of floating regfile reads -system.cpu.fp_regfile_writes 2441504 # number of floating regfile writes -system.cpu.cc_regfile_reads 709589080 # number of cc regfile reads -system.cpu.cc_regfile_writes 229556340 # number of cc regfile writes -system.cpu.misc_regfile_reads 59312089 # number of misc regfile reads +system.cpu.cpi 0.985911 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.985911 # CPI: Total CPI of All Threads +system.cpu.ipc 1.014290 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.014290 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 218725741 # number of integer regfile reads +system.cpu.int_regfile_writes 114168991 # number of integer regfile writes +system.cpu.fp_regfile_reads 2904222 # number of floating regfile reads +system.cpu.fp_regfile_writes 2441435 # number of floating regfile writes +system.cpu.cc_regfile_reads 708194084 # number of cc regfile reads +system.cpu.cc_regfile_writes 229512691 # number of cc regfile writes +system.cpu.misc_regfile_reads 59249211 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.dcache.tags.replacements 72854 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.416253 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 41114439 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 73366 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 560.401807 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 507537500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.416253 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998860 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998860 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 72581 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.413915 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 41031177 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 73093 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 561.355766 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 508221500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.413915 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998855 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998855 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 231 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 42 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 229 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 44 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 82527906 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 82527906 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 28728233 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28728233 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12341290 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12341290 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 361 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 361 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 82360603 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 82360603 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28644947 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28644947 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12341311 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12341311 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 364 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 364 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22148 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22148 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41069523 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41069523 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41069884 # number of overall hits -system.cpu.dcache.overall_hits::total 41069884 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89457 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89457 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 22997 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 22997 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 118 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 118 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 40986258 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40986258 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40986622 # number of overall hits +system.cpu.dcache.overall_hits::total 40986622 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89227 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89227 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 22976 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22976 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 116 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 116 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 259 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 259 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 112454 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 112454 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 112572 # number of overall misses -system.cpu.dcache.overall_misses::total 112572 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1065753500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1065753500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 241354499 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 241354499 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2315500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 2315500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1307107999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1307107999 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1307107999 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1307107999 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28817690 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28817690 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 112203 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 112203 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 112319 # number of overall misses +system.cpu.dcache.overall_misses::total 112319 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1066843000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1066843000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 241030499 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 241030499 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2297500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 2297500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1307873499 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1307873499 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1307873499 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1307873499 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28734174 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28734174 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 479 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 479 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 480 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 480 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41181977 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41181977 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41182456 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41182456 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003104 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003104 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001860 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001860 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.246347 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.246347 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 41098461 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41098461 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41098941 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41098941 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003105 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003105 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001858 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001858 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.241667 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.241667 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011559 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011559 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002731 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002731 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002730 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002730 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002733 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002733 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11913.584180 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11913.584180 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10495.042788 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10495.042788 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8940.154440 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8940.154440 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 11623.490485 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 11623.490485 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 11611.306533 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 11611.306533 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11956.504197 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11956.504197 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10490.533557 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10490.533557 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8870.656371 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8870.656371 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 11656.314885 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 11656.314885 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 11644.276561 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 11644.276561 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 166 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 10450 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 10738 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 866 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 864 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 83 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 12.066975 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 12.428241 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 72854 # number of writebacks -system.cpu.dcache.writebacks::total 72854 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24777 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 24777 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14426 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 14426 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 72581 # number of writebacks +system.cpu.dcache.writebacks::total 72581 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24802 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 24802 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14421 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 14421 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 259 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 259 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 39203 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 39203 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 39203 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 39203 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64680 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64680 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8571 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 8571 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 115 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 115 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 73251 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 73251 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 73366 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 73366 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 654439000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 654439000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86279999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 86279999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 978000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 978000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 740718999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 740718999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 741696999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 741696999 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002244 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002244 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000693 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000693 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.240084 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.240084 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001779 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001779 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001781 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001781 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10118.104515 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10118.104515 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10066.503208 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10066.503208 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8504.347826 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8504.347826 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10112.066716 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 10112.066716 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10109.546643 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 10109.546643 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 39223 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 39223 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 39223 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 39223 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64425 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 64425 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8555 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 8555 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 113 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 113 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 72980 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 72980 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 73093 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 73093 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 653903000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 653903000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85317499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85317499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 962000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 962000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 739220499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 739220499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 740182499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 740182499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002242 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002242 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000692 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000692 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.235417 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.235417 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001776 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001776 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001778 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001778 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10149.833139 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10149.833139 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9972.822794 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9972.822794 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8513.274336 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8513.274336 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10129.083297 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 10129.083297 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10126.585295 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 10126.585295 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 54401 # number of replacements -system.cpu.icache.tags.tagsinuse 510.602972 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 78901806 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 54913 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1436.851128 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 84733597500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.602972 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997271 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997271 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 53623 # number of replacements +system.cpu.icache.tags.tagsinuse 510.594536 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78269055 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 54135 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1445.812413 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 84183071500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.594536 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997255 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997255 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 48 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 51 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 157975329 # Number of tag accesses -system.cpu.icache.tags.data_accesses 157975329 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 78901806 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78901806 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78901806 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78901806 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78901806 # number of overall hits -system.cpu.icache.overall_hits::total 78901806 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 58402 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 58402 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 58402 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 58402 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 58402 # number of overall misses -system.cpu.icache.overall_misses::total 58402 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1157058425 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1157058425 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1157058425 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1157058425 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1157058425 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1157058425 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78960208 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78960208 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78960208 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78960208 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78960208 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78960208 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000740 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000740 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000740 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000740 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000740 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000740 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19811.965772 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19811.965772 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19811.965772 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19811.965772 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19811.965772 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19811.965772 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 72401 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 156707315 # Number of tag accesses +system.cpu.icache.tags.data_accesses 156707315 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 78269055 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 78269055 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 78269055 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 78269055 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 78269055 # number of overall hits +system.cpu.icache.overall_hits::total 78269055 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 57535 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 57535 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 57535 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 57535 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 57535 # number of overall misses +system.cpu.icache.overall_misses::total 57535 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1155198430 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1155198430 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1155198430 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1155198430 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1155198430 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1155198430 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 78326590 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 78326590 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 78326590 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 78326590 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 78326590 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 78326590 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000735 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000735 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000735 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000735 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000735 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000735 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20078.185974 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20078.185974 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20078.185974 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20078.185974 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20078.185974 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20078.185974 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 73195 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 27 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3397 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3246 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 21.313218 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 22.549291 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 13.500000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 54401 # number of writebacks -system.cpu.icache.writebacks::total 54401 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3488 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3488 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3488 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1043630451 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1043630451 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1043630451 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000695 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000695 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000695 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000695 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000695 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000695 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19004.815730 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1039886452 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1039886452 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1039886452 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000691 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000691 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000691 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19208.778853 # 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Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 2944 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 24 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 87 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 141 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 856 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 162 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1653 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1022 0.015503 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.179749 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 851088649 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027315 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027315 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167079 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.167079 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.028227 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.028227 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167079 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.028119 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.087605 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167079 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.028119 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027140 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027140 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.169536 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.169536 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.028385 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.028385 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.169536 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.028238 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.088360 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.169536 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.028238 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.103555 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 32702.175464 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 32702.175464 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73817.796610 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73817.796610 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68928.283379 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68928.283379 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70928.845101 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70928.845101 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68928.283379 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71259.331071 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69356.202171 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68928.283379 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71259.331071 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 32702.175464 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63710.753613 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.104135 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34294.294469 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 34294.294469 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70476.495726 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70476.495726 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69132.327304 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69132.327304 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71733.333333 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71733.333333 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69132.327304 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71590.843023 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69583.703967 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69132.327304 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71590.843023 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34294.294469 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64237.953732 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 255535 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 127274 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10474 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 11941 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3419 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 8522 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 119639 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 64840 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 62415 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 11001 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 2383 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 8640 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 8640 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 54914 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 64726 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 164228 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 219586 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 383814 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6996096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9358080 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 16354176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 13384 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 141664 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.218517 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.539520 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 253433 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 126224 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10473 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 11905 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3377 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 8528 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 118606 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 64698 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 61506 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 11007 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 2350 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 8622 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 8622 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 54136 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 64471 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 161894 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218767 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 380661 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6896512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9323136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 16219648 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 13357 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 140586 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.219979 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.541213 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 119230 84.16% 84.16% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 13912 9.82% 93.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 8522 6.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 118188 84.07% 84.07% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 13870 9.87% 93.93% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 8528 6.07% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 141664 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 255022500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 140586 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 252920500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 82377983 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 81207989 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 110053990 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 109644490 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 12107 # Transaction distribution -system.membus.trans_dist::ReadExReq 236 # Transaction distribution -system.membus.trans_dist::ReadExResp 236 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 12108 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 24687 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 24687 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 789952 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 789952 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 12116 # Transaction distribution +system.membus.trans_dist::ReadExReq 234 # Transaction distribution +system.membus.trans_dist::ReadExResp 234 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 12117 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 24701 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 24701 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 790400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 790400 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 12344 # Request fanout histogram +system.membus.snoop_fanout::samples 12351 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 12344 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 12351 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 12344 # Request fanout histogram -system.membus.reqLayer0.occupancy 15598659 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 12351 # Request fanout histogram +system.membus.reqLayer0.occupancy 15618188 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 66476550 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 66520835 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |