diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-13 12:30:30 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-13 12:30:30 -0600 |
| commit | 0d46708dc20c438d29bd724fb7d4b54d4d2f318a (patch) | |
| tree | 337e1a7404c57817cd08106a0369542ea5c4ac30 /tests/long/se/70.twolf/ref/arm | |
| parent | 9b05e96b9efdb9cdcc4e40ef9c96b1228df7a175 (diff) | |
| download | gem5-0d46708dc20c438d29bd724fb7d4b54d4d2f318a.tar.xz | |
bp: fix up stats for changes to branch predictor
Diffstat (limited to 'tests/long/se/70.twolf/ref/arm')
| -rwxr-xr-x | tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout | 8 | ||||
| -rw-r--r-- | tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt | 1055 |
2 files changed, 538 insertions, 525 deletions
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout index d10088405..8c858c201 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 16:37:09 +gem5 compiled Feb 12 2012 17:19:56 +gem5 started Feb 12 2012 20:58:01 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing +Couldn't unlink build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing/smred.sav +Couldn't unlink build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -21,4 +23,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 105850842000 because target called exit() +122 123 124 Exiting @ tick 88632152500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 98dddaff0..64cc4b80a 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,25 +1,25 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.105851 # Number of seconds simulated -sim_ticks 105850842000 # Number of ticks simulated -final_tick 105850842000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.088632 # Number of seconds simulated +sim_ticks 88632152500 # Number of ticks simulated +final_tick 88632152500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 122767 # Simulator instruction rate (inst/s) -host_op_rate 134419 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 75414821 # Simulator tick rate (ticks/s) -host_mem_usage 227032 # Number of bytes of host memory used -host_seconds 1403.58 # Real time elapsed on the host -sim_insts 172314144 # Number of instructions simulated -sim_ops 188667627 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 239936 # Number of bytes read from this memory -system.physmem.bytes_inst_read 128320 # Number of instructions bytes read from this memory +host_inst_rate 134694 # Simulator instruction rate (inst/s) +host_op_rate 147478 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69281557 # Simulator tick rate (ticks/s) +host_mem_usage 227272 # Number of bytes of host memory used +host_seconds 1279.30 # Real time elapsed on the host +sim_insts 172315139 # Number of instructions simulated +sim_ops 188668622 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 244352 # Number of bytes read from this memory +system.physmem.bytes_inst_read 132032 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 3749 # Number of read requests responded to by this memory +system.physmem.num_reads 3818 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2266737 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1212272 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2266737 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 2756923 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1489663 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 2756923 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -63,315 +63,315 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 211701685 # number of cpu cycles simulated +system.cpu.numCycles 177264306 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 102100879 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 80677195 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 9930193 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 84233443 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 79245701 # Number of BTB hits +system.cpu.BPredUnit.lookups 96525090 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 74749964 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 6668938 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 46796658 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 44215963 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 4698090 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 111402 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 44542965 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 416708415 # Number of instructions fetch has processed -system.cpu.fetch.Branches 102100879 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 83943791 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 108793327 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 33207424 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 35058719 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 11 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 259 # Number of stall cycles due to pending traps +system.cpu.BPredUnit.usedRAS 4389679 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 114813 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 39966229 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 381133369 # Number of instructions fetch has processed +system.cpu.fetch.Branches 96525090 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48605642 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80754991 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 27412697 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 35762422 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9389 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.CacheLines 40619675 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2204435 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 211643202 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.135620 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.646860 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 36758976 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1679336 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 177207232 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.350259 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.058598 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 103052143 48.69% 48.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4614041 2.18% 50.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 32953123 15.57% 66.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 18235328 8.62% 75.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 9171108 4.33% 79.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 12530200 5.92% 85.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 8476968 4.01% 89.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4316297 2.04% 91.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 18293994 8.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 96615622 54.52% 54.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5430463 3.06% 57.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10300720 5.81% 63.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10325695 5.83% 69.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8756862 4.94% 74.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6889395 3.89% 78.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6237128 3.52% 81.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8634116 4.87% 86.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 24017231 13.55% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 211643202 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.482287 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.968376 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 53231519 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 33609414 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 100494512 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1217161 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 23090596 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14181130 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 166488 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 422617374 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 695976 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 23090596 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 62189594 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 455687 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 28663702 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 92677243 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4566380 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 388527700 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 20997 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2241803 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 666137382 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1656361753 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1638646831 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 17714922 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 298061936 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 368075446 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2723266 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2675408 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 23504222 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 46900559 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16903337 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3858030 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2525525 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 332647611 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2225423 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 261830951 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 960204 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 143464205 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 342029155 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 589405 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 211643202 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.237134 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.489338 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 177207232 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.544526 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.150085 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 46183847 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 34297054 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74780894 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1386206 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 20559231 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14846637 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 165269 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 392589126 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 748420 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 20559231 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 52356007 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 443712 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 29007637 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 69958724 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4881921 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 367191514 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 92621 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2515930 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 627979317 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1558602975 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1541578337 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 17024638 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 298063528 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 329915789 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2303042 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2294526 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 21773052 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 41898813 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 15562062 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3360389 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2124393 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 324040554 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2103109 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 248819756 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 576048 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 136002156 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 346792965 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 466892 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 177207232 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.404117 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.633607 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 97826086 46.22% 46.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 37864076 17.89% 64.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34104807 16.11% 80.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 22781361 10.76% 90.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 11447248 5.41% 96.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4765675 2.25% 98.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2321089 1.10% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 393603 0.19% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 139257 0.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 78492090 44.29% 44.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 28577659 16.13% 60.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 26660356 15.04% 75.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 21359445 12.05% 87.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12490578 7.05% 94.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 5763951 3.25% 97.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3149996 1.78% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 544249 0.31% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 168908 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 211643202 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 177207232 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 397917 18.24% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5522 0.25% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 50 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 46 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1324685 60.73% 79.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 453082 20.77% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 627952 27.03% 27.03% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5535 0.24% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 48 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 1 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1223626 52.68% 79.95% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 465789 20.05% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 204918446 78.26% 78.26% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 928788 0.35% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33078 0.01% 78.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 166576 0.06% 78.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 257183 0.10% 78.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76398 0.03% 78.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 467924 0.18% 79.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 207596 0.08% 79.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71825 0.03% 79.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 325 0.00% 79.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 40744644 15.56% 94.67% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13958168 5.33% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 194916381 78.34% 78.34% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 997256 0.40% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33202 0.01% 78.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 163976 0.07% 78.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 252533 0.10% 78.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76462 0.03% 78.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 463893 0.19% 79.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206151 0.08% 79.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71843 0.03% 79.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.25% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 37907135 15.23% 94.48% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13730603 5.52% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 261830951 # Type of FU issued -system.cpu.iq.rate 1.236792 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2181302 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008331 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 734699293 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 476117347 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 242859396 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3747317 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2232204 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1844998 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 262127165 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1885088 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1590290 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 248819756 # Type of FU issued +system.cpu.iq.rate 1.403665 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2322951 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009336 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 674003670 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 460004017 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 236904190 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3742073 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2153997 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1836768 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 249257876 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1884831 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1793335 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 17048851 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 31549 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12762 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4256480 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 12046906 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 20817 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12587 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2915006 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 20 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 150 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 23090596 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 13781 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 840 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 334926486 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 3752435 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 46900559 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16903337 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2201532 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 340 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 255 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12762 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 9994816 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1695108 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 11689924 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 249206258 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 38606621 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 12624693 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 20559231 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 11749 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 500 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 326199297 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1048998 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 41898813 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 15562062 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2080622 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 86 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 254 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12587 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4245338 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3938864 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8184202 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 241936044 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 36336721 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6883712 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 53452 # number of nop insts executed -system.cpu.iew.exec_refs 52203623 # number of memory reference insts executed -system.cpu.iew.exec_branches 52584405 # Number of branches executed -system.cpu.iew.exec_stores 13597002 # Number of stores executed -system.cpu.iew.exec_rate 1.177158 # Inst execution rate -system.cpu.iew.wb_sent 246234772 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 244704394 # cumulative count of insts written-back -system.cpu.iew.wb_producers 148512928 # num instructions producing a value -system.cpu.iew.wb_consumers 247801271 # num instructions consuming a value +system.cpu.iew.exec_nop 55634 # number of nop insts executed +system.cpu.iew.exec_refs 49775211 # number of memory reference insts executed +system.cpu.iew.exec_branches 53836233 # Number of branches executed +system.cpu.iew.exec_stores 13438490 # Number of stores executed +system.cpu.iew.exec_rate 1.364832 # Inst execution rate +system.cpu.iew.wb_sent 239697329 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 238740958 # cumulative count of insts written-back +system.cpu.iew.wb_producers 143497606 # num instructions producing a value +system.cpu.iew.wb_consumers 250089451 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.155893 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.599323 # average fanout of values written-back +system.cpu.iew.wb_rate 1.346808 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.573785 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 172328532 # The number of committed instructions -system.cpu.commit.commitCommittedOps 188682015 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 146244510 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1636018 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9791900 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 188552607 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.000686 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.681539 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 172329527 # The number of committed instructions +system.cpu.commit.commitCommittedOps 188683010 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 137516300 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1636217 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 6533063 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 156648002 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.204503 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.917568 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 105375521 55.89% 55.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 40844225 21.66% 77.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 19484606 10.33% 87.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8759294 4.65% 92.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4914501 2.61% 95.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2011973 1.07% 96.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1708688 0.91% 97.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1009693 0.54% 97.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4444106 2.36% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 79778069 50.93% 50.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 37231664 23.77% 74.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15824405 10.10% 84.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8489087 5.42% 90.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4756905 3.04% 93.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1480671 0.95% 94.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1767391 1.13% 95.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1258526 0.80% 96.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6061284 3.87% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 188552607 # Number of insts commited each cycle -system.cpu.commit.committedInsts 172328532 # Number of instructions committed -system.cpu.commit.committedOps 188682015 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 156648002 # Number of insts commited each cycle +system.cpu.commit.committedInsts 172329527 # Number of instructions committed +system.cpu.commit.committedOps 188683010 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 42498565 # Number of memory references committed -system.cpu.commit.loads 29851708 # Number of loads committed +system.cpu.commit.refs 42498963 # Number of memory references committed +system.cpu.commit.loads 29851907 # Number of loads committed system.cpu.commit.membars 22408 # Number of memory barriers committed -system.cpu.commit.branches 40283906 # Number of branches committed +system.cpu.commit.branches 40284105 # Number of branches committed system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. -system.cpu.commit.int_insts 150115117 # Number of committed integer instructions. +system.cpu.commit.int_insts 150115913 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4444106 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6061284 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 519029825 # The number of ROB reads -system.cpu.rob.rob_writes 693007050 # The number of ROB writes -system.cpu.timesIdled 1719 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 58483 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 172314144 # Number of Instructions Simulated -system.cpu.committedOps 188667627 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 172314144 # Number of Instructions Simulated -system.cpu.cpi 1.228580 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.228580 # CPI: Total CPI of All Threads -system.cpu.ipc 0.813948 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.813948 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1111988877 # number of integer regfile reads -system.cpu.int_regfile_writes 407368356 # number of integer regfile writes -system.cpu.fp_regfile_reads 2928539 # number of floating regfile reads -system.cpu.fp_regfile_writes 2498508 # number of floating regfile writes -system.cpu.misc_regfile_reads 502946356 # number of misc regfile reads -system.cpu.misc_regfile_writes 824482 # number of misc regfile writes -system.cpu.icache.replacements 1934 # number of replacements -system.cpu.icache.tagsinuse 1329.301324 # Cycle average of tags in use -system.cpu.icache.total_refs 40615441 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 3640 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11158.088187 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 476780827 # The number of ROB reads +system.cpu.rob.rob_writes 673054212 # The number of ROB writes +system.cpu.timesIdled 1680 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 57074 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 172315139 # Number of Instructions Simulated +system.cpu.committedOps 188668622 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 172315139 # Number of Instructions Simulated +system.cpu.cpi 1.028722 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.028722 # CPI: Total CPI of All Threads +system.cpu.ipc 0.972080 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.972080 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1073592031 # number of integer regfile reads +system.cpu.int_regfile_writes 384645437 # number of integer regfile writes +system.cpu.fp_regfile_reads 2906196 # number of floating regfile reads +system.cpu.fp_regfile_writes 2487132 # number of floating regfile writes +system.cpu.misc_regfile_reads 464057527 # number of misc regfile reads +system.cpu.misc_regfile_writes 824880 # number of misc regfile writes +system.cpu.icache.replacements 2566 # number of replacements +system.cpu.icache.tagsinuse 1366.287383 # Cycle average of tags in use +system.cpu.icache.total_refs 36753975 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4308 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 8531.563370 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1329.301324 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.649073 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.649073 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 40615441 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 40615441 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 40615441 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 40615441 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 40615441 # number of overall hits -system.cpu.icache.overall_hits::total 40615441 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4234 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4234 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4234 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4234 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4234 # number of overall misses -system.cpu.icache.overall_misses::total 4234 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 101275500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 101275500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 101275500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 101275500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 101275500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 101275500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 40619675 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 40619675 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 40619675 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 40619675 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 40619675 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 40619675 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000104 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000104 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000104 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23919.579594 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23919.579594 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23919.579594 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1366.287383 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.667133 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.667133 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 36753975 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 36753975 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 36753975 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 36753975 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 36753975 # number of overall hits +system.cpu.icache.overall_hits::total 36753975 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5001 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5001 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5001 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5001 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5001 # number of overall misses +system.cpu.icache.overall_misses::total 5001 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 108825000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 108825000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 108825000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 108825000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 108825000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 108825000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 36758976 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 36758976 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 36758976 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 36758976 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 36758976 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 36758976 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000136 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000136 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000136 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21760.647870 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21760.647870 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21760.647870 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -380,214 +380,219 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 594 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 594 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 594 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 594 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 594 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 594 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3640 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 3640 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 3640 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 3640 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 3640 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 3640 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 74572500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 74572500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 74572500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 74572500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 74572500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 74572500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000090 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000090 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000090 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20486.950549 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20486.950549 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20486.950549 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 692 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 692 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 692 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 692 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 692 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 692 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4309 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4309 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4309 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4309 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4309 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4309 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 78064500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 78064500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 78064500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 78064500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 78064500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 78064500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18116.616384 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18116.616384 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18116.616384 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 53 # number of replacements -system.cpu.dcache.tagsinuse 1403.723956 # Cycle average of tags in use -system.cpu.dcache.total_refs 48643693 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1846 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 26350.862947 # Average number of references to valid blocks. +system.cpu.dcache.replacements 55 # number of replacements +system.cpu.dcache.tagsinuse 1415.234721 # Cycle average of tags in use +system.cpu.dcache.total_refs 46401176 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1864 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 24893.334764 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1403.723956 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.342706 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.342706 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 36234545 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 36234545 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12356727 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12356727 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 27791 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 27791 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 24630 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 24630 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 48591272 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 48591272 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 48591272 # number of overall hits -system.cpu.dcache.overall_hits::total 48591272 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1808 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1808 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 7560 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 7560 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 1415.234721 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.345516 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.345516 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 33991693 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 33991693 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12356758 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12356758 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 27891 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 27891 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 24829 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 24829 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 46348451 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 46348451 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 46348451 # number of overall hits +system.cpu.dcache.overall_hits::total 46348451 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1783 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1783 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 7529 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 7529 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9368 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9368 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9368 # number of overall misses -system.cpu.dcache.overall_misses::total 9368 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 59529000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 59529000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 237156500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 237156500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 63500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 63500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 296685500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 296685500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 296685500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 296685500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 36236353 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 36236353 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9312 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9312 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9312 # number of overall misses +system.cpu.dcache.overall_misses::total 9312 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 58909500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 58909500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 235574500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 235574500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 64000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 64000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 294484000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 294484000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 294484000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 294484000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 33993476 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 33993476 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 27793 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 27793 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 24630 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 24630 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 48600640 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 48600640 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 48600640 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 48600640 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000050 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000611 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 27893 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 27893 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 24829 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 24829 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46357763 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46357763 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46357763 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46357763 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000052 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000609 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000072 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000193 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000193 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32925.331858 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31369.907407 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31670.100342 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31670.100342 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.000201 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000201 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33039.540101 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31288.949396 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 32000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31624.140893 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31624.140893 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 20000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 20000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 18 # number of writebacks -system.cpu.dcache.writebacks::total 18 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1053 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1053 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6469 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6469 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 20 # number of writebacks +system.cpu.dcache.writebacks::total 20 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1009 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1009 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6438 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6438 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7522 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7522 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7522 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7522 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 755 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 755 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 7447 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7447 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7447 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7447 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 774 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 774 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1091 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1091 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1846 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1846 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1846 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1846 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24116500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24116500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 38344000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 38344000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62460500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 62460500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62460500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 62460500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 1865 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1865 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1865 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1865 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24707500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24707500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 38314500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 38314500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63022000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 63022000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63022000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 63022000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000038 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000038 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31942.384106 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35145.737855 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33835.590466 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33835.590466 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31921.834625 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35118.698442 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33791.957105 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33791.957105 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 1923.480613 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1714 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2676 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.640508 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 1978.402021 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2325 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2747 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.846378 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 4.004344 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1392.392495 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 527.083774 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 4.009293 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1435.553811 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 538.838917 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000122 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.042492 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.016085 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.058700 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 1633 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 81 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1714 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 18 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 18 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 9 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 9 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1633 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 90 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1723 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1633 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 90 # number of overall hits -system.cpu.l2cache.overall_hits::total 1723 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2007 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 674 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 2681 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 1082 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1082 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2007 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1756 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 3763 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2007 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1756 # number of overall misses -system.cpu.l2cache.overall_misses::total 3763 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 68771500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 23150500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 91922000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 37184000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 37184000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 68771500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 60334500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 129106000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 68771500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 60334500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 129106000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 3640 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 755 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 4395 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1091 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1091 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 3640 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1846 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 5486 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 3640 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1846 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 5486 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.551374 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.892715 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.991751 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.551374 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.951246 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.551374 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.951246 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34265.819631 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34347.922849 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34365.988909 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34265.819631 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34359.054670 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34265.819631 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34359.054670 # average overall miss latency +system.cpu.l2cache.occ_percent::cpu.inst 0.043810 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.016444 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.060376 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 2242 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 82 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2324 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 20 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 20 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 10 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 10 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2242 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 92 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2334 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2242 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 92 # number of overall hits +system.cpu.l2cache.overall_hits::total 2334 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2066 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 692 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 2758 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1080 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1080 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2066 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1772 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 3838 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2066 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1772 # number of overall misses +system.cpu.l2cache.overall_misses::total 3838 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 70811000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 23716000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 94527000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 37109500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 37109500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 70811000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 60825500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 131636500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 70811000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 60825500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 131636500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 4308 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 774 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 5082 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 20 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 20 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1090 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1090 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 4308 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1864 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 6172 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4308 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1864 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 6172 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.479573 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.894057 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.990826 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.479573 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.950644 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.479573 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.950644 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34274.443369 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34271.676301 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34360.648148 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34274.443369 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34325.902935 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34274.443369 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34325.902935 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -596,51 +601,57 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 12 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 12 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 12 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2005 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 662 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2667 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1082 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1082 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2005 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1744 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3749 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2005 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1744 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 3749 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 62251500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20643500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 82895000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33590000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33590000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 62251500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 54233500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 116485000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 62251500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 54233500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 116485000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.550824 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.876821 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991751 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.550824 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.944745 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.550824 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.944745 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31048.129676 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31183.534743 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31044.362292 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31048.129676 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31097.190367 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31048.129676 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31097.190367 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 17 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 20 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 17 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 20 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 17 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 20 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2063 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 675 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2738 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1080 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1080 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2063 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1755 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3818 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2063 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1755 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 3818 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 64062500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 21038500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 85101000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 31000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 31000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33524500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33524500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64062500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 54563000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 118625500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64062500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 54563000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 118625500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.478877 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.872093 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.990826 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.478877 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.941524 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.478877 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.941524 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31053.078042 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31168.148148 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31041.203704 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31053.078042 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31090.028490 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31053.078042 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31090.028490 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |