diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-11-02 11:50:06 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-11-02 11:50:06 -0500 |
| commit | 1dbf9bb4ca6cc3bee68713a28778c1bdfe222f75 (patch) | |
| tree | 81108e7ff1951b652258f53bd5615a617b734ce2 /tests/long/se/70.twolf/ref/arm | |
| parent | ddd6af414cdd4939f4ff382f0e83e7dfa695781d (diff) | |
| download | gem5-1dbf9bb4ca6cc3bee68713a28778c1bdfe222f75.tar.xz | |
update stats for preceeding changes
Diffstat (limited to 'tests/long/se/70.twolf/ref/arm')
3 files changed, 704 insertions, 677 deletions
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini index 6abd7ca4a..27e85dd46 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,18 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -159,7 +160,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -432,18 +433,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -457,6 +458,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -465,7 +483,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -473,24 +491,24 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -500,10 +518,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -540,15 +558,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout index b01ca9643..df8c6714b 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 13:57:03 +gem5 compiled Oct 30 2012 11:20:14 +gem5 started Oct 30 2012 20:48:26 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +21,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 76020082000 because target called exit() +122 123 124 Exiting @ tick 74245032000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 3d59bfc93..341764510 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.075963 # Number of seconds simulated -sim_ticks 75962996000 # Number of ticks simulated -final_tick 75962996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.074245 # Number of seconds simulated +sim_ticks 74245032000 # Number of ticks simulated +final_tick 74245032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 82470 # Simulator instruction rate (inst/s) -host_op_rate 90296 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36352186 # Simulator tick rate (ticks/s) -host_mem_usage 236740 # Number of bytes of host memory used -host_seconds 2089.64 # Real time elapsed on the host -sim_insts 172333241 # Number of instructions simulated -sim_ops 188686723 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 132736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 112192 # Number of bytes read from this memory -system.physmem.bytes_read::total 244928 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 132736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 132736 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2074 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1753 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3827 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1747377 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1476930 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3224307 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1747377 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1747377 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1747377 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1476930 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3224307 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3828 # Total number of read requests seen +host_inst_rate 109443 # Simulator instruction rate (inst/s) +host_op_rate 119829 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47150577 # Simulator tick rate (ticks/s) +host_mem_usage 234068 # Number of bytes of host memory used +host_seconds 1574.64 # Real time elapsed on the host +sim_insts 172333441 # Number of instructions simulated +sim_ops 188686923 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 131008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 111680 # Number of bytes read from this memory +system.physmem.bytes_read::total 242688 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 131008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 131008 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2047 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1745 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3792 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1764536 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1504208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3268744 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1764536 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1764536 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1764536 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1504208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3268744 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3793 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 3829 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 244928 # Total number of bytes read from memory +system.physmem.cpureqs 3795 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 242688 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 244928 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 242688 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 1 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 320 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 234 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 192 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 240 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 228 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 194 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 224 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 284 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 247 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 249 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 248 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 263 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 249 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 236 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 182 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 238 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 319 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 231 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 191 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 236 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 227 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 193 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 221 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 282 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 242 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 247 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 247 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 259 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 248 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 234 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 179 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 237 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 75962976500 # Total gap between requests +system.physmem.totGap 74245012500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 3828 # Categorize read packet sizes +system.physmem.readPktSize::6 3793 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -95,15 +95,15 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 1 # categorize neither packet sizes +system.physmem.neitherpktsize::6 2 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 2829 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 799 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 40 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2791 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 811 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 147 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 15909310 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 90413310 # Sum of mem lat for all requests -system.physmem.totBusLat 15312000 # Total cycles spent in databus access -system.physmem.totBankLat 59192000 # Total cycles spent in bank access -system.physmem.avgQLat 4156.04 # Average queueing delay per request -system.physmem.avgBankLat 15462.90 # Average bank access latency per request +system.physmem.totQLat 12366785 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 86366785 # Sum of mem lat for all requests +system.physmem.totBusLat 15172000 # Total cycles spent in databus access +system.physmem.totBankLat 58828000 # Total cycles spent in bank access +system.physmem.avgQLat 3260.42 # Average queueing delay per request +system.physmem.avgBankLat 15509.62 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23618.94 # Average memory access latency -system.physmem.avgRdBW 3.22 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 22770.05 # Average memory access latency +system.physmem.avgRdBW 3.27 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.22 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 3.27 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 3324 # Number of row buffer hits during reads +system.physmem.readRowHits 3295 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.83 # Row buffer hit rate for reads +system.physmem.readRowHitRate 86.87 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19844037.75 # Average gap between requests +system.physmem.avgGap 19574218.96 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -228,647 +228,645 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 151925993 # number of cpu cycles simulated +system.cpu.numCycles 148490065 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 96812188 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 76032236 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 6553809 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 46446152 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 44209779 # Number of BTB hits +system.cpu.BPredUnit.lookups 94824011 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 74811084 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 6283419 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 44691419 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 43068728 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 4476893 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 89558 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 40612935 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 388214882 # Number of instructions fetch has processed -system.cpu.fetch.Branches 96812188 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48686672 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 82228989 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 28431080 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7111966 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 46 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9226 # Number of stall cycles due to pending traps +system.cpu.BPredUnit.usedRAS 4355687 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 88461 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 39671704 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 380334125 # Number of instructions fetch has processed +system.cpu.fetch.Branches 94824011 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 47424415 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80393373 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 27296286 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7321256 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 4918 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 57 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 37654254 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1887415 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 151824267 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.799061 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.153208 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 51 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 36859860 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1828379 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 148388373 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.800016 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.152801 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 69765849 45.95% 45.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5500538 3.62% 49.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10700560 7.05% 56.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10437997 6.88% 63.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8786758 5.79% 69.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6834684 4.50% 73.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6296298 4.15% 77.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8361211 5.51% 83.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 25140372 16.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68164460 45.94% 45.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5263921 3.55% 49.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10532073 7.10% 56.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10289171 6.93% 63.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8658719 5.84% 69.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6556174 4.42% 73.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6250200 4.21% 77.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8011886 5.40% 83.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 24661769 16.62% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151824267 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.637233 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.555289 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 46639472 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5819765 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 76543741 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1113557 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 21707732 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14816289 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 162918 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 401266810 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 729123 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 21707732 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 52145776 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 716376 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 699385 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 72090483 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4464515 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 378976726 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 316631 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3575950 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 15 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 642441440 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1614452334 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1596874036 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 17578298 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 298092491 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 344348949 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 33473 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 33471 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12628265 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 43987484 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16888261 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5791013 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3746055 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 334831031 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 55567 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 252811108 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 890392 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 144974552 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 373956822 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 4307 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151824267 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.665156 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.759693 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 148388373 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.638588 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.561344 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45525708 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5988328 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74834240 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1196373 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 20843724 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14343881 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 164426 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 392938907 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 736414 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 20843724 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50922630 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 727420 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 699991 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 70572280 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4622328 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 371457492 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 340569 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3661423 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 29 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 631852668 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1582346867 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1565037376 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 17309491 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 298092811 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 333759857 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 32532 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 32528 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13064863 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 43027461 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16443523 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5668310 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3691413 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 329308816 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 54643 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 249531465 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 795533 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 139603170 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 362284552 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3343 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 148388373 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.681611 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.761108 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 58367016 38.44% 38.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23007793 15.15% 53.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25146514 16.56% 70.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20482198 13.49% 83.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12879503 8.48% 92.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6581643 4.34% 96.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4062886 2.68% 99.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1113562 0.73% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 183152 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56153945 37.84% 37.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 22688522 15.29% 53.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24821947 16.73% 69.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20330759 13.70% 83.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12554169 8.46% 92.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6514357 4.39% 96.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4035019 2.72% 99.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1109043 0.75% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 180612 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151824267 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 148388373 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 966665 37.55% 37.55% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5596 0.22% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 94 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 37.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 27 0.00% 37.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 37.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 37.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 37.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1198357 46.55% 84.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 403391 15.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 962652 38.43% 38.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5596 0.22% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 100 0.00% 38.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 50 0.00% 38.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1162967 46.43% 85.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 373557 14.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 197328873 78.05% 78.05% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 995382 0.39% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33194 0.01% 78.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 163810 0.06% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 255234 0.10% 78.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76440 0.03% 78.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 467356 0.18% 78.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206283 0.08% 78.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71857 0.03% 78.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 78.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 39021114 15.43% 94.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 14191245 5.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 194943196 78.12% 78.12% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 980225 0.39% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33090 0.01% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 164479 0.07% 78.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 254525 0.10% 78.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76418 0.03% 78.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 465710 0.19% 78.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206458 0.08% 79.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71854 0.03% 79.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 38372441 15.38% 94.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13962748 5.60% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 252811108 # Type of FU issued -system.cpu.iq.rate 1.664041 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2574130 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010182 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 657138452 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 477635375 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 240576408 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3772553 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2244745 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1851453 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 253490963 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1894275 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2028433 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 249531465 # Type of FU issued +system.cpu.iq.rate 1.680459 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2504922 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010039 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 647013011 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 466795184 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237947786 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3738747 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2189794 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1841578 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 250160112 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1876275 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2013222 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14131956 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 16953 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19730 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4237583 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13171893 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11381 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18785 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3792805 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 84 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 14 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 96 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 21707732 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 16237 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 835 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 334904365 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 834808 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 43987484 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16888261 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 33011 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 182 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 269 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 19730 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4101344 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3925912 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8027256 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 245818022 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 37400003 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6993086 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 20843724 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 17321 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 891 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 329380427 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 786985 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 43027461 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16443523 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 32104 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 209 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 288 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18785 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3890771 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3762289 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7653060 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 243027736 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 36864796 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6503729 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 17767 # number of nop insts executed -system.cpu.iew.exec_refs 51208402 # number of memory reference insts executed -system.cpu.iew.exec_branches 54033495 # Number of branches executed -system.cpu.iew.exec_stores 13808399 # Number of stores executed -system.cpu.iew.exec_rate 1.618012 # Inst execution rate -system.cpu.iew.wb_sent 243559168 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 242427861 # cumulative count of insts written-back -system.cpu.iew.wb_producers 150062323 # num instructions producing a value -system.cpu.iew.wb_consumers 269174598 # num instructions consuming a value +system.cpu.iew.exec_nop 16968 # number of nop insts executed +system.cpu.iew.exec_refs 50523279 # number of memory reference insts executed +system.cpu.iew.exec_branches 53444477 # Number of branches executed +system.cpu.iew.exec_stores 13658483 # Number of stores executed +system.cpu.iew.exec_rate 1.636660 # Inst execution rate +system.cpu.iew.wb_sent 240848315 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 239789364 # cumulative count of insts written-back +system.cpu.iew.wb_producers 148488630 # num instructions producing a value +system.cpu.iew.wb_consumers 267300896 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.595697 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.557491 # average fanout of values written-back +system.cpu.iew.wb_rate 1.614851 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.555511 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 146203238 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 51260 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6400494 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 130116536 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.450247 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.162155 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 140679091 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 51300 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 6130085 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 127544650 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.479492 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.184685 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59888298 46.03% 46.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 32076129 24.65% 70.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13982572 10.75% 81.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7654340 5.88% 87.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4412681 3.39% 90.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1335897 1.03% 91.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1741211 1.34% 93.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1283921 0.99% 94.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7741487 5.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 57798190 45.32% 45.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 31737959 24.88% 70.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13785979 10.81% 81.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7635406 5.99% 87.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4383857 3.44% 90.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1319533 1.03% 91.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1705049 1.34% 92.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1307627 1.03% 93.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7871050 6.17% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 130116536 # Number of insts commited each cycle -system.cpu.commit.committedInsts 172347629 # Number of instructions committed -system.cpu.commit.committedOps 188701111 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 127544650 # Number of insts commited each cycle +system.cpu.commit.committedInsts 172347829 # Number of instructions committed +system.cpu.commit.committedOps 188701311 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 42506206 # Number of memory references committed -system.cpu.commit.loads 29855528 # Number of loads committed +system.cpu.commit.refs 42506286 # Number of memory references committed +system.cpu.commit.loads 29855568 # Number of loads committed system.cpu.commit.membars 22408 # Number of memory barriers committed -system.cpu.commit.branches 40306355 # Number of branches committed +system.cpu.commit.branches 40306395 # Number of branches committed system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. -system.cpu.commit.int_insts 150130393 # Number of committed integer instructions. +system.cpu.commit.int_insts 150130553 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 7741487 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 7871050 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 457274197 # The number of ROB reads -system.cpu.rob.rob_writes 691635591 # The number of ROB writes -system.cpu.timesIdled 2582 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 101726 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 172333241 # Number of Instructions Simulated -system.cpu.committedOps 188686723 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 172333241 # Number of Instructions Simulated -system.cpu.cpi 0.881583 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.881583 # CPI: Total CPI of All Threads -system.cpu.ipc 1.134324 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.134324 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1091906245 # number of integer regfile reads -system.cpu.int_regfile_writes 388600616 # number of integer regfile writes -system.cpu.fp_regfile_reads 2911397 # number of floating regfile reads -system.cpu.fp_regfile_writes 2511024 # number of floating regfile writes -system.cpu.misc_regfile_reads 474438629 # number of misc regfile reads -system.cpu.misc_regfile_writes 832124 # number of misc regfile writes -system.cpu.icache.replacements 2644 # number of replacements -system.cpu.icache.tagsinuse 1367.286315 # Cycle average of tags in use -system.cpu.icache.total_refs 37648759 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4386 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8583.848381 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 449048801 # The number of ROB reads +system.cpu.rob.rob_writes 679713725 # The number of ROB writes +system.cpu.timesIdled 2572 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 101692 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 172333441 # Number of Instructions Simulated +system.cpu.committedOps 188686923 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 172333441 # Number of Instructions Simulated +system.cpu.cpi 0.861644 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.861644 # CPI: Total CPI of All Threads +system.cpu.ipc 1.160572 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.160572 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1079711901 # number of integer regfile reads +system.cpu.int_regfile_writes 384939818 # number of integer regfile writes +system.cpu.fp_regfile_reads 2913621 # number of floating regfile reads +system.cpu.fp_regfile_writes 2497505 # number of floating regfile writes +system.cpu.misc_regfile_reads 464692735 # number of misc regfile reads +system.cpu.misc_regfile_writes 832204 # number of misc regfile writes +system.cpu.icache.replacements 2508 # number of replacements +system.cpu.icache.tagsinuse 1347.136586 # Cycle average of tags in use +system.cpu.icache.total_refs 36854521 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4234 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 8704.421587 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1367.286315 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.667620 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.667620 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 37648759 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 37648759 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 37648759 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 37648759 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 37648759 # number of overall hits -system.cpu.icache.overall_hits::total 37648759 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5495 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5495 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5495 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5495 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5495 # number of overall misses -system.cpu.icache.overall_misses::total 5495 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 164010000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 164010000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 164010000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 164010000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 164010000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 164010000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 37654254 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 37654254 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 37654254 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 37654254 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 37654254 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 37654254 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000146 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000146 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000146 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000146 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000146 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000146 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29847.133758 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 29847.133758 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 29847.133758 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 29847.133758 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 29847.133758 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 29847.133758 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 669 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1347.136586 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.657782 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.657782 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 36854521 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 36854521 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 36854521 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 36854521 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 36854521 # number of overall hits +system.cpu.icache.overall_hits::total 36854521 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5339 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5339 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5339 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5339 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5339 # number of overall misses +system.cpu.icache.overall_misses::total 5339 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 158626499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 158626499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 158626499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 158626499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 158626499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 158626499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 36859860 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 36859860 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 36859860 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 36859860 # 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average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34107.570788 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34368.847168 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33800.926648 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34107.570788 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 57 # number of replacements -system.cpu.dcache.tagsinuse 1416.459985 # Cycle average of tags in use -system.cpu.dcache.total_refs 47307506 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1862 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 25406.823845 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 1406.445400 # Cycle average of tags in use +system.cpu.dcache.total_refs 46805125 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1854 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 25245.482740 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1416.459985 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.345815 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.345815 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 34892236 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 34892236 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12356557 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12356557 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 30260 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 30260 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 28451 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 28451 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 47248793 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 47248793 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 47248793 # number of overall hits -system.cpu.dcache.overall_hits::total 47248793 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1972 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1972 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 7730 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 7730 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 1406.445400 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.343370 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.343370 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 34390274 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 34390274 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12356568 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12356568 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 29790 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 29790 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 28491 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 28491 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 46746842 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 46746842 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 46746842 # number of overall hits +system.cpu.dcache.overall_hits::total 46746842 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1833 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1833 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 7719 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 7719 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9702 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9702 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9702 # number of overall misses -system.cpu.dcache.overall_misses::total 9702 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 89685500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 89685500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 298721497 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 298721497 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9552 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9552 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9552 # number of overall misses +system.cpu.dcache.overall_misses::total 9552 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 82596000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 82596000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 292720496 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 292720496 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 102000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 102000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 388406997 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 388406997 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 388406997 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 388406997 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 34894208 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 34894208 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 375316496 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 375316496 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 375316496 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 375316496 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 34392107 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 34392107 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 30262 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 30262 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 28451 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 28451 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 47258495 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 47258495 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 47258495 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 47258495 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000057 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000057 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000625 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000625 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000066 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000066 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000205 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000205 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000205 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000205 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45479.462475 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 45479.462475 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38644.436869 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38644.436869 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29792 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 29792 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 28491 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 28491 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46756394 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46756394 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46756394 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46756394 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000624 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000624 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000067 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000067 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000204 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000204 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000204 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000204 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45060.556465 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 45060.556465 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37922.074880 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37922.074880 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40033.704082 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40033.704082 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40033.704082 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40033.704082 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 433 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 45 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39291.927973 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39291.927973 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39291.927973 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39291.927973 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 476 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 40 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 39.363636 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 22.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 18 # number of writebacks system.cpu.dcache.writebacks::total 18 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1197 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1197 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6641 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6641 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1062 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1062 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7838 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7838 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7838 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7838 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 775 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 775 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1089 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1089 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1864 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1864 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1864 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1864 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 38083000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 38083000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 48635999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 48635999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 86718999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 86718999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 86718999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 86718999 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 7696 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7696 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7696 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7696 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 771 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 771 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1085 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1085 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1856 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1856 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1856 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1856 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36781000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36781000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 47410498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 47410498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 84191498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 84191498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 84191498 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 84191498 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000039 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000039 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49139.354839 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49139.354839 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44661.156107 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44661.156107 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46523.068133 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 46523.068133 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46523.068133 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 46523.068133 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47705.577173 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47705.577173 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43696.311521 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43696.311521 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45361.798491 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 45361.798491 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45361.798491 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 45361.798491 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 1988.724621 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2398 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2755 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.870417 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3.999610 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1449.117125 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 535.607885 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000122 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.044224 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.016345 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.060691 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 2308 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 88 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2396 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 18 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 18 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 9 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 9 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2308 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 97 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2405 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2308 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 97 # number of overall hits -system.cpu.l2cache.overall_hits::total 2405 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2079 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 685 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 2764 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 1080 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1080 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2079 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1765 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 3844 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2079 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1765 # number of overall misses -system.cpu.l2cache.overall_misses::total 3844 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 98742500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 36322000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 135064500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 47502500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 47502500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 98742500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 83824500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 182567000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 98742500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 83824500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 182567000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 4387 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 773 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 5160 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1089 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1089 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 4387 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1862 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 6249 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 4387 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1862 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 6249 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.473900 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.886158 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.535659 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.500000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.991736 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.991736 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.473900 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.947905 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.615138 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.473900 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.947905 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.615138 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47495.189995 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53024.817518 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 48865.593343 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43983.796296 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43983.796296 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47495.189995 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47492.634561 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 47494.016649 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47495.189995 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47492.634561 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 47494.016649 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 12 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 12 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 12 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2075 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 673 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2748 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1080 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1080 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2075 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1753 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3828 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2075 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1753 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 3828 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 72306456 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27405972 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 99712428 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 10001 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 10001 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33965187 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33965187 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 72306456 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 61371159 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 133677615 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 72306456 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 61371159 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 133677615 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.472988 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870634 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.532558 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991736 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991736 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.472988 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.941461 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.612578 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.472988 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.941461 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.612578 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34846.484819 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40722.098068 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36285.454148 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31449.247222 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31449.247222 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34846.484819 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35009.217912 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34921.007053 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34846.484819 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35009.217912 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34921.007053 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |