SE/FS: Make both SE and FS tests available all the time.

--HG--
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/status => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
rename : tests/long/10.linux-boot/test.py => tests/long/fs/10.linux-boot/test.py
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm
rename : tests/long/80.solaris-boot/test.py => tests/long/fs/80.solaris-boot/test.py
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simerr
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simout => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simerr
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simout => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simerr
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simout => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simerr
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/simout => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simout => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/simout => tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/00.gzip/test.py => tests/long/se/00.gzip/test.py
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/mcf.out => tests/long/se/10.mcf/ref/arm/linux/o3-timing/mcf.out
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/simerr => tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/simout => tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/simout => tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/mcf.out
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/simout => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/mcf.out => tests/long/se/10.mcf/ref/x86/linux/o3-timing/mcf.out
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simerr => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simout => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/x86/linux/simple-timing/mcf.out
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/simout => tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/10.mcf/test.py => tests/long/se/10.mcf/test.py
rename : tests/long/20.parser/ref/alpha/tru64/NOTE => tests/long/se/20.parser/ref/alpha/tru64/NOTE
rename : tests/long/20.parser/ref/arm/linux/o3-timing/config.ini => tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
rename : tests/long/20.parser/ref/arm/linux/o3-timing/simerr => tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
rename : tests/long/20.parser/ref/arm/linux/o3-timing/simout => tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
rename : tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt => tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini => tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/simerr => tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/simout => tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/20.parser/ref/arm/linux/simple-timing/config.ini => tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
rename : tests/long/20.parser/ref/arm/linux/simple-timing/simerr => tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr
rename : tests/long/20.parser/ref/arm/linux/simple-timing/simout => tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
rename : tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt => tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/20.parser/ref/x86/linux/o3-timing/config.ini => tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
rename : tests/long/20.parser/ref/x86/linux/o3-timing/simerr => tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr
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rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal
rename : tests/quick/10.linux-boot/test.py => tests/quick/fs/10.linux-boot/test.py
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal
rename : tests/quick/80.netperf-stream/test.py => tests/quick/fs/80.netperf-stream/test.py
rename : tests/quick/00.hello.mp/test.py => tests/quick/se/00.hello.mp/test.py
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/simerr => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simerr
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/simout => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
rename : tests/quick/00.hello/ref/arm/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr
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rename : tests/quick/01.hello-2T-smt/test.py => tests/quick/se/01.hello-2T-smt/test.py
rename : tests/quick/02.insttest/ref/sparc/linux/inorder-timing/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini
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rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
rename : tests/quick/02.insttest/test.py => tests/quick/se/02.insttest/test.py
rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/detailed/config.ini
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rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
rename : tests/quick/20.eio-short/test.py => tests/quick/se/20.eio-short/test.py
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
rename : tests/quick/30.eio-mp/test.py => tests/quick/se/30.eio-mp/test.py
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
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rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
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rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt
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rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
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rename : tests/quick/40.m5threads-test-atomic/test.py => tests/quick/se/40.m5threads-test-atomic/test.py
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
rename : tests/quick/50.memtest/test.py => tests/quick/se/50.memtest/test.py
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
rename : tests/quick/60.rubytest/test.py => tests/quick/se/60.rubytest/test.py

15 files changed, 2654 insertions, 0 deletions

diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
new file mode 100644
index 000000000..8db3f9119
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
@@ -0,0 +1,535 @@
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+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
new file mode 100755
index 000000000..bee9aa417
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
@@ -0,0 +1,26 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:47:07
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing
+Couldn't unlink  build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/smred.sav
+Couldn't unlink  build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/smred.sv2
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+         Yale University
+info: Increasing stack size by one page.
+  1   2   3   4   5   6   7   8   9  10  11  12  13  14  15 
+ 16  17  18  19  20  21  22  23  24  25  26  27  28  29  30 
+ 31  32  33  34  35  36  37  38  39  40  41  42  43  44  45 
+ 46  47  48  49  50  51  52  53  54  55  56  57  58  59  60 
+ 61  62  63  64  65  66  67  68  69  70  71  72  73  74  75 
+ 76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
+ 91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
+122 123 124 Exiting @ tick 105874925000 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/smred.out b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/smred.out
new file mode 100644
index 000000000..00387ae5c
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/smred.out
@@ -0,0 +1,276 @@
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+          Yale University
+
+
+NOTE: Restart file .rs2 not used
+
+TimberWolf will perform a global route step
+rowSep: 1.000000
+feedThruWidth: 4
+
+******************
+BLOCK DATA
+block:1 desire:85
+block:2 desire:85
+Total Desired Length: 170
+total cell length: 168
+total block length: 168
+block x-span:84  block y-span:78
+implicit feed thru range: -84
+Using default value of bin.penalty.control:1.000000
+numBins automatically set to:5
+binWidth = average_cell_width + 0 sigma= 17
+average_cell_width is:16
+standard deviation of cell length is:23.6305
+TimberWolfSC starting from the beginning
+
+
+
+THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
+The number of nets with 1 pin is 4
+The number of nets with 2 pin is 9
+The number of nets with 3 pin is 0
+The number of nets with 4 pin is 2
+The number of nets with 5 pin is 0
+The number of nets with 6 pin is 0
+The number of nets with 7 pin is 0
+The number of nets with 8 pin is 0
+The number of nets with 9 pin is 0
+The number of nets with 10 pin or more is 0
+
+New Cost Function: Initial Horizontal Cost:242
+New Cost Function: FEEDS:0   MISSING_ROWS:-46
+
+bdxlen:86  bdylen:78
+l:0  t:78  r:86  b:0
+
+
+
+THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
+
+
+
+THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
+
+The rand generator seed was at utemp() : 1
+
+
+  tempfile[0][0] = 0.982500    tempfile[0][1] = 90.000000
+  tempfile[1][0] = 0.915000    tempfile[1][1] = 20.000000
+  tempfile[2][0] = 0.700000    tempfile[2][1] = 10.000000
+  tempfile[3][0] = 0.100000    tempfile[3][1] = 0.000000
+
+  I   T  fds     Wire Penalty P_lim Epct binC rowC  acc  s/p early  FDs    MRs
+  1 500    0      929     592   160 30.0  1.0  3.0 84.2 34.7  0.0     0     40
+  2 491    0      876     106   726  0.0  0.8  2.5 80.0 18.5  0.0     0     46
+  3 482    0      822     273   372  0.0  0.5  1.5 80.8 21.2  0.0     0     46
+  4 474    0      826      53   247  0.0  0.5  0.9 65.0 21.9  0.0     0     48
+  5 465    8      987      73   190  0.0  0.5  0.5 50.0 38.3  0.0     0     46
+  6 457    8      851      67   226  0.0  0.5  0.5 53.8 42.9  0.0     0     52
+  7 449    8     1067     108   190  0.0  0.5  0.5 46.2 53.8  0.0     0     50
+  8 441    8      918     106   171  0.0  0.5  0.5 47.1 40.4  0.0     0     48
+  9 434    8      812     101   197  0.0  0.5  0.5 53.6 21.0  0.0     0     48
+ 10 426    8     1038     121   181  0.0  0.5  0.5 43.6 27.1  0.0     0     48
+ 11 419    8      898      93   187  0.0  0.5  0.5 45.3 47.8  0.0     0     50
+ 12 411    4      857      94   240  0.0  0.5  0.5 62.7 51.6  0.0     0     44
+ 13 404    8     1043      88   185  0.0  0.5  0.5 54.0 52.8  0.0     0     50
+ 14 397    8      767      94   154  0.0  0.5  0.5 33.8 35.0  0.0     0     50
+ 15 390    8      862      89   183  0.0  0.5  0.5 55.6 29.0  0.0     0     46
+ 16 383    4      798      79   173  0.0  0.5  0.5 57.5 35.3  0.0     0     52
+ 17 376    8      827     100   152  0.0  0.5  0.5 35.3 81.8  0.0     0     50
+ 18 370    8      878     101   208  0.0  0.5  0.5 44.7 46.2  0.0     0     48
+ 19 363    4      921      67   167  0.0  0.5  0.5 57.1 34.7  0.0     0     48
+ 20 357    8      933      93   154  0.0  0.5  0.5 46.5 43.6  0.0     0     52
+ 21 351    8      930      89   147  0.0  0.5  0.5 39.4 36.5  0.0     0     52
+ 22 345    8      951      79   142  0.0  0.5  0.5 32.8 51.3  0.0     0     50
+ 23 339    8     1046      87   207  0.0  0.5  0.5 52.8 61.0  0.0     0     48
+ 24 333    4      989      96   185  0.0  0.5  0.5 45.3 43.3  0.0     0     42
+ 25 327    4      577      86   157  0.0  0.5  0.5 31.1 55.3  0.0     0     52
+ 26 321    8      776      97   174  0.0  0.5  0.5 47.9 62.5  0.0     0     52
+ 27 315    8      850      81   188  0.0  0.5  0.5 45.0 55.2  0.0     0     50
+ 28 310    8      898      97   148  0.0  0.5  0.5 43.0 45.8  0.0     0     48
+ 29 304    8      889      65   173  0.0  0.5  0.5 32.5 41.3  0.0     0     50
+ 30 299    8      858      81   153  0.0  0.5  0.5 44.3 29.2  0.0     0     46
+ 31 294    8      871      82   187  0.0  0.5  0.5 45.7 47.7  0.0     0     48
+ 32 289    8      782     109   173  0.0  0.5  0.5 35.2 57.4  0.0     0     48
+ 33 284    8      743      98   189  0.0  0.6  0.5 41.8 64.3  0.0     0     52
+ 34 279    8      943      90   147  0.0  0.5  0.5 38.6 32.8  0.0     0     48
+ 35 274    8      907      57   166  0.0  0.5  0.5 33.6 51.0  0.0     0     48
+ 36 269    8      900      70   148  0.0  0.5  0.5 45.0 41.4  0.0     0     50
+ 37 264    4      875     106   133  0.0  0.5  0.5 31.7 55.3  0.0     0     52
+ 38 260    8     1023     145   149  0.0  0.6  0.5 28.7 65.0  0.0     0     52
+ 39 255    8      801     151   173  0.0  0.9  0.5 41.7 41.2  0.0     0     48
+ 40 251    8      741     104   159  0.0  0.8  0.5 36.2 47.5  0.0     0     48
+ 41 246    8      828     108   149  0.0  0.5  0.5 34.6 50.9  0.0     0     50
+ 42 242    8      947     128   132  0.0  0.7  0.5 34.2 39.0  0.0     0     50
+ 43 238    8      917     101   142  0.0  0.8  0.5 34.4 50.9  0.0     0     48
+ 44 234    8      761      86   129  0.0  0.5  0.5 42.0 36.4  0.0     0     52
+ 45 229    8      979     106   137  0.0  0.5  0.5 29.2 55.3  0.0     0     50
+ 46 225    8      806      74   130  0.0  0.7  0.5 33.1 65.4  0.0     0     52
+ 47 221    8      971     125   114  0.0  0.5  0.5 31.9 45.6  0.0     0     52
+ 48 218    8      869     125   104  0.0  0.9  0.5 30.0 56.0  0.0     0     48
+ 49 214    8      999     153   140  0.0  0.8  0.5 30.4 46.4  0.0     0     52
+ 50 210    8      798     192   139  0.0  1.0  0.5 28.9 50.0  0.0     0     52
+ 51 206    8      860     125   157  0.0  1.2  0.5 31.5 26.9  0.0     0     52
+ 52 203    8      893     186   127  5.9  0.9  0.5 26.4 42.3  0.0     0     46
+ 53 199    8      863     126   141  0.0  1.2  0.5 32.5 44.4  0.0     0     44
+ 54 196    8      788      97   133  0.0  0.9  0.5 37.5 40.0  0.0     0     50
+ 55 192    8      926     119   116  0.0  0.6  0.5 26.1 55.3  0.0     0     52
+ 56 189    8      789     162   107  0.0  0.8  0.5 25.2 40.4  0.0     0     48
+ 57 186    8      878     107   128  0.0  1.1  0.5 23.1 34.0  0.0     0     52
+ 58 182    8      775     105   122  0.0  0.8  0.5 25.5 57.4  0.0     0     50
+ 59 179    8      747      94   129  0.0  0.7  0.5 34.3 37.3  0.0     0     50
+ 60 176    8      845      96   138  0.0  0.6  0.5 28.3 41.7  0.0     0     52
+ 61 173    8      961     121   110  0.0  0.6  0.5 29.0 52.6  0.0     0     48
+ 62 170    4      911     110   109  0.0  0.9  0.5 33.5 33.3  0.0     0     48
+ 63 167    8      656     109   109  0.0  0.8  0.5 21.9 44.7  0.0     0     52
+ 64 164    8      934     117   105  0.0  0.8  0.5 15.5 50.0  0.0     0     52
+ 65 161    8      972     125    95  0.0  0.8  0.5 24.4 50.0  0.0     0     50
+ 66 158    8      894     125   101  0.0  0.9  0.5 27.2 35.9  0.0     0     52
+ 67 155    8      798     146   129  0.0  1.0  0.5 22.8 58.7  0.0     0     52
+ 68 153    8      901     183    92  0.0  1.1  0.5 23.6 34.5  0.0     0     52
+ 69 150    8      977     197   103  0.0  1.4  0.5 23.6 36.8  0.0     0     52
+ 70 147    8      905     262    93  0.0  1.5  0.5 20.3 63.4  0.0     0     52
+ 71 145    8      995     148   122  0.0  1.9  0.5 20.9 35.3  0.0     0     52
+ 72 142    8      934     230    99  0.0  1.6  0.5 20.0 65.9  0.0     0     52
+ 73 140    8      862     173   100  0.0  1.8  0.5 26.8 46.8  0.0     0     52
+ 74 137    8      924     139    90  0.0  1.7  0.5 16.8 42.5  0.0     0     52
+ 75 135    8      888     168   113  0.0  1.6  0.5 22.9 40.4  0.0     0     52
+ 76 133    8      712     212    84  0.0  1.6  0.5 13.4 46.9  0.0     0     52
+ 77 130    8      868     210    91  0.0  1.7  0.5 17.7 51.2  0.0     0     52
+ 78 128    8      952     307    92  0.0  1.9  0.5 19.7 44.9  0.0     0     50
+ 79 126    8      801     157   107  0.0  2.2  0.5 15.8 39.0  0.0     0     52
+ 80 123    8      849     147    93  0.0  2.1  0.5 15.6 51.4  0.0     0     52
+ 81 121    8      799     154    86  0.0  1.9  0.5 12.2 50.0  0.0     0     52
+ 82 119    8      941     213    82  0.0  1.8  0.5 19.5 41.2  0.0     0     50
+ 83 117    8      751     268    94  0.0  2.0  0.5 20.8 42.6  0.0     0     50
+ 84 115    8      828     198   102  0.0  2.2  0.5 15.5 59.5  0.0     0     52
+ 85 113    8      898     266   123  0.0  2.2  0.5 13.2 85.2  0.0     0     52
+ 86 111    8      943     190    93  0.0  2.4  0.5 19.5 45.1  0.0     0     52
+ 87 109    8      864     183    65  0.0  2.4  0.5 14.9 31.8  0.0     0     52
+ 88 107    8      793     203    93  0.0  2.4  0.5 11.8 35.3  0.0     0     52
+ 89 105    8      752     162    74  1.2  2.4  0.5 13.1 21.4  0.0     0     52
+ 90 103    8      801     149    77  0.0  2.3  0.5  9.7 58.3  0.0     0     52
+ 91 102    8      901     230    99  0.0  2.2  0.5 16.0 25.5  0.0     0     52
+ 92 100    8      826     201    87  0.0  2.4  0.5 12.8 45.7  0.0     0     52
+ 93  98    8      810     196    83  0.0  2.5  0.5 14.0 24.4  0.0     0     52
+ 94  96    8      857     209    68  1.0  2.5  0.5 11.5 27.0  5.1     0     52
+ 95  95    8      771     174    91  0.0  2.6  0.5 10.5 26.5  0.0     0     52
+ 96  93    8      955     210    59  0.0  2.6  0.5 10.0 36.7  0.7     0     52
+ 97  91    8      833     206    53  0.0  2.7  0.5 10.2 19.4  1.4     0     52
+ 98  90    8      888     229    86  0.0  2.8  0.5  8.1 36.0  0.0     0     52
+ 99  88    8      794     186    91  1.0  2.9  0.5  8.3 25.0  0.5     0     52
+100  81    8      756     170    72  1.0  2.9  0.5  6.0 23.8  7.0     0     52
+101  74    8      791     176    67  0.0  2.9  0.5  4.4 58.3  4.0     0     52
+102  67    8      813     213    43  0.0  3.0  0.5  7.0 150.0  4.2     0     52
+103  62    8      779     245    39  0.0  3.1  0.5  3.2 16.7 13.0     0     52
+104  56    8      767     303    63  0.0  3.2  0.5  4.1 20.0  0.7     0     52
+105  52    8      757     270    57  0.0  3.5  0.5  6.4  3.7  0.5     0     52
+106  47    8      763     283    41  0.0  3.7  0.5  4.5  0.0  0.0     0     52
+107  43    8      768     283    36  0.0  3.7  0.5  2.9 18.2  3.6     0     52
+108  39    8      804     283    25  0.0  3.7  0.5  3.1  0.0  6.2     0     52
+109  36    8      781     283    24  0.0  3.7  0.5  3.6  6.7  6.7     0     52
+110  33    8      738     298    42  0.0  3.7  0.5  3.3 15.4  3.5     0     52
+111  30    8      761     298    36  0.0  3.7  0.5  2.2  0.0  4.3     0     52
+112  27    8      769     298    37  0.0  3.7  0.5  0.9  0.0  2.2     0     52
+113  25    8      745     298    31  0.0  3.7  0.5  1.5  0.0  6.6     0     52
+114  23    8      753     298    16  0.0  3.7  0.5  1.3  0.0  2.8     0     52
+115  21    8      745     298    11  0.0  3.7  0.5  1.5  0.0 14.0     0     52
+116  19    8      747     298    21  0.0  3.7  0.5  2.1  0.0  5.8     0     52
+117  13    8      737     298    12  0.0  3.7  0.5  1.0  0.0 10.0     0     52
+118   9    8      736     298     4  0.0  3.7  0.5  1.5  0.0 18.5     0     52
+119   0    8      739     298     0  0.0  3.7  0.5  1.8  0.0 18.0     0     52
+120   0    8      732     298     0  0.0  3.7  0.5  1.2  0.0 21.8     0     52
+121   0    8      732      19    -1 0.0  0.0  0.5  0.0 100.0 54.8
+
+Initial Wiring Cost: 645   Final Wiring Cost: 732
+############## Percent Wire Cost Reduction: -13
+
+
+Initial Wire Length: 645   Final Wire Length: 732
+************** Percent Wire Length Reduction: -13
+
+
+Initial Horiz. Wire: 216   Final Horiz. Wire: 147
+$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
+
+
+Initial Vert. Wire: 429   Final Vert. Wire: 585
+@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
+
+Before Feeds are Added:
+BLOCK      TOTAL CELL LENGTHS      OVER/UNDER TARGET
+  1                 82                   -20
+  2                 86                   -16
+
+LONGEST Block is:2   Its length is:86
+BLOCK      TOTAL CELL LENGTHS      OVER/UNDER TARGET
+  1                 86                   -16
+  2                 86                   -16
+
+LONGEST Block is:1   Its length is:86
+Added: 1  feed-through cells
+
+Removed the cell overlaps --- Will do neighbor interchanges only now
+
+TOTAL INTERCONNECT LENGTH: 994
+OVERLAP PENALTY: 0
+
+initialRowControl:   1.650
+finalRowControl:   0.300
+iter      T      Wire accept
+ 122  0.001       976   16%
+ 123  0.001       971    0%
+ 124  0.001       971    0%
+Total Feed-Alignment Movement (Pass 1): 0
+Total Feed-Alignment Movement (Pass 2): 0
+Total Feed-Alignment Movement (Pass 3): 0
+Total Feed-Alignment Movement (Pass 4): 0
+Total Feed-Alignment Movement (Pass 5): 0
+Total Feed-Alignment Movement (Pass 6): 0
+Total Feed-Alignment Movement (Pass 7): 0
+Total Feed-Alignment Movement (Pass 8): 0
+
+The rand generator seed was at globroute() : 987654321
+
+
+Total Number of Net Segments: 9
+Number of Switchable Net Segments: 0
+
+Number of channels: 3
+
+
+
+THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
+
+
+no. of accepted flips: 0
+no. of attempted flips: 0
+THIS IS THE NUMBER OF TRACKS: 5
+
+
+
+FINAL NUMBER OF ROUTING TRACKS: 5
+
+MAX OF CHANNEL:  1  is:   0
+MAX OF CHANNEL:  2  is:   4
+MAX OF CHANNEL:  3  is:   1
+FINAL TOTAL INTERCONNECT LENGTH: 978
+FINAL OVERLAP PENALTY: 0    FINAL VALUE OF TOTAL COST IS: 978
+MAX NUMBER OF ATTEMPTED FLIPS PER T:      55
+
+
+cost_scale_factor:3.90616
+
+Number of Feed Thrus: 0
+Number of Implicit Feed Thrus: 0
+
+Statistics:
+Number of Standard Cells: 10
+Number of Pads: 0 
+Number of Nets: 15 
+Number of Pins: 46 
+Usage statistics not available
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
new file mode 100644
index 000000000..4282a0231
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
@@ -0,0 +1,534 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.105875                       # Number of seconds simulated
+sim_ticks                                105874925000                       # Number of ticks simulated
+final_tick                               105874925000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 103612                       # Simulator instruction rate (inst/s)
+host_tick_rate                               58144234                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 224188                       # Number of bytes of host memory used
+host_seconds                                  1820.90                       # Real time elapsed on the host
+sim_insts                                   188667572                       # Number of instructions simulated
+system.physmem.bytes_read                      240192                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 128512                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                         3753                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                        2268639                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                   1213810                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                       2268639                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                  400                       # Number of system calls
+system.cpu.numCycles                        211749851                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.BPredUnit.lookups                102127285                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           80698368                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            9933568                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              84243150                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 79257318                       # Number of BTB hits
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.usedRAS                  4698618                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect              111511                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           44551125                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      416786863                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   102127285                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           83955936                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     108810185                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                33218375                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               35074253                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                    9                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           251                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles            1                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.CacheLines                  40624886                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               2204416                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          211691341                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.135529                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.646861                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                103083318     48.70%     48.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  4611723      2.18%     50.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 32955553     15.57%     66.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 18242297      8.62%     75.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  9176940      4.34%     79.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 12529739      5.92%     85.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  8472403      4.00%     89.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  4322449      2.04%     91.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 18296919      8.64%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total            211691341                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.482302                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.968298                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 53244805                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              33622636                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 100506105                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1219607                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               23098188                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             14186059                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                166456                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              422686981                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                695509                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               23098188                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 62205667                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                  461892                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       28663713                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  92688664                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               4573217                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              388586256                       # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents                  22473                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               2248529                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands           666261253                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1656600047                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1638859233                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          17740814                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             298061848                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                368199405                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            2723713                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        2675909                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  23519864                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             46897665                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            16902365                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           3883401                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2525721                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  332696460                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2225712                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 261853052                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            956132                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       143515224                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    342118821                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         589705                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     211691341                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.236957                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.489139                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            97854722     46.23%     46.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            37874169     17.89%     64.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            34110087     16.11%     80.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            22786114     10.76%     90.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            11453676      5.41%     96.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             4761165      2.25%     98.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             2318956      1.10%     99.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              393514      0.19%     99.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              138938      0.07%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       211691341                       # Number of insts issued each cycle
+system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  398184     18.25%     18.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                   5522      0.25%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     18.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                54      0.00%     18.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     18.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     18.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     18.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     18.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc               48      0.00%     18.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     18.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     18.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     18.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1324595     60.71%     79.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                453293     20.78%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             204944335     78.27%     78.27% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               928862      0.35%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     78.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd           33072      0.01%     78.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     78.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp          166569      0.06%     78.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt          257495      0.10%     78.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv           76397      0.03%     78.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc         468208      0.18%     79.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult         207568      0.08%     79.08% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc        71821      0.03%     79.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt            325      0.00%     79.11% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             40739224     15.56%     94.67% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            13959176      5.33%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::total              261853052                       # Type of FU issued
+system.cpu.iq.rate                           1.236615                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2181696                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.008332                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          734785745                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         476212492                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    242882419                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             3749528                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            2237188                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      1845400                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              262148601                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 1886147                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1588917                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread0.squashedLoads     17045968                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        31330                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        12732                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      4255519                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread0.rescheduledLoads           19                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked             1                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewSquashCycles               23098188                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                   13857                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                   833                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           334975630                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           3751995                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              46897665                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             16902365                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            2201836                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                    328                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                   255                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          12732                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        9997150                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      1695546                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             11692696                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             249230612                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              38607191                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          12622440                       # Number of squashed instructions skipped in execute
+system.cpu.iew.exec_swp                             0                       # number of swp insts executed
+system.cpu.iew.exec_nop                         53458                       # number of nop insts executed
+system.cpu.iew.exec_refs                     52205543                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 52589382                       # Number of branches executed
+system.cpu.iew.exec_stores                   13598352                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.177005                       # Inst execution rate
+system.cpu.iew.wb_sent                      246260336                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     244727819                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 148531018                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 247826872                       # num instructions consuming a value
+system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.wb_rate                       1.155740                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.599334                       # average fanout of values written-back
+system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.commit.commitCommittedInsts      188681960                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts       146293697                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1636007                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           9795278                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    188593154                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.000471                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.681076                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    105401505     55.89%     55.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     40855723     21.66%     77.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     19482895     10.33%     87.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      8763575      4.65%     92.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      4920568      2.61%     95.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      2013461      1.07%     96.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1707502      0.91%     97.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1008267      0.53%     97.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      4439658      2.35%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    188593154                       # Number of insts commited each cycle
+system.cpu.commit.count                     188681960                       # Number of instructions committed
+system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
+system.cpu.commit.refs                       42498543                       # Number of memory references committed
+system.cpu.commit.loads                      29851697                       # Number of loads committed
+system.cpu.commit.membars                       22408                       # Number of memory barriers committed
+system.cpu.commit.branches                   40283895                       # Number of branches committed
+system.cpu.commit.fp_insts                    1752310                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                 150115073                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              1848934                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events               4439658                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
+system.cpu.rob.rob_reads                    519123952                       # The number of ROB reads
+system.cpu.rob.rob_writes                   693113124                       # The number of ROB writes
+system.cpu.timesIdled                            1721                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           58510                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   188667572                       # Number of Instructions Simulated
+system.cpu.committedInsts_total             188667572                       # Number of Instructions Simulated
+system.cpu.cpi                               1.122344                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.122344                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.890993                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.890993                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1112090730                       # number of integer regfile reads
+system.cpu.int_regfile_writes               407417013                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   2928432                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  2499453                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               503028333                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 824460                       # number of misc regfile writes
+system.cpu.icache.replacements                   1929                       # number of replacements
+system.cpu.icache.tagsinuse               1329.893683                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 40620654                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   3638                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               11165.655305                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1329.893683                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.649362                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits               40620654                       # number of ReadReq hits
+system.cpu.icache.demand_hits                40620654                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits               40620654                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 4232                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  4232                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 4232                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      101343500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       101343500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      101343500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses           40624886                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses            40624886                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses           40624886                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000104                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000104                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000104                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 23946.951796                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 23946.951796                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 23946.951796                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits               594                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits                594                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits               594                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses            3638                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses             3638                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses            3638                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency     74666000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency     74666000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency     74666000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000090                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000090                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000090                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 20523.914239                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 20523.914239                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 20523.914239                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                     55                       # number of replacements
+system.cpu.dcache.tagsinuse               1403.749083                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 48644661                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                   1849                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs               26308.632234                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           1403.749083                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.342712                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               36235521                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              12356728                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits            27793                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits             24619                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits                48592249                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               48592249                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                 1802                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses                7559                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses              2                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses                  9361                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                 9361                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency       59198500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency     237194000                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency        63500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency       296392500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency      296392500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           36237323                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          12364287                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses        27795                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses         24619                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses            48601610                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           48601610                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.000050                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.000611                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate     0.000072                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate           0.000193                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.000193                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 32851.553829                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 31379.018389                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency        31750                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 31662.482641                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 31662.482641                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        20000                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets        20000                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                       19                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits              1044                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits             6468                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits            2                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits               7512                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits              7512                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses             758                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses           1091                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses             1849                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses            1849                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency     24153000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency     38344000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency     62497000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency     62497000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.000021                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000088                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.000038                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.000038                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31864.116095                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35145.737855                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 33800.432666                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 33800.432666                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                     0                       # number of replacements
+system.cpu.l2cache.tagsinuse              1924.111202                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                    1711                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  2681                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.638195                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          1920.073953                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1             4.037248                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.058596                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.000123                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                  1711                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits                  19                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits                   9                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                   1720                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                  1720                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses                2685                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses              1082                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                 3767                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses                3767                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency      92055500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency     37184500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency      129240000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency     129240000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses              4396                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses              19                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses            1091                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses               5487                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses              5487                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.610783                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.991751                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.686532                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.686532                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency 34285.102421                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34366.451017                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34308.468277                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34308.468277                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                       0                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits               14                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits                14                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits               14                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses           2671                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses         1082                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses            3753                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses           3753                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency     83018000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency     33590000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency    116608000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency    116608000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.607598                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.991751                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.683980                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.683980                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.242980                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31044.362292                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31070.610179                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31070.610179                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
new file mode 100644
index 000000000..01def30a3
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
@@ -0,0 +1,102 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb itb tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu.tracer
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simerr b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout
new file mode 100755
index 000000000..f2a9f0661
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout
@@ -0,0 +1,26 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:50:48
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic
+Couldn't unlink  build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic/smred.sav
+Couldn't unlink  build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic/smred.sv2
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+         Yale University
+info: Increasing stack size by one page.
+  1   2   3   4   5   6   7   8   9  10  11  12  13  14  15 
+ 16  17  18  19  20  21  22  23  24  25  26  27  28  29  30 
+ 31  32  33  34  35  36  37  38  39  40  41  42  43  44  45 
+ 46  47  48  49  50  51  52  53  54  55  56  57  58  59  60 
+ 61  62  63  64  65  66  67  68  69  70  71  72  73  74  75 
+ 76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
+ 91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
+122 123 124 Exiting @ tick 103106771000 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/smred.out b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/smred.out
new file mode 100644
index 000000000..00387ae5c
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/smred.out
@@ -0,0 +1,276 @@
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+          Yale University
+
+
+NOTE: Restart file .rs2 not used
+
+TimberWolf will perform a global route step
+rowSep: 1.000000
+feedThruWidth: 4
+
+******************
+BLOCK DATA
+block:1 desire:85
+block:2 desire:85
+Total Desired Length: 170
+total cell length: 168
+total block length: 168
+block x-span:84  block y-span:78
+implicit feed thru range: -84
+Using default value of bin.penalty.control:1.000000
+numBins automatically set to:5
+binWidth = average_cell_width + 0 sigma= 17
+average_cell_width is:16
+standard deviation of cell length is:23.6305
+TimberWolfSC starting from the beginning
+
+
+
+THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
+The number of nets with 1 pin is 4
+The number of nets with 2 pin is 9
+The number of nets with 3 pin is 0
+The number of nets with 4 pin is 2
+The number of nets with 5 pin is 0
+The number of nets with 6 pin is 0
+The number of nets with 7 pin is 0
+The number of nets with 8 pin is 0
+The number of nets with 9 pin is 0
+The number of nets with 10 pin or more is 0
+
+New Cost Function: Initial Horizontal Cost:242
+New Cost Function: FEEDS:0   MISSING_ROWS:-46
+
+bdxlen:86  bdylen:78
+l:0  t:78  r:86  b:0
+
+
+
+THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
+
+
+
+THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
+
+The rand generator seed was at utemp() : 1
+
+
+  tempfile[0][0] = 0.982500    tempfile[0][1] = 90.000000
+  tempfile[1][0] = 0.915000    tempfile[1][1] = 20.000000
+  tempfile[2][0] = 0.700000    tempfile[2][1] = 10.000000
+  tempfile[3][0] = 0.100000    tempfile[3][1] = 0.000000
+
+  I   T  fds     Wire Penalty P_lim Epct binC rowC  acc  s/p early  FDs    MRs
+  1 500    0      929     592   160 30.0  1.0  3.0 84.2 34.7  0.0     0     40
+  2 491    0      876     106   726  0.0  0.8  2.5 80.0 18.5  0.0     0     46
+  3 482    0      822     273   372  0.0  0.5  1.5 80.8 21.2  0.0     0     46
+  4 474    0      826      53   247  0.0  0.5  0.9 65.0 21.9  0.0     0     48
+  5 465    8      987      73   190  0.0  0.5  0.5 50.0 38.3  0.0     0     46
+  6 457    8      851      67   226  0.0  0.5  0.5 53.8 42.9  0.0     0     52
+  7 449    8     1067     108   190  0.0  0.5  0.5 46.2 53.8  0.0     0     50
+  8 441    8      918     106   171  0.0  0.5  0.5 47.1 40.4  0.0     0     48
+  9 434    8      812     101   197  0.0  0.5  0.5 53.6 21.0  0.0     0     48
+ 10 426    8     1038     121   181  0.0  0.5  0.5 43.6 27.1  0.0     0     48
+ 11 419    8      898      93   187  0.0  0.5  0.5 45.3 47.8  0.0     0     50
+ 12 411    4      857      94   240  0.0  0.5  0.5 62.7 51.6  0.0     0     44
+ 13 404    8     1043      88   185  0.0  0.5  0.5 54.0 52.8  0.0     0     50
+ 14 397    8      767      94   154  0.0  0.5  0.5 33.8 35.0  0.0     0     50
+ 15 390    8      862      89   183  0.0  0.5  0.5 55.6 29.0  0.0     0     46
+ 16 383    4      798      79   173  0.0  0.5  0.5 57.5 35.3  0.0     0     52
+ 17 376    8      827     100   152  0.0  0.5  0.5 35.3 81.8  0.0     0     50
+ 18 370    8      878     101   208  0.0  0.5  0.5 44.7 46.2  0.0     0     48
+ 19 363    4      921      67   167  0.0  0.5  0.5 57.1 34.7  0.0     0     48
+ 20 357    8      933      93   154  0.0  0.5  0.5 46.5 43.6  0.0     0     52
+ 21 351    8      930      89   147  0.0  0.5  0.5 39.4 36.5  0.0     0     52
+ 22 345    8      951      79   142  0.0  0.5  0.5 32.8 51.3  0.0     0     50
+ 23 339    8     1046      87   207  0.0  0.5  0.5 52.8 61.0  0.0     0     48
+ 24 333    4      989      96   185  0.0  0.5  0.5 45.3 43.3  0.0     0     42
+ 25 327    4      577      86   157  0.0  0.5  0.5 31.1 55.3  0.0     0     52
+ 26 321    8      776      97   174  0.0  0.5  0.5 47.9 62.5  0.0     0     52
+ 27 315    8      850      81   188  0.0  0.5  0.5 45.0 55.2  0.0     0     50
+ 28 310    8      898      97   148  0.0  0.5  0.5 43.0 45.8  0.0     0     48
+ 29 304    8      889      65   173  0.0  0.5  0.5 32.5 41.3  0.0     0     50
+ 30 299    8      858      81   153  0.0  0.5  0.5 44.3 29.2  0.0     0     46
+ 31 294    8      871      82   187  0.0  0.5  0.5 45.7 47.7  0.0     0     48
+ 32 289    8      782     109   173  0.0  0.5  0.5 35.2 57.4  0.0     0     48
+ 33 284    8      743      98   189  0.0  0.6  0.5 41.8 64.3  0.0     0     52
+ 34 279    8      943      90   147  0.0  0.5  0.5 38.6 32.8  0.0     0     48
+ 35 274    8      907      57   166  0.0  0.5  0.5 33.6 51.0  0.0     0     48
+ 36 269    8      900      70   148  0.0  0.5  0.5 45.0 41.4  0.0     0     50
+ 37 264    4      875     106   133  0.0  0.5  0.5 31.7 55.3  0.0     0     52
+ 38 260    8     1023     145   149  0.0  0.6  0.5 28.7 65.0  0.0     0     52
+ 39 255    8      801     151   173  0.0  0.9  0.5 41.7 41.2  0.0     0     48
+ 40 251    8      741     104   159  0.0  0.8  0.5 36.2 47.5  0.0     0     48
+ 41 246    8      828     108   149  0.0  0.5  0.5 34.6 50.9  0.0     0     50
+ 42 242    8      947     128   132  0.0  0.7  0.5 34.2 39.0  0.0     0     50
+ 43 238    8      917     101   142  0.0  0.8  0.5 34.4 50.9  0.0     0     48
+ 44 234    8      761      86   129  0.0  0.5  0.5 42.0 36.4  0.0     0     52
+ 45 229    8      979     106   137  0.0  0.5  0.5 29.2 55.3  0.0     0     50
+ 46 225    8      806      74   130  0.0  0.7  0.5 33.1 65.4  0.0     0     52
+ 47 221    8      971     125   114  0.0  0.5  0.5 31.9 45.6  0.0     0     52
+ 48 218    8      869     125   104  0.0  0.9  0.5 30.0 56.0  0.0     0     48
+ 49 214    8      999     153   140  0.0  0.8  0.5 30.4 46.4  0.0     0     52
+ 50 210    8      798     192   139  0.0  1.0  0.5 28.9 50.0  0.0     0     52
+ 51 206    8      860     125   157  0.0  1.2  0.5 31.5 26.9  0.0     0     52
+ 52 203    8      893     186   127  5.9  0.9  0.5 26.4 42.3  0.0     0     46
+ 53 199    8      863     126   141  0.0  1.2  0.5 32.5 44.4  0.0     0     44
+ 54 196    8      788      97   133  0.0  0.9  0.5 37.5 40.0  0.0     0     50
+ 55 192    8      926     119   116  0.0  0.6  0.5 26.1 55.3  0.0     0     52
+ 56 189    8      789     162   107  0.0  0.8  0.5 25.2 40.4  0.0     0     48
+ 57 186    8      878     107   128  0.0  1.1  0.5 23.1 34.0  0.0     0     52
+ 58 182    8      775     105   122  0.0  0.8  0.5 25.5 57.4  0.0     0     50
+ 59 179    8      747      94   129  0.0  0.7  0.5 34.3 37.3  0.0     0     50
+ 60 176    8      845      96   138  0.0  0.6  0.5 28.3 41.7  0.0     0     52
+ 61 173    8      961     121   110  0.0  0.6  0.5 29.0 52.6  0.0     0     48
+ 62 170    4      911     110   109  0.0  0.9  0.5 33.5 33.3  0.0     0     48
+ 63 167    8      656     109   109  0.0  0.8  0.5 21.9 44.7  0.0     0     52
+ 64 164    8      934     117   105  0.0  0.8  0.5 15.5 50.0  0.0     0     52
+ 65 161    8      972     125    95  0.0  0.8  0.5 24.4 50.0  0.0     0     50
+ 66 158    8      894     125   101  0.0  0.9  0.5 27.2 35.9  0.0     0     52
+ 67 155    8      798     146   129  0.0  1.0  0.5 22.8 58.7  0.0     0     52
+ 68 153    8      901     183    92  0.0  1.1  0.5 23.6 34.5  0.0     0     52
+ 69 150    8      977     197   103  0.0  1.4  0.5 23.6 36.8  0.0     0     52
+ 70 147    8      905     262    93  0.0  1.5  0.5 20.3 63.4  0.0     0     52
+ 71 145    8      995     148   122  0.0  1.9  0.5 20.9 35.3  0.0     0     52
+ 72 142    8      934     230    99  0.0  1.6  0.5 20.0 65.9  0.0     0     52
+ 73 140    8      862     173   100  0.0  1.8  0.5 26.8 46.8  0.0     0     52
+ 74 137    8      924     139    90  0.0  1.7  0.5 16.8 42.5  0.0     0     52
+ 75 135    8      888     168   113  0.0  1.6  0.5 22.9 40.4  0.0     0     52
+ 76 133    8      712     212    84  0.0  1.6  0.5 13.4 46.9  0.0     0     52
+ 77 130    8      868     210    91  0.0  1.7  0.5 17.7 51.2  0.0     0     52
+ 78 128    8      952     307    92  0.0  1.9  0.5 19.7 44.9  0.0     0     50
+ 79 126    8      801     157   107  0.0  2.2  0.5 15.8 39.0  0.0     0     52
+ 80 123    8      849     147    93  0.0  2.1  0.5 15.6 51.4  0.0     0     52
+ 81 121    8      799     154    86  0.0  1.9  0.5 12.2 50.0  0.0     0     52
+ 82 119    8      941     213    82  0.0  1.8  0.5 19.5 41.2  0.0     0     50
+ 83 117    8      751     268    94  0.0  2.0  0.5 20.8 42.6  0.0     0     50
+ 84 115    8      828     198   102  0.0  2.2  0.5 15.5 59.5  0.0     0     52
+ 85 113    8      898     266   123  0.0  2.2  0.5 13.2 85.2  0.0     0     52
+ 86 111    8      943     190    93  0.0  2.4  0.5 19.5 45.1  0.0     0     52
+ 87 109    8      864     183    65  0.0  2.4  0.5 14.9 31.8  0.0     0     52
+ 88 107    8      793     203    93  0.0  2.4  0.5 11.8 35.3  0.0     0     52
+ 89 105    8      752     162    74  1.2  2.4  0.5 13.1 21.4  0.0     0     52
+ 90 103    8      801     149    77  0.0  2.3  0.5  9.7 58.3  0.0     0     52
+ 91 102    8      901     230    99  0.0  2.2  0.5 16.0 25.5  0.0     0     52
+ 92 100    8      826     201    87  0.0  2.4  0.5 12.8 45.7  0.0     0     52
+ 93  98    8      810     196    83  0.0  2.5  0.5 14.0 24.4  0.0     0     52
+ 94  96    8      857     209    68  1.0  2.5  0.5 11.5 27.0  5.1     0     52
+ 95  95    8      771     174    91  0.0  2.6  0.5 10.5 26.5  0.0     0     52
+ 96  93    8      955     210    59  0.0  2.6  0.5 10.0 36.7  0.7     0     52
+ 97  91    8      833     206    53  0.0  2.7  0.5 10.2 19.4  1.4     0     52
+ 98  90    8      888     229    86  0.0  2.8  0.5  8.1 36.0  0.0     0     52
+ 99  88    8      794     186    91  1.0  2.9  0.5  8.3 25.0  0.5     0     52
+100  81    8      756     170    72  1.0  2.9  0.5  6.0 23.8  7.0     0     52
+101  74    8      791     176    67  0.0  2.9  0.5  4.4 58.3  4.0     0     52
+102  67    8      813     213    43  0.0  3.0  0.5  7.0 150.0  4.2     0     52
+103  62    8      779     245    39  0.0  3.1  0.5  3.2 16.7 13.0     0     52
+104  56    8      767     303    63  0.0  3.2  0.5  4.1 20.0  0.7     0     52
+105  52    8      757     270    57  0.0  3.5  0.5  6.4  3.7  0.5     0     52
+106  47    8      763     283    41  0.0  3.7  0.5  4.5  0.0  0.0     0     52
+107  43    8      768     283    36  0.0  3.7  0.5  2.9 18.2  3.6     0     52
+108  39    8      804     283    25  0.0  3.7  0.5  3.1  0.0  6.2     0     52
+109  36    8      781     283    24  0.0  3.7  0.5  3.6  6.7  6.7     0     52
+110  33    8      738     298    42  0.0  3.7  0.5  3.3 15.4  3.5     0     52
+111  30    8      761     298    36  0.0  3.7  0.5  2.2  0.0  4.3     0     52
+112  27    8      769     298    37  0.0  3.7  0.5  0.9  0.0  2.2     0     52
+113  25    8      745     298    31  0.0  3.7  0.5  1.5  0.0  6.6     0     52
+114  23    8      753     298    16  0.0  3.7  0.5  1.3  0.0  2.8     0     52
+115  21    8      745     298    11  0.0  3.7  0.5  1.5  0.0 14.0     0     52
+116  19    8      747     298    21  0.0  3.7  0.5  2.1  0.0  5.8     0     52
+117  13    8      737     298    12  0.0  3.7  0.5  1.0  0.0 10.0     0     52
+118   9    8      736     298     4  0.0  3.7  0.5  1.5  0.0 18.5     0     52
+119   0    8      739     298     0  0.0  3.7  0.5  1.8  0.0 18.0     0     52
+120   0    8      732     298     0  0.0  3.7  0.5  1.2  0.0 21.8     0     52
+121   0    8      732      19    -1 0.0  0.0  0.5  0.0 100.0 54.8
+
+Initial Wiring Cost: 645   Final Wiring Cost: 732
+############## Percent Wire Cost Reduction: -13
+
+
+Initial Wire Length: 645   Final Wire Length: 732
+************** Percent Wire Length Reduction: -13
+
+
+Initial Horiz. Wire: 216   Final Horiz. Wire: 147
+$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
+
+
+Initial Vert. Wire: 429   Final Vert. Wire: 585
+@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
+
+Before Feeds are Added:
+BLOCK      TOTAL CELL LENGTHS      OVER/UNDER TARGET
+  1                 82                   -20
+  2                 86                   -16
+
+LONGEST Block is:2   Its length is:86
+BLOCK      TOTAL CELL LENGTHS      OVER/UNDER TARGET
+  1                 86                   -16
+  2                 86                   -16
+
+LONGEST Block is:1   Its length is:86
+Added: 1  feed-through cells
+
+Removed the cell overlaps --- Will do neighbor interchanges only now
+
+TOTAL INTERCONNECT LENGTH: 994
+OVERLAP PENALTY: 0
+
+initialRowControl:   1.650
+finalRowControl:   0.300
+iter      T      Wire accept
+ 122  0.001       976   16%
+ 123  0.001       971    0%
+ 124  0.001       971    0%
+Total Feed-Alignment Movement (Pass 1): 0
+Total Feed-Alignment Movement (Pass 2): 0
+Total Feed-Alignment Movement (Pass 3): 0
+Total Feed-Alignment Movement (Pass 4): 0
+Total Feed-Alignment Movement (Pass 5): 0
+Total Feed-Alignment Movement (Pass 6): 0
+Total Feed-Alignment Movement (Pass 7): 0
+Total Feed-Alignment Movement (Pass 8): 0
+
+The rand generator seed was at globroute() : 987654321
+
+
+Total Number of Net Segments: 9
+Number of Switchable Net Segments: 0
+
+Number of channels: 3
+
+
+
+THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
+
+
+no. of accepted flips: 0
+no. of attempted flips: 0
+THIS IS THE NUMBER OF TRACKS: 5
+
+
+
+FINAL NUMBER OF ROUTING TRACKS: 5
+
+MAX OF CHANNEL:  1  is:   0
+MAX OF CHANNEL:  2  is:   4
+MAX OF CHANNEL:  3  is:   1
+FINAL TOTAL INTERCONNECT LENGTH: 978
+FINAL OVERLAP PENALTY: 0    FINAL VALUE OF TOTAL COST IS: 978
+MAX NUMBER OF ATTEMPTED FLIPS PER T:      55
+
+
+cost_scale_factor:3.90616
+
+Number of Feed Thrus: 0
+Number of Implicit Feed Thrus: 0
+
+Statistics:
+Number of Standard Cells: 10
+Number of Pads: 0 
+Number of Nets: 15 
+Number of Pins: 46 
+Usage statistics not available
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
new file mode 100644
index 000000000..079a70f11
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
@@ -0,0 +1,87 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.103107                       # Number of seconds simulated
+sim_ticks                                103106771000                       # Number of ticks simulated
+final_tick                               103106771000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                3006793                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1643182108                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 213456                       # Number of bytes of host memory used
+host_seconds                                    62.75                       # Real time elapsed on the host
+sim_insts                                   188670900                       # Number of instructions simulated
+system.physmem.bytes_read                   869973902                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read              759440240                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                 45252940                       # Number of bytes written to this memory
+system.physmem.num_reads                    219482514                       # Number of read requests responded to by this memory
+system.physmem.num_writes                    12386694                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                     8437602047                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                7365570977                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                     438893969                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                    8876496016                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                  400                       # Number of system calls
+system.cpu.numCycles                        206213543                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                        188670900                       # Number of instructions executed
+system.cpu.num_int_alu_accesses             150106226                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                1752310                       # Number of float alu accesses
+system.cpu.num_func_calls                     3504894                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     31949383                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    150106226                       # number of integer instructions
+system.cpu.num_fp_insts                       1752310                       # number of float instructions
+system.cpu.num_int_register_reads           809396650                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          294073530                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads              2822225                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes             2378039                       # number of times the floating registers were written
+system.cpu.num_mem_refs                      42494120                       # number of memory refs
+system.cpu.num_load_insts                    29849485                       # Number of load instructions
+system.cpu.num_store_insts                   12644635                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  206213543                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
new file mode 100644
index 000000000..3f54c6512
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
@@ -0,0 +1,205 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+memories=system.physmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[0]
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[2]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simerr b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simerr
new file mode 100755
index 000000000..e45cd058f
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simerr
@@ -0,0 +1,2 @@
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
new file mode 100755
index 000000000..b21763742
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
@@ -0,0 +1,26 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:16:21
+gem5 started Jan 23 2012 09:52:01
+gem5 executing on zizzer
+command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing
+Couldn't unlink  build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sav
+Couldn't unlink  build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sv2
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+         Yale University
+info: Increasing stack size by one page.
+  1   2   3   4   5   6   7   8   9  10  11  12  13  14  15 
+ 16  17  18  19  20  21  22  23  24  25  26  27  28  29  30 
+ 31  32  33  34  35  36  37  38  39  40  41  42  43  44  45 
+ 46  47  48  49  50  51  52  53  54  55  56  57  58  59  60 
+ 61  62  63  64  65  66  67  68  69  70  71  72  73  74  75 
+ 76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
+ 91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
+122 123 124 Exiting @ tick 232077154000 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/smred.out b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/smred.out
new file mode 100644
index 000000000..00387ae5c
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/smred.out
@@ -0,0 +1,276 @@
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+          Yale University
+
+
+NOTE: Restart file .rs2 not used
+
+TimberWolf will perform a global route step
+rowSep: 1.000000
+feedThruWidth: 4
+
+******************
+BLOCK DATA
+block:1 desire:85
+block:2 desire:85
+Total Desired Length: 170
+total cell length: 168
+total block length: 168
+block x-span:84  block y-span:78
+implicit feed thru range: -84
+Using default value of bin.penalty.control:1.000000
+numBins automatically set to:5
+binWidth = average_cell_width + 0 sigma= 17
+average_cell_width is:16
+standard deviation of cell length is:23.6305
+TimberWolfSC starting from the beginning
+
+
+
+THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
+The number of nets with 1 pin is 4
+The number of nets with 2 pin is 9
+The number of nets with 3 pin is 0
+The number of nets with 4 pin is 2
+The number of nets with 5 pin is 0
+The number of nets with 6 pin is 0
+The number of nets with 7 pin is 0
+The number of nets with 8 pin is 0
+The number of nets with 9 pin is 0
+The number of nets with 10 pin or more is 0
+
+New Cost Function: Initial Horizontal Cost:242
+New Cost Function: FEEDS:0   MISSING_ROWS:-46
+
+bdxlen:86  bdylen:78
+l:0  t:78  r:86  b:0
+
+
+
+THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
+
+
+
+THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
+
+The rand generator seed was at utemp() : 1
+
+
+  tempfile[0][0] = 0.982500    tempfile[0][1] = 90.000000
+  tempfile[1][0] = 0.915000    tempfile[1][1] = 20.000000
+  tempfile[2][0] = 0.700000    tempfile[2][1] = 10.000000
+  tempfile[3][0] = 0.100000    tempfile[3][1] = 0.000000
+
+  I   T  fds     Wire Penalty P_lim Epct binC rowC  acc  s/p early  FDs    MRs
+  1 500    0      929     592   160 30.0  1.0  3.0 84.2 34.7  0.0     0     40
+  2 491    0      876     106   726  0.0  0.8  2.5 80.0 18.5  0.0     0     46
+  3 482    0      822     273   372  0.0  0.5  1.5 80.8 21.2  0.0     0     46
+  4 474    0      826      53   247  0.0  0.5  0.9 65.0 21.9  0.0     0     48
+  5 465    8      987      73   190  0.0  0.5  0.5 50.0 38.3  0.0     0     46
+  6 457    8      851      67   226  0.0  0.5  0.5 53.8 42.9  0.0     0     52
+  7 449    8     1067     108   190  0.0  0.5  0.5 46.2 53.8  0.0     0     50
+  8 441    8      918     106   171  0.0  0.5  0.5 47.1 40.4  0.0     0     48
+  9 434    8      812     101   197  0.0  0.5  0.5 53.6 21.0  0.0     0     48
+ 10 426    8     1038     121   181  0.0  0.5  0.5 43.6 27.1  0.0     0     48
+ 11 419    8      898      93   187  0.0  0.5  0.5 45.3 47.8  0.0     0     50
+ 12 411    4      857      94   240  0.0  0.5  0.5 62.7 51.6  0.0     0     44
+ 13 404    8     1043      88   185  0.0  0.5  0.5 54.0 52.8  0.0     0     50
+ 14 397    8      767      94   154  0.0  0.5  0.5 33.8 35.0  0.0     0     50
+ 15 390    8      862      89   183  0.0  0.5  0.5 55.6 29.0  0.0     0     46
+ 16 383    4      798      79   173  0.0  0.5  0.5 57.5 35.3  0.0     0     52
+ 17 376    8      827     100   152  0.0  0.5  0.5 35.3 81.8  0.0     0     50
+ 18 370    8      878     101   208  0.0  0.5  0.5 44.7 46.2  0.0     0     48
+ 19 363    4      921      67   167  0.0  0.5  0.5 57.1 34.7  0.0     0     48
+ 20 357    8      933      93   154  0.0  0.5  0.5 46.5 43.6  0.0     0     52
+ 21 351    8      930      89   147  0.0  0.5  0.5 39.4 36.5  0.0     0     52
+ 22 345    8      951      79   142  0.0  0.5  0.5 32.8 51.3  0.0     0     50
+ 23 339    8     1046      87   207  0.0  0.5  0.5 52.8 61.0  0.0     0     48
+ 24 333    4      989      96   185  0.0  0.5  0.5 45.3 43.3  0.0     0     42
+ 25 327    4      577      86   157  0.0  0.5  0.5 31.1 55.3  0.0     0     52
+ 26 321    8      776      97   174  0.0  0.5  0.5 47.9 62.5  0.0     0     52
+ 27 315    8      850      81   188  0.0  0.5  0.5 45.0 55.2  0.0     0     50
+ 28 310    8      898      97   148  0.0  0.5  0.5 43.0 45.8  0.0     0     48
+ 29 304    8      889      65   173  0.0  0.5  0.5 32.5 41.3  0.0     0     50
+ 30 299    8      858      81   153  0.0  0.5  0.5 44.3 29.2  0.0     0     46
+ 31 294    8      871      82   187  0.0  0.5  0.5 45.7 47.7  0.0     0     48
+ 32 289    8      782     109   173  0.0  0.5  0.5 35.2 57.4  0.0     0     48
+ 33 284    8      743      98   189  0.0  0.6  0.5 41.8 64.3  0.0     0     52
+ 34 279    8      943      90   147  0.0  0.5  0.5 38.6 32.8  0.0     0     48
+ 35 274    8      907      57   166  0.0  0.5  0.5 33.6 51.0  0.0     0     48
+ 36 269    8      900      70   148  0.0  0.5  0.5 45.0 41.4  0.0     0     50
+ 37 264    4      875     106   133  0.0  0.5  0.5 31.7 55.3  0.0     0     52
+ 38 260    8     1023     145   149  0.0  0.6  0.5 28.7 65.0  0.0     0     52
+ 39 255    8      801     151   173  0.0  0.9  0.5 41.7 41.2  0.0     0     48
+ 40 251    8      741     104   159  0.0  0.8  0.5 36.2 47.5  0.0     0     48
+ 41 246    8      828     108   149  0.0  0.5  0.5 34.6 50.9  0.0     0     50
+ 42 242    8      947     128   132  0.0  0.7  0.5 34.2 39.0  0.0     0     50
+ 43 238    8      917     101   142  0.0  0.8  0.5 34.4 50.9  0.0     0     48
+ 44 234    8      761      86   129  0.0  0.5  0.5 42.0 36.4  0.0     0     52
+ 45 229    8      979     106   137  0.0  0.5  0.5 29.2 55.3  0.0     0     50
+ 46 225    8      806      74   130  0.0  0.7  0.5 33.1 65.4  0.0     0     52
+ 47 221    8      971     125   114  0.0  0.5  0.5 31.9 45.6  0.0     0     52
+ 48 218    8      869     125   104  0.0  0.9  0.5 30.0 56.0  0.0     0     48
+ 49 214    8      999     153   140  0.0  0.8  0.5 30.4 46.4  0.0     0     52
+ 50 210    8      798     192   139  0.0  1.0  0.5 28.9 50.0  0.0     0     52
+ 51 206    8      860     125   157  0.0  1.2  0.5 31.5 26.9  0.0     0     52
+ 52 203    8      893     186   127  5.9  0.9  0.5 26.4 42.3  0.0     0     46
+ 53 199    8      863     126   141  0.0  1.2  0.5 32.5 44.4  0.0     0     44
+ 54 196    8      788      97   133  0.0  0.9  0.5 37.5 40.0  0.0     0     50
+ 55 192    8      926     119   116  0.0  0.6  0.5 26.1 55.3  0.0     0     52
+ 56 189    8      789     162   107  0.0  0.8  0.5 25.2 40.4  0.0     0     48
+ 57 186    8      878     107   128  0.0  1.1  0.5 23.1 34.0  0.0     0     52
+ 58 182    8      775     105   122  0.0  0.8  0.5 25.5 57.4  0.0     0     50
+ 59 179    8      747      94   129  0.0  0.7  0.5 34.3 37.3  0.0     0     50
+ 60 176    8      845      96   138  0.0  0.6  0.5 28.3 41.7  0.0     0     52
+ 61 173    8      961     121   110  0.0  0.6  0.5 29.0 52.6  0.0     0     48
+ 62 170    4      911     110   109  0.0  0.9  0.5 33.5 33.3  0.0     0     48
+ 63 167    8      656     109   109  0.0  0.8  0.5 21.9 44.7  0.0     0     52
+ 64 164    8      934     117   105  0.0  0.8  0.5 15.5 50.0  0.0     0     52
+ 65 161    8      972     125    95  0.0  0.8  0.5 24.4 50.0  0.0     0     50
+ 66 158    8      894     125   101  0.0  0.9  0.5 27.2 35.9  0.0     0     52
+ 67 155    8      798     146   129  0.0  1.0  0.5 22.8 58.7  0.0     0     52
+ 68 153    8      901     183    92  0.0  1.1  0.5 23.6 34.5  0.0     0     52
+ 69 150    8      977     197   103  0.0  1.4  0.5 23.6 36.8  0.0     0     52
+ 70 147    8      905     262    93  0.0  1.5  0.5 20.3 63.4  0.0     0     52
+ 71 145    8      995     148   122  0.0  1.9  0.5 20.9 35.3  0.0     0     52
+ 72 142    8      934     230    99  0.0  1.6  0.5 20.0 65.9  0.0     0     52
+ 73 140    8      862     173   100  0.0  1.8  0.5 26.8 46.8  0.0     0     52
+ 74 137    8      924     139    90  0.0  1.7  0.5 16.8 42.5  0.0     0     52
+ 75 135    8      888     168   113  0.0  1.6  0.5 22.9 40.4  0.0     0     52
+ 76 133    8      712     212    84  0.0  1.6  0.5 13.4 46.9  0.0     0     52
+ 77 130    8      868     210    91  0.0  1.7  0.5 17.7 51.2  0.0     0     52
+ 78 128    8      952     307    92  0.0  1.9  0.5 19.7 44.9  0.0     0     50
+ 79 126    8      801     157   107  0.0  2.2  0.5 15.8 39.0  0.0     0     52
+ 80 123    8      849     147    93  0.0  2.1  0.5 15.6 51.4  0.0     0     52
+ 81 121    8      799     154    86  0.0  1.9  0.5 12.2 50.0  0.0     0     52
+ 82 119    8      941     213    82  0.0  1.8  0.5 19.5 41.2  0.0     0     50
+ 83 117    8      751     268    94  0.0  2.0  0.5 20.8 42.6  0.0     0     50
+ 84 115    8      828     198   102  0.0  2.2  0.5 15.5 59.5  0.0     0     52
+ 85 113    8      898     266   123  0.0  2.2  0.5 13.2 85.2  0.0     0     52
+ 86 111    8      943     190    93  0.0  2.4  0.5 19.5 45.1  0.0     0     52
+ 87 109    8      864     183    65  0.0  2.4  0.5 14.9 31.8  0.0     0     52
+ 88 107    8      793     203    93  0.0  2.4  0.5 11.8 35.3  0.0     0     52
+ 89 105    8      752     162    74  1.2  2.4  0.5 13.1 21.4  0.0     0     52
+ 90 103    8      801     149    77  0.0  2.3  0.5  9.7 58.3  0.0     0     52
+ 91 102    8      901     230    99  0.0  2.2  0.5 16.0 25.5  0.0     0     52
+ 92 100    8      826     201    87  0.0  2.4  0.5 12.8 45.7  0.0     0     52
+ 93  98    8      810     196    83  0.0  2.5  0.5 14.0 24.4  0.0     0     52
+ 94  96    8      857     209    68  1.0  2.5  0.5 11.5 27.0  5.1     0     52
+ 95  95    8      771     174    91  0.0  2.6  0.5 10.5 26.5  0.0     0     52
+ 96  93    8      955     210    59  0.0  2.6  0.5 10.0 36.7  0.7     0     52
+ 97  91    8      833     206    53  0.0  2.7  0.5 10.2 19.4  1.4     0     52
+ 98  90    8      888     229    86  0.0  2.8  0.5  8.1 36.0  0.0     0     52
+ 99  88    8      794     186    91  1.0  2.9  0.5  8.3 25.0  0.5     0     52
+100  81    8      756     170    72  1.0  2.9  0.5  6.0 23.8  7.0     0     52
+101  74    8      791     176    67  0.0  2.9  0.5  4.4 58.3  4.0     0     52
+102  67    8      813     213    43  0.0  3.0  0.5  7.0 150.0  4.2     0     52
+103  62    8      779     245    39  0.0  3.1  0.5  3.2 16.7 13.0     0     52
+104  56    8      767     303    63  0.0  3.2  0.5  4.1 20.0  0.7     0     52
+105  52    8      757     270    57  0.0  3.5  0.5  6.4  3.7  0.5     0     52
+106  47    8      763     283    41  0.0  3.7  0.5  4.5  0.0  0.0     0     52
+107  43    8      768     283    36  0.0  3.7  0.5  2.9 18.2  3.6     0     52
+108  39    8      804     283    25  0.0  3.7  0.5  3.1  0.0  6.2     0     52
+109  36    8      781     283    24  0.0  3.7  0.5  3.6  6.7  6.7     0     52
+110  33    8      738     298    42  0.0  3.7  0.5  3.3 15.4  3.5     0     52
+111  30    8      761     298    36  0.0  3.7  0.5  2.2  0.0  4.3     0     52
+112  27    8      769     298    37  0.0  3.7  0.5  0.9  0.0  2.2     0     52
+113  25    8      745     298    31  0.0  3.7  0.5  1.5  0.0  6.6     0     52
+114  23    8      753     298    16  0.0  3.7  0.5  1.3  0.0  2.8     0     52
+115  21    8      745     298    11  0.0  3.7  0.5  1.5  0.0 14.0     0     52
+116  19    8      747     298    21  0.0  3.7  0.5  2.1  0.0  5.8     0     52
+117  13    8      737     298    12  0.0  3.7  0.5  1.0  0.0 10.0     0     52
+118   9    8      736     298     4  0.0  3.7  0.5  1.5  0.0 18.5     0     52
+119   0    8      739     298     0  0.0  3.7  0.5  1.8  0.0 18.0     0     52
+120   0    8      732     298     0  0.0  3.7  0.5  1.2  0.0 21.8     0     52
+121   0    8      732      19    -1 0.0  0.0  0.5  0.0 100.0 54.8
+
+Initial Wiring Cost: 645   Final Wiring Cost: 732
+############## Percent Wire Cost Reduction: -13
+
+
+Initial Wire Length: 645   Final Wire Length: 732
+************** Percent Wire Length Reduction: -13
+
+
+Initial Horiz. Wire: 216   Final Horiz. Wire: 147
+$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
+
+
+Initial Vert. Wire: 429   Final Vert. Wire: 585
+@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
+
+Before Feeds are Added:
+BLOCK      TOTAL CELL LENGTHS      OVER/UNDER TARGET
+  1                 82                   -20
+  2                 86                   -16
+
+LONGEST Block is:2   Its length is:86
+BLOCK      TOTAL CELL LENGTHS      OVER/UNDER TARGET
+  1                 86                   -16
+  2                 86                   -16
+
+LONGEST Block is:1   Its length is:86
+Added: 1  feed-through cells
+
+Removed the cell overlaps --- Will do neighbor interchanges only now
+
+TOTAL INTERCONNECT LENGTH: 994
+OVERLAP PENALTY: 0
+
+initialRowControl:   1.650
+finalRowControl:   0.300
+iter      T      Wire accept
+ 122  0.001       976   16%
+ 123  0.001       971    0%
+ 124  0.001       971    0%
+Total Feed-Alignment Movement (Pass 1): 0
+Total Feed-Alignment Movement (Pass 2): 0
+Total Feed-Alignment Movement (Pass 3): 0
+Total Feed-Alignment Movement (Pass 4): 0
+Total Feed-Alignment Movement (Pass 5): 0
+Total Feed-Alignment Movement (Pass 6): 0
+Total Feed-Alignment Movement (Pass 7): 0
+Total Feed-Alignment Movement (Pass 8): 0
+
+The rand generator seed was at globroute() : 987654321
+
+
+Total Number of Net Segments: 9
+Number of Switchable Net Segments: 0
+
+Number of channels: 3
+
+
+
+THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
+
+
+no. of accepted flips: 0
+no. of attempted flips: 0
+THIS IS THE NUMBER OF TRACKS: 5
+
+
+
+FINAL NUMBER OF ROUTING TRACKS: 5
+
+MAX OF CHANNEL:  1  is:   0
+MAX OF CHANNEL:  2  is:   4
+MAX OF CHANNEL:  3  is:   1
+FINAL TOTAL INTERCONNECT LENGTH: 978
+FINAL OVERLAP PENALTY: 0    FINAL VALUE OF TOTAL COST IS: 978
+MAX NUMBER OF ATTEMPTED FLIPS PER T:      55
+
+
+cost_scale_factor:3.90616
+
+Number of Feed Thrus: 0
+Number of Implicit Feed Thrus: 0
+
+Statistics:
+Number of Standard Cells: 10
+Number of Pads: 0 
+Number of Nets: 15 
+Number of Pins: 46 
+Usage statistics not available
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
new file mode 100644
index 000000000..d861ddab1
--- /dev/null
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
@@ -0,0 +1,279 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.232077                       # Number of seconds simulated
+sim_ticks                                232077154000                       # Number of ticks simulated
+final_tick                               232077154000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                1497030                       # Simulator instruction rate (inst/s)
+host_tick_rate                             1846187485                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 222460                       # Number of bytes of host memory used
+host_seconds                                   125.71                       # Real time elapsed on the host
+sim_insts                                   188185929                       # Number of instructions simulated
+system.physmem.bytes_read                      220992                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                 110656                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                         3453                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                         952235                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read                    476807                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total                        952235                       # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                            0                       # DTB read hits
+system.cpu.dtb.read_misses                          0                       # DTB read misses
+system.cpu.dtb.write_hits                           0                       # DTB write hits
+system.cpu.dtb.write_misses                         0                       # DTB write misses
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                  400                       # Number of system calls
+system.cpu.numCycles                        464154308                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.num_insts                        188185929                       # Number of instructions executed
+system.cpu.num_int_alu_accesses             150106226                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                1752310                       # Number of float alu accesses
+system.cpu.num_func_calls                     3504894                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     31949383                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    150106226                       # number of integer instructions
+system.cpu.num_fp_insts                       1752310                       # number of float instructions
+system.cpu.num_int_register_reads           898652287                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          294073530                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads              2822225                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes             2378039                       # number of times the floating registers were written
+system.cpu.num_mem_refs                      42494120                       # number of memory refs
+system.cpu.num_load_insts                    29849485                       # Number of load instructions
+system.cpu.num_store_insts                   12644635                       # Number of store instructions
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.num_busy_cycles                  464154308                       # Number of busy cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.icache.replacements                   1506                       # number of replacements
+system.cpu.icache.tagsinuse               1147.981155                       # Cycle average of tags in use
+system.cpu.icache.total_refs                189857010                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   3051                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               62227.797443                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::0           1147.981155                       # Average occupied blocks per context
+system.cpu.icache.occ_percent::0             0.560538                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits              189857010                       # number of ReadReq hits
+system.cpu.icache.demand_hits               189857010                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits              189857010                       # number of overall hits
+system.cpu.icache.ReadReq_misses                 3051                       # number of ReadReq misses
+system.cpu.icache.demand_misses                  3051                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses                 3051                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency      115332000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency       115332000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency      115332000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses          189860061                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses           189860061                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses          189860061                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate          0.000016                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate           0.000016                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate          0.000016                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency 37801.376598                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency 37801.376598                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 37801.376598                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses            3051                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses             3051                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses            3051                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency    106179000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency    106179000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency    106179000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000016                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate      0.000016                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate     0.000016                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34801.376598                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34801.376598                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 34801.376598                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                     40                       # number of replacements
+system.cpu.dcache.tagsinuse               1363.604315                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 42007359                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                   1789                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs               23480.916154                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::0           1363.604315                       # Average occupied blocks per context
+system.cpu.dcache.occ_percent::0             0.332911                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits               29599358                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits              12363187                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits            22407                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits             22407                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits                41962545                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits               41962545                       # number of overall hits
+system.cpu.dcache.ReadReq_misses                  689                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses                1100                       # number of WriteReq misses
+system.cpu.dcache.demand_misses                  1789                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses                 1789                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency       36190000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency      61264000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency        97454000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency       97454000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses           29600047                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses          12364287                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses        22407                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses         22407                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses            41964334                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses           41964334                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate          0.000023                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate         0.000089                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate           0.000043                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate          0.000043                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency 52525.399129                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 55694.545455                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency 54474.007826                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency 54474.007826                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks                       16                       # number of writebacks
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses             689                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses           1100                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses             1789                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses            1789                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency     34123000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency     57964000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency     92087000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency     92087000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.000023                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000089                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate      0.000043                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate     0.000043                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 49525.399129                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52694.545455                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 51474.007826                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 51474.007826                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                     0                       # number of replacements
+system.cpu.l2cache.tagsinuse              1675.648030                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                    1379                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  2369                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.582102                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::0          1672.609981                       # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1             3.038048                       # Average occupied blocks per context
+system.cpu.l2cache.occ_percent::0            0.051044                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::1            0.000093                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits                  1379                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits                  16                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits                   8                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits                   1387                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits                  1387                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses                2361                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses              1092                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses                 3453                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses                3453                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency     122772000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency     56784000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency      179556000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency     179556000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses              3740                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses              16                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses            1100                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses               4840                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses              4840                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate         0.631283                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate       0.992727                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate          0.713430                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate         0.713430                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks                       0                       # number of writebacks
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses           2361                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses         1092                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses            3453                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses           3453                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency     94440000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency     43680000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency    138120000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency    138120000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.631283                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.992727                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate     0.713430                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate     0.713430                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------