diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-08-15 10:38:05 -0400 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-08-15 10:38:05 -0400 |
| commit | 73e9e923d00c6f5df9e79a6c40ecc159894d2bc5 (patch) | |
| tree | f84188c6697fe79f0521b73d9d38855ce7e04d29 /tests/long/se/70.twolf/ref/sparc | |
| parent | dd1b346584e520ba970e62aa3bcc7d32828cdeba (diff) | |
| download | gem5-73e9e923d00c6f5df9e79a6c40ecc159894d2bc5.tar.xz | |
stats: Update stats for syscall emulation Linux kernel changes.
Diffstat (limited to 'tests/long/se/70.twolf/ref/sparc')
6 files changed, 102 insertions, 102 deletions
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini index 505ad335a..48cbbbbde 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini @@ -99,8 +99,8 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 -master=system.physmem.port[0] +width=8 +master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.physmem] diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout index 435dd5018..a6bbf65c9 100755 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:01:47 -gem5 started Jun 4 2012 15:01:23 +gem5 compiled Aug 13 2012 17:04:37 +gem5 started Aug 13 2012 18:21:10 gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sav @@ -23,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 info: Increasing stack size by one page. -122 123 124 Exiting @ tick 96722951500 because target called exit() +122 123 124 Exiting @ tick 96722945000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt index 7fc4c3f51..fd4974069 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.096723 # Number of seconds simulated -sim_ticks 96722951500 # Number of ticks simulated -final_tick 96722951500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 96722945000 # Number of ticks simulated +final_tick 96722945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2785942 # Simulator instruction rate (inst/s) -host_op_rate 2785945 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1392980356 # Simulator tick rate (ticks/s) -host_mem_usage 218424 # Number of bytes of host memory used -host_seconds 69.44 # Real time elapsed on the host -sim_insts 193444531 # Number of instructions simulated -sim_ops 193444769 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 773782192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 223463414 # Number of bytes read from this memory -system.physmem.bytes_read::total 997245606 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 773782192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 773782192 # Number of instructions bytes read from this memory +host_inst_rate 2917410 # Simulator instruction rate (inst/s) +host_op_rate 2917413 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1458714810 # Simulator tick rate (ticks/s) +host_mem_usage 226640 # Number of bytes of host memory used +host_seconds 66.31 # Real time elapsed on the host +sim_insts 193444518 # Number of instructions simulated +sim_ops 193444756 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 773782140 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 223463413 # Number of bytes read from this memory +system.physmem.bytes_read::total 997245553 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 773782140 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 773782140 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 72065412 # Number of bytes written to this memory system.physmem.bytes_written::total 72065412 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 193445548 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 57735069 # Number of read requests responded to by this memory -system.physmem.num_reads::total 251180617 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 193445535 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 57735068 # Number of read requests responded to by this memory +system.physmem.num_reads::total 251180603 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 18976439 # Number of write requests responded to by this memory system.physmem.num_writes::total 18976439 # Number of write requests responded to by this memory system.physmem.num_other::cpu.data 22406 # Number of other requests responded to by this memory system.physmem.num_other::total 22406 # Number of other requests responded to by this memory system.physmem.bw_read::cpu.inst 7999985319 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2310345275 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10310330594 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2310345420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10310330739 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 7999985319 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 7999985319 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 745070440 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 745070440 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 745070490 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 745070490 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::cpu.inst 7999985319 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3055415715 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11055401034 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3055415910 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11055401229 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 401 # Number of system calls -system.cpu.numCycles 193445904 # number of cpu cycles simulated +system.cpu.numCycles 193445891 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 193444531 # Number of instructions committed -system.cpu.committedOps 193444769 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 167974818 # Number of integer alu accesses +system.cpu.committedInsts 193444518 # Number of instructions committed +system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses system.cpu.num_func_calls 1957920 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8665107 # number of instructions that are conditional controls -system.cpu.num_int_insts 167974818 # number of integer instructions +system.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls +system.cpu.num_int_insts 167974806 # number of integer instructions system.cpu.num_fp_insts 1970372 # number of float instructions -system.cpu.num_int_register_reads 352617963 # number of times the integer registers were read -system.cpu.num_int_register_writes 163060137 # number of times the integer registers were written +system.cpu.num_int_register_reads 352617941 # number of times the integer registers were read +system.cpu.num_int_register_writes 163060124 # number of times the integer registers were written system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written -system.cpu.num_mem_refs 76733959 # number of memory refs -system.cpu.num_load_insts 57735092 # Number of load instructions +system.cpu.num_mem_refs 76733958 # number of memory refs +system.cpu.num_load_insts 57735091 # Number of load instructions system.cpu.num_store_insts 18998867 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 193445904 # Number of busy cycles +system.cpu.num_busy_cycles 193445891 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini index fd32216ef..27af806dd 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -158,7 +158,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing +cwd=build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing egid=100 env= errout=cerr @@ -181,7 +181,7 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout index 123985114..d049db054 100755 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:54:18 -gem5 started Jul 2 2012 12:35:14 +gem5 compiled Aug 13 2012 17:04:37 +gem5 started Aug 13 2012 18:21:48 gem5 executing on zizzer -command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing -Couldn't unlink build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing/smred.sav -Couldn't unlink build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing/smred.sv2 +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing +Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sav +Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 info: Increasing stack size by one page. -122 123 124 Exiting @ tick 270628681000 because target called exit() +122 123 124 Exiting @ tick 270628667000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index 23f251d47..9d89c8f58 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.270629 # Number of seconds simulated -sim_ticks 270628681000 # Number of ticks simulated -final_tick 270628681000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 270628667000 # Number of ticks simulated +final_tick 270628667000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1015199 # Simulator instruction rate (inst/s) -host_op_rate 1015200 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1420261450 # Simulator tick rate (ticks/s) -host_mem_usage 225612 # Number of bytes of host memory used -host_seconds 190.55 # Real time elapsed on the host -sim_insts 193444531 # Number of instructions simulated -sim_ops 193444769 # Number of ops (including micro ops) simulated +host_inst_rate 1532509 # Simulator instruction rate (inst/s) +host_op_rate 1532510 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2143977461 # Simulator tick rate (ticks/s) +host_mem_usage 235212 # Number of bytes of host memory used +host_seconds 126.23 # Real time elapsed on the host +sim_insts 193444518 # Number of instructions simulated +sim_ops 193444756 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory system.physmem.bytes_read::total 331072 # Number of bytes read from this memory @@ -28,43 +28,43 @@ system.physmem.bw_total::cpu.inst 850642 # To system.physmem.bw_total::cpu.data 372703 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1223344 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 401 # Number of system calls -system.cpu.numCycles 541257362 # number of cpu cycles simulated +system.cpu.numCycles 541257334 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 193444531 # Number of instructions committed -system.cpu.committedOps 193444769 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 167974818 # Number of integer alu accesses +system.cpu.committedInsts 193444518 # Number of instructions committed +system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses system.cpu.num_func_calls 1957920 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8665107 # number of instructions that are conditional controls -system.cpu.num_int_insts 167974818 # number of integer instructions +system.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls +system.cpu.num_int_insts 167974806 # number of integer instructions system.cpu.num_fp_insts 1970372 # number of float instructions -system.cpu.num_int_register_reads 352617963 # number of times the integer registers were read -system.cpu.num_int_register_writes 163060136 # number of times the integer registers were written +system.cpu.num_int_register_reads 352617941 # number of times the integer registers were read +system.cpu.num_int_register_writes 163060123 # number of times the integer registers were written system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written -system.cpu.num_mem_refs 76733959 # number of memory refs -system.cpu.num_load_insts 57735092 # Number of load instructions +system.cpu.num_mem_refs 76733958 # number of memory refs +system.cpu.num_load_insts 57735091 # Number of load instructions system.cpu.num_store_insts 18998867 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 541257362 # Number of busy cycles +system.cpu.num_busy_cycles 541257334 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 10362 # number of replacements -system.cpu.icache.tagsinuse 1591.549936 # Cycle average of tags in use -system.cpu.icache.total_refs 193433261 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1591.550018 # Cycle average of tags in use +system.cpu.icache.total_refs 193433248 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 15741.639079 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 15741.638021 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1591.549936 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1591.550018 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.777124 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.777124 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 193433261 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 193433261 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 193433261 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 193433261 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 193433261 # number of overall hits -system.cpu.icache.overall_hits::total 193433261 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 193433248 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 193433248 # number of overall hits +system.cpu.icache.overall_hits::total 193433248 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 12288 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 12288 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 12288 # number of demand (read+write) misses @@ -77,12 +77,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 323106000 system.cpu.icache.demand_miss_latency::total 323106000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 323106000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 323106000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 193445549 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 193445549 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 193445549 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 193445549 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 193445549 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 193445549 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 193445536 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 193445536 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 193445536 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000064 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000064 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 # miss rate for demand accesses @@ -129,24 +129,24 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23294.433594 system.cpu.icache.overall_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2 # number of replacements -system.cpu.dcache.tagsinuse 1237.179086 # Cycle average of tags in use -system.cpu.dcache.total_refs 76732338 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1237.179149 # Cycle average of tags in use +system.cpu.dcache.total_refs 76732337 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1576 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 48688.031726 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 48688.031091 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1237.179086 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 1237.179149 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.302046 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.302046 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 57734571 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 57734571 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 76709933 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 76709933 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 76709933 # number of overall hits -system.cpu.dcache.overall_hits::total 76709933 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 76709932 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 76709932 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 76709932 # number of overall hits +system.cpu.dcache.overall_hits::total 76709932 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 498 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 498 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1077 # number of WriteReq misses @@ -167,16 +167,16 @@ system.cpu.dcache.demand_miss_latency::cpu.data 88200000 system.cpu.dcache.demand_miss_latency::total 88200000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 88200000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 88200000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 57735069 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 57735069 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 18976439 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 22406 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 22406 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 76711508 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 76711508 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 76711508 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 76711508 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 76711507 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 76711507 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 76711507 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 76711507 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000009 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses @@ -249,14 +249,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2678.289467 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2678.289604 # Cycle average of tags in use system.cpu.l2cache.total_refs 8691 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 4097 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.121308 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 0.000456 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2275.240506 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 403.048505 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2275.240623 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 403.048526 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.069435 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy |