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authorAli Saidi <saidi@eecs.umich.edu>2012-06-05 01:23:16 -0400
committerAli Saidi <saidi@eecs.umich.edu>2012-06-05 01:23:16 -0400
commitc49e739352b6d6bd665c78c560602d0cff1e6a1a (patch)
tree5d32efd82f884376573604727d971a80458ed04a /tests/long/se/70.twolf/ref/sparc
parente5f0d6016ba768c06b36d8b3d54f3ea700a4aa58 (diff)
downloadgem5-c49e739352b6d6bd665c78c560602d0cff1e6a1a.tar.xz
all: Update stats for memory per master and total fix.
Diffstat (limited to 'tests/long/se/70.twolf/ref/sparc')
-rw-r--r--tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini3
-rwxr-xr-xtests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr1
-rwxr-xr-xtests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout6
-rw-r--r--tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt44
-rw-r--r--tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini6
-rwxr-xr-xtests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout6
-rw-r--r--tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt83
7 files changed, 108 insertions, 41 deletions
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
index b2ac1c016..505ad335a 100644
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
@@ -94,9 +94,8 @@ system=system
uid=100
[system.membus]
-type=Bus
+type=CoherentBus
block_size=64
-bus_id=0
clock=1000
header_cycles=1
use_default_range=false
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr
index e45cd058f..7edd901b2 100755
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr
@@ -1,2 +1,3 @@
+warn: CoherentBus system.membus has no snooping ports attached!
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout
index fe38fbd1a..435dd5018 100755
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 8 2012 15:05:42
-gem5 started May 8 2012 15:47:40
-gem5 executing on piton
+gem5 compiled Jun 4 2012 12:01:47
+gem5 started Jun 4 2012 15:01:23
+gem5 executing on zizzer
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic
Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sav
Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sv2
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
index 417f58ce8..7fc4c3f51 100644
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
@@ -4,23 +4,37 @@ sim_seconds 0.096723 # Nu
sim_ticks 96722951500 # Number of ticks simulated
final_tick 96722951500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1581365 # Simulator instruction rate (inst/s)
-host_op_rate 1581366 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 790687708 # Simulator tick rate (ticks/s)
-host_mem_usage 217932 # Number of bytes of host memory used
-host_seconds 122.33 # Real time elapsed on the host
+host_inst_rate 2785942 # Simulator instruction rate (inst/s)
+host_op_rate 2785945 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1392980356 # Simulator tick rate (ticks/s)
+host_mem_usage 218424 # Number of bytes of host memory used
+host_seconds 69.44 # Real time elapsed on the host
sim_insts 193444531 # Number of instructions simulated
sim_ops 193444769 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read 997245606 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 773782192 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 72065412 # Number of bytes written to this memory
-system.physmem.num_reads 251180617 # Number of read requests responded to by this memory
-system.physmem.num_writes 18976439 # Number of write requests responded to by this memory
-system.physmem.num_other 22406 # Number of other requests responded to by this memory
-system.physmem.bw_read 10310330594 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 7999985319 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 745070440 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 11055401034 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst 773782192 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 223463414 # Number of bytes read from this memory
+system.physmem.bytes_read::total 997245606 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 773782192 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 773782192 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data 72065412 # Number of bytes written to this memory
+system.physmem.bytes_written::total 72065412 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 193445548 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 57735069 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 251180617 # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data 18976439 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 18976439 # Number of write requests responded to by this memory
+system.physmem.num_other::cpu.data 22406 # Number of other requests responded to by this memory
+system.physmem.num_other::total 22406 # Number of other requests responded to by this memory
+system.physmem.bw_read::cpu.inst 7999985319 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2310345275 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 10310330594 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 7999985319 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 7999985319 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 745070440 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 745070440 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 7999985319 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 3055415715 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 11055401034 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 401 # Number of system calls
system.cpu.numCycles 193445904 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
index af9f6c271..35d8a380c 100644
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
@@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
-type=Bus
+type=CoherentBus
block_size=64
-bus_id=0
clock=1000
header_cycles=1
use_default_range=false
@@ -176,9 +175,8 @@ system=system
uid=100
[system.membus]
-type=Bus
+type=CoherentBus
block_size=64
-bus_id=0
clock=1000
header_cycles=1
use_default_range=false
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout
index f7fdf9677..8467606a8 100755
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 8 2012 15:05:42
-gem5 started May 8 2012 15:49:18
-gem5 executing on piton
+gem5 compiled Jun 4 2012 12:01:47
+gem5 started Jun 4 2012 15:02:43
+gem5 executing on zizzer
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing
Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sav
Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sv2
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
index 415ede7b3..170992582 100644
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
@@ -4,22 +4,29 @@ sim_seconds 0.270577 # Nu
sim_ticks 270576960000 # Number of ticks simulated
final_tick 270576960000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 668557 # Simulator instruction rate (inst/s)
-host_op_rate 668558 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 935131366 # Simulator tick rate (ticks/s)
-host_mem_usage 226812 # Number of bytes of host memory used
-host_seconds 289.35 # Real time elapsed on the host
+host_inst_rate 1394951 # Simulator instruction rate (inst/s)
+host_op_rate 1394952 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1951161352 # Simulator tick rate (ticks/s)
+host_mem_usage 227304 # Number of bytes of host memory used
+host_seconds 138.67 # Real time elapsed on the host
sim_insts 193444531 # Number of instructions simulated
sim_ops 193444769 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read 331072 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 230208 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 0 # Number of bytes written to this memory
-system.physmem.num_reads 5173 # Number of read requests responded to by this memory
-system.physmem.num_writes 0 # Number of write requests responded to by this memory
-system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 1223578 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 850804 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total 1223578 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory
+system.physmem.bytes_read::total 331072 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 230208 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 230208 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 3597 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1576 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 5173 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 850804 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 372774 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1223578 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 850804 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 850804 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 850804 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 372774 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1223578 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 401 # Number of system calls
system.cpu.numCycles 541153920 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
@@ -77,11 +84,17 @@ system.cpu.icache.demand_accesses::total 193445549 # nu
system.cpu.icache.overall_accesses::cpu.inst 193445549 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 193445549 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000064 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.000064 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26294.433594 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 26294.433594 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 26294.433594 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 26294.433594 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 26294.433594 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 26294.433594 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -103,11 +116,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 286242000
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 286242000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 286242000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000064 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23294.433594 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23294.433594 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23294.433594 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23294.433594 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2 # number of replacements
system.cpu.dcache.tagsinuse 1237.197455 # Cycle average of tags in use
@@ -159,15 +178,25 @@ system.cpu.dcache.demand_accesses::total 76711508 # nu
system.cpu.dcache.overall_accesses::cpu.data 76711508 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 76711508 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000009 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000057 # miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000045 # miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_miss_rate::total 0.000045 # miss rate for SwapReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 56000 # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::total 56000 # average SwapReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -199,15 +228,25 @@ system.cpu.dcache.demand_mshr_miss_latency::total 83475000
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 83475000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 83475000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000057 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000045 # mshr miss rate for SwapReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 53000 # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 53000 # average SwapReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 2678.327135 # Cycle average of tags in use
@@ -267,18 +306,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 1576
system.cpu.l2cache.overall_accesses::total 13864 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.292725 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.320272 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.292725 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.373125 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.292725 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.373125 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -311,18 +358,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 63040000
system.cpu.l2cache.overall_mshr_miss_latency::total 206920000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.320272 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.373125 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------