stats: update stats for no_value -> nan

Lots of accumulated older changes too.

6 files changed, 56 insertions, 46 deletions

diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
index bf42eae33..b2ac1c016 100644
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -39,6 +38,7 @@ do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -57,8 +57,8 @@ system=system
 tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
-dcache_port=system.membus.port[3]
-icache_port=system.membus.port[2]
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
 
 [system.cpu.dtb]
 type=SparcTLB
@@ -77,7 +77,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-atomic
+cwd=build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -101,15 +101,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout
index 288eec929..fe38fbd1a 100755
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout
@@ -1,10 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:08:33
-gem5 started Feb 11 2012 14:01:49
-gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-atomic
+gem5 compiled May  8 2012 15:05:42
+gem5 started May  8 2012 15:47:40
+gem5 executing on piton
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic
+Couldn't unlink  build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sav
+Couldn't unlink  build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
index acb9c3a66..417f58ce8 100644
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.096723                       # Nu
 sim_ticks                                 96722951500                       # Number of ticks simulated
 final_tick                                96722951500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                4190258                       # Simulator instruction rate (inst/s)
-host_op_rate                                  4190262                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2095142285                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 207744                       # Number of bytes of host memory used
-host_seconds                                    46.17                       # Real time elapsed on the host
+host_inst_rate                                1581365                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1581366                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              790687708                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 217932                       # Number of bytes of host memory used
+host_seconds                                   122.33                       # Real time elapsed on the host
 sim_insts                                   193444531                       # Number of instructions simulated
 sim_ops                                     193444769                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                   997245606                       # Number of bytes read from this memory
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
index 4355111bc..af9f6c271 100644
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
@@ -16,7 +16,6 @@ load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
-physmem=system.physmem
 readfile=
 symbolfile=
 work_begin_ckpt_count=0
@@ -26,7 +25,7 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -80,7 +79,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=SparcTLB
@@ -88,7 +87,7 @@ size=64
 
 [system.cpu.icache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -109,7 +108,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=SparcInterrupts
@@ -120,7 +119,7 @@ size=64
 
 [system.cpu.l2cache]
 type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
 forward_snoops=true
@@ -140,8 +139,8 @@ tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
 type=Bus
@@ -151,7 +150,8 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -159,7 +159,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing
+cwd=build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -183,15 +183,18 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
-type=PhysicalMemory
+type=SimpleMemory
+conf_table_reported=false
 file=
+in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
 
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout
index cb4fa4440..f7fdf9677 100755
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout
@@ -1,10 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 11 2012 13:08:33
-gem5 started Feb 11 2012 14:02:21
-gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing
+gem5 compiled May  8 2012 15:05:42
+gem5 started May  8 2012 15:49:18
+gem5 executing on piton
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing
+Couldn't unlink  build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sav
+Couldn't unlink  build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
index fba3d7989..415ede7b3 100644
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.270577                       # Nu
 sim_ticks                                270576960000                       # Number of ticks simulated
 final_tick                               270576960000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2083715                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2083717                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2914556895                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 216616                       # Number of bytes of host memory used
-host_seconds                                    92.84                       # Real time elapsed on the host
+host_inst_rate                                 668557                       # Simulator instruction rate (inst/s)
+host_op_rate                                   668558                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              935131366                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 226812                       # Number of bytes of host memory used
+host_seconds                                   289.35                       # Real time elapsed on the host
 sim_insts                                   193444531                       # Number of instructions simulated
 sim_ops                                     193444769                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                      331072                       # Number of bytes read from this memory
@@ -86,8 +86,8 @@ system.cpu.icache.blocked_cycles::no_mshrs            0                       #
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst        12288                       # number of ReadReq MSHR misses
@@ -172,8 +172,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs            0                       #
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks            2                       # number of writebacks
@@ -283,8 +283,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs            0                       #
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3597                       # number of ReadReq MSHR misses