tests: update reference outputs

Apparently only stats.txt was updated the last time, so
this changeset updates other reference output files
(config.ini, simout, simerr, ruby.stats) so that
test output diffs should not be cluttered with irrelevant
changes.  There are a few stats.txt updates too, but
they are in the minority.

2 files changed, 79 insertions, 29 deletions

diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
index 32480c302..078b2c3e8 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,9 +30,14 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=DerivO3CPU
-children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
+children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
 LFSTSize=1024
 LQEntries=32
 LSQCheckLoads=true
@@ -43,7 +49,7 @@ backComSize=5
 branchPred=system.cpu.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -92,6 +98,7 @@ renameToFetchDelay=1
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -113,6 +120,11 @@ workload=system.cpu.workload
 dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
+[system.cpu.apic_clk_domain]
+type=DerivedClockDomain
+clk_divider=16
+clk_domain=system.cpu_clk_domain
+
 [system.cpu.branchPred]
 type=BranchPredictor
 BTBEntries=4096
@@ -121,11 +133,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -133,10 +143,10 @@ predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -147,12 +157,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=X86TLB
 children=walker
@@ -161,7 +180,8 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[3]
 
@@ -430,10 +450,10 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -444,15 +464,24 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=X86LocalApic
-clock=8000
+clk_domain=system.cpu.apic_clk_domain
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -472,16 +501,17 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -492,16 +522,24 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -520,7 +558,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
+executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -531,10 +569,14 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -545,19 +587,24 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -568,6 +615,9 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
index 7157fcc8e..23eb40269 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/s
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 15:13:59
-gem5 started Mar 26 2013 23:44:56
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 06:21:20
+gem5 started Sep 22 2013 06:27:45
+gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
 Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav
 Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2
@@ -26,4 +26,4 @@ info: Increasing stack size by one page.
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 82784332500 because target called exit()
+122 123 124 Exiting @ tick 144470654000 because target called exit()