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author | Andreas Hansson <andreas.hansson@arm.com> | 2013-05-30 12:54:18 -0400 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-05-30 12:54:18 -0400 |
commit | 74553c7d3fc5430752c0c08f2b319a99fb7ed632 (patch) | |
tree | 79b2a309fff0edaf1ef3e9aa62656904c3351650 /tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt | |
parent | 3bc4ecdcb4785a976a1c3fd463bf7052b8415d8b (diff) | |
download | gem5-74553c7d3fc5430752c0c08f2b319a99fb7ed632.tar.xz |
stats: Update the stats to reflect bus and memory changes
This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.
Diffstat (limited to 'tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt')
-rw-r--r-- | tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index cfc0b5abb..de904232a 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -27,6 +27,25 @@ system.physmem.bw_inst_read::total 724276 # In system.physmem.bw_total::cpu.inst 724276 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 483276 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1207552 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 1207552 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3160 # Transaction distribution +system.membus.trans_dist::ReadResp 3160 # Transaction distribution +system.membus.trans_dist::ReadExReq 1575 # Transaction distribution +system.membus.trans_dist::ReadExResp 1575 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 9470 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 303040 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 4753500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 42633500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.workload.num_syscalls 400 # Number of system calls system.cpu.numCycles 501907914 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -364,5 +383,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 52780.314961 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 1684707 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 5021 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 7 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1578 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 9388 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3817 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 13205 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 300416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 122368 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 422784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 422784 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3310000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 7041000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |