diff options
author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
---|---|---|
committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
commit | 4f8d1a4cef2b23b423ea083078cd933c66c88e2a (patch) | |
tree | c6d7d7567ead8bc2fe34bbf35604cc10d50dd72c /tests/long/se/70.twolf/ref/x86/linux/simple-timing | |
parent | 542d0ceebca1d24bfb433ce9fe916b0586f8d029 (diff) | |
download | gem5-4f8d1a4cef2b23b423ea083078cd933c66c88e2a.tar.xz |
stats: update stats for insts/ops and master id changes
Diffstat (limited to 'tests/long/se/70.twolf/ref/x86/linux/simple-timing')
3 files changed, 281 insertions, 187 deletions
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini index d7a510398..62a1aa7b0 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -81,7 +84,14 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] type=X86TLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.toL2Bus.port[3] [system.cpu.icache] type=BaseCache @@ -94,20 +104,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,9 +118,25 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_port=system.membus.port[4] +pio=system.membus.port[3] + [system.cpu.itb] type=X86TLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.toL2Bus.port[2] [system.cpu.l2cache] type=BaseCache @@ -130,25 +149,18 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] +cpu_side=system.cpu.toL2Bus.port[4] mem_side=system.membus.port[2] [system.cpu.toL2Bus] @@ -159,7 +171,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side [system.cpu.tracer] type=ExeTracer @@ -167,7 +179,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing +cwd=build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing egid=100 env= errout=cerr @@ -191,7 +203,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port [system.physmem] type=PhysicalMemory diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout index a3170a407..fff65e67f 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:08:34 -gem5 started Jan 23 2012 08:26:06 +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 15:28:59 gem5 executing on zizzer -command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sav -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sv2 +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index 1c9d2c1e6..6e3725588 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.250961 # Nu sim_ticks 250960631000 # Number of ticks simulated final_tick 250960631000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1263573 # Simulator instruction rate (inst/s) -host_tick_rate 1432520595 # Simulator tick rate (ticks/s) -host_mem_usage 220856 # Number of bytes of host memory used -host_seconds 175.19 # Real time elapsed on the host -sim_insts 221363018 # Number of instructions simulated +host_inst_rate 1043901 # Simulator instruction rate (inst/s) +host_op_rate 1749670 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1983612036 # Simulator tick rate (ticks/s) +host_mem_usage 226268 # Number of bytes of host memory used +host_seconds 126.52 # Real time elapsed on the host +sim_insts 132071228 # Number of instructions simulated +sim_ops 221363018 # Number of ops (including micro ops) simulated system.physmem.bytes_read 303040 # Number of bytes read from this memory system.physmem.bytes_inst_read 181760 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -22,7 +24,8 @@ system.cpu.workload.num_syscalls 400 # Nu system.cpu.numCycles 501921262 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 221363018 # Number of instructions executed +system.cpu.committedInsts 132071228 # Number of instructions committed +system.cpu.committedOps 221363018 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured @@ -46,26 +49,39 @@ system.cpu.icache.total_refs 173489718 # To system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 36959.888794 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1455.289108 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.710590 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 173489718 # number of ReadReq hits -system.cpu.icache.demand_hits 173489718 # number of demand (read+write) hits -system.cpu.icache.overall_hits 173489718 # number of overall hits -system.cpu.icache.ReadReq_misses 4694 # number of ReadReq misses -system.cpu.icache.demand_misses 4694 # number of demand (read+write) misses -system.cpu.icache.overall_misses 4694 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 185041500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 185041500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 185041500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 173494412 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 173494412 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 173494412 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000027 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000027 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 39420.856412 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 39420.856412 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 39420.856412 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1455.289108 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.710590 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.710590 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 173489718 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 173489718 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 173489718 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 173489718 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 173489718 # number of overall hits +system.cpu.icache.overall_hits::total 173489718 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4694 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4694 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4694 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses +system.cpu.icache.overall_misses::total 4694 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 185041500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 185041500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 185041500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 185041500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 185041500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 185041500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 173494412 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 173494412 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 173494412 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 173494412 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 173494412 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 173494412 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39420.856412 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 39420.856412 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 39420.856412 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -74,26 +90,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 4694 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 4694 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 4694 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 170928000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 170928000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 170928000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000027 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000027 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000027 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 36414.145718 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4694 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4694 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4694 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170928000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 170928000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170928000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 170928000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170928000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 170928000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36414.145718 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36414.145718 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.145718 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 41 # number of replacements system.cpu.dcache.tagsinuse 1363.451495 # Cycle average of tags in use @@ -101,32 +115,49 @@ system.cpu.dcache.total_refs 77195833 # To system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 40522.746982 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1363.451495 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.332874 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 56681681 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 20514152 # number of WriteReq hits -system.cpu.dcache.demand_hits 77195833 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 77195833 # number of overall hits -system.cpu.dcache.ReadReq_misses 327 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1578 # number of WriteReq misses -system.cpu.dcache.demand_misses 1905 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1905 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 18020000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 88242000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 106262000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 106262000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 56682008 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 77197738 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 77197738 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000077 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 55107.033639 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 55920.152091 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 55780.577428 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 55780.577428 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 1363.451495 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.332874 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.332874 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 56681681 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 56681681 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20514152 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20514152 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 77195833 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 77195833 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 77195833 # number of overall hits +system.cpu.dcache.overall_hits::total 77195833 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1578 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1905 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses +system.cpu.dcache.overall_misses::total 1905 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18020000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18020000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 88242000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 88242000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 106262000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 106262000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 106262000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 106262000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 56682008 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 56682008 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 77197738 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 77197738 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 77197738 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 77197738 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55107.033639 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55920.152091 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55780.577428 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55780.577428 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -135,30 +166,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 7 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 327 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1578 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1905 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1905 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 17038500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 83508000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 100546500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 100546500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000077 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52105.504587 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52920.152091 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52780.314961 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 52780.314961 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 7 # number of writebacks +system.cpu.dcache.writebacks::total 7 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 327 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 327 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1578 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1578 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1905 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17038500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17038500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83508000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 83508000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 100546500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 100546500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 100546500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 100546500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52105.504587 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52920.152091 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 2058.168190 # Cycle average of tags in use @@ -166,36 +199,75 @@ system.cpu.l2cache.total_refs 1861 # To system.cpu.l2cache.sampled_refs 3164 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.588180 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2058.146434 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 0.021756 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.062810 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000001 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1861 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 7 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 3 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 1864 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1864 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3160 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 1575 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 4735 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 4735 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 164335500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 81900000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 246235500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 246235500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 5021 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 7 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 6599 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 6599 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.629357 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.998099 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.717533 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.717533 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52004.905063 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52003.273495 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52003.273495 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 0.021756 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1829.968899 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 228.177535 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.055846 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.062810 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 1854 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 7 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1861 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 7 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 7 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 3 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 3 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1854 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 10 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1864 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1854 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 10 # number of overall hits +system.cpu.l2cache.overall_hits::total 1864 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2840 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 320 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 3160 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1575 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1575 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2840 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1895 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 4735 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2840 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1895 # number of overall misses +system.cpu.l2cache.overall_misses::total 4735 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 147694000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16641500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 164335500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 81900000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 81900000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 147694000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 98541500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 246235500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 147694000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 98541500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 246235500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 4694 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 327 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 5021 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 7 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 7 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1578 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1578 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 4694 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 6599 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4694 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 6599 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.605028 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.978593 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.998099 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.605028 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.994751 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52004.929577 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52004.687500 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52004.929577 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.791557 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52004.929577 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.791557 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -204,30 +276,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3160 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1575 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 4735 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 4735 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 126400000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 63000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 189400000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 189400000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.629357 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.998099 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.717533 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.717533 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2840 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 320 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3160 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1575 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1575 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2840 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1895 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 4735 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2840 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1895 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4735 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 113600000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12800000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 126400000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63000000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63000000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 113600000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 75800000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 189400000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 113600000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 75800000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 189400000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.978593 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.998099 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |