diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-13 12:30:30 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-13 12:30:30 -0600 |
| commit | 0d46708dc20c438d29bd724fb7d4b54d4d2f318a (patch) | |
| tree | 337e1a7404c57817cd08106a0369542ea5c4ac30 /tests/long/se/70.twolf/ref/x86/linux | |
| parent | 9b05e96b9efdb9cdcc4e40ef9c96b1228df7a175 (diff) | |
| download | gem5-0d46708dc20c438d29bd724fb7d4b54d4d2f318a.tar.xz | |
bp: fix up stats for changes to branch predictor
Diffstat (limited to 'tests/long/se/70.twolf/ref/x86/linux')
| -rwxr-xr-x | tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout | 8 | ||||
| -rw-r--r-- | tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt | 964 |
2 files changed, 487 insertions, 485 deletions
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout index 99b3e7f21..138f6116a 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:53 -gem5 started Feb 11 2012 15:02:46 +gem5 compiled Feb 12 2012 17:18:12 +gem5 started Feb 12 2012 19:27:36 gem5 executing on zizzer command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing +Couldn't unlink build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing/smred.sav +Couldn't unlink build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -22,4 +24,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 96266258000 because target called exit() +122 123 124 Exiting @ tick 87727531000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 0aeabdea4..7c2d38b1f 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,264 +1,264 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.096266 # Number of seconds simulated -sim_ticks 96266258000 # Number of ticks simulated -final_tick 96266258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.087728 # Number of seconds simulated +sim_ticks 87727531000 # Number of ticks simulated +final_tick 87727531000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 89516 # Simulator instruction rate (inst/s) -host_op_rate 150037 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 65247901 # Simulator tick rate (ticks/s) -host_mem_usage 229524 # Number of bytes of host memory used -host_seconds 1475.39 # Real time elapsed on the host +host_inst_rate 101058 # Simulator instruction rate (inst/s) +host_op_rate 169383 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67127344 # Simulator tick rate (ticks/s) +host_mem_usage 229892 # Number of bytes of host memory used +host_seconds 1306.88 # Real time elapsed on the host sim_insts 132071227 # Number of instructions simulated sim_ops 221363017 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 339712 # Number of bytes read from this memory -system.physmem.bytes_inst_read 214912 # Number of instructions bytes read from this memory +system.physmem.bytes_read 345792 # Number of bytes read from this memory +system.physmem.bytes_inst_read 220224 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 5308 # Number of read requests responded to by this memory +system.physmem.num_reads 5403 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 3528879 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 2232475 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 3528879 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 3941659 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 2510318 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 3941659 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 192532517 # number of cpu cycles simulated +system.cpu.numCycles 175455063 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 25728486 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 25728486 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2892788 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 23533152 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 20839978 # Number of BTB hits +system.cpu.BPredUnit.lookups 20916443 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 20916443 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2209285 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 15543482 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 13847483 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 30657479 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 260466955 # Number of instructions fetch has processed -system.cpu.fetch.Branches 25728486 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 20839978 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 70644215 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 26785814 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 67566342 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 136 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1120 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 28758661 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 555177 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 192452166 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.262310 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.335029 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27331578 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 227091825 # Number of instructions fetch has processed +system.cpu.fetch.Branches 20916443 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13847483 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 59872682 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 19479342 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 71171142 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1142 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9711 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 25826236 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 465691 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 175377754 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.138493 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.301400 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 123644733 64.25% 64.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4091160 2.13% 66.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3200074 1.66% 68.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4567374 2.37% 70.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4265123 2.22% 72.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4442159 2.31% 74.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5459285 2.84% 77.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3091960 1.61% 79.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 39690298 20.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 117181647 66.82% 66.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3214918 1.83% 68.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2487615 1.42% 70.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3152390 1.80% 71.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3541045 2.02% 73.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3761465 2.14% 76.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4534795 2.59% 78.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2814480 1.60% 80.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 34689399 19.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 192452166 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.133632 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.352847 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 44411978 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 57625858 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 56973408 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9858048 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 23582874 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 423042956 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 23582874 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 52998252 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14705836 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 23082 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 57546904 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 43595218 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 410638323 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 18885984 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22330558 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 437009036 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1063910767 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1053088723 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10822044 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 175377754 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.119213 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.294302 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 40655078 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 60979767 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 46580847 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10170563 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 16991499 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 366154541 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 16991499 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 48551575 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 16255360 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 22908 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 48159937 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 45396475 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 356930622 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 31 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 20611614 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22556100 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 370578330 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 915376002 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 905357204 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10018798 # Number of floating rename lookups system.cpu.rename.CommittedMaps 234363409 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 202645627 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1783 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1777 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 94569707 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 103994638 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 37171273 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 66711674 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 21456392 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 395555693 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2683 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 287296212 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 238230 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 173600960 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 348497721 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1437 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 192452166 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.492819 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.482262 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 136214921 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1884 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1879 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 95075204 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89798900 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 33126150 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 59105892 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 19470251 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 344622515 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 7679 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 271009025 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 252543 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 122771831 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 234148079 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 6433 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 175377754 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.545287 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.468253 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 60170871 31.27% 31.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 53695201 27.90% 59.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 36000837 18.71% 77.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20815986 10.82% 88.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 13514067 7.02% 95.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 5325466 2.77% 98.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2181156 1.13% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 607811 0.32% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 140771 0.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 49123743 28.01% 28.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 52511910 29.94% 57.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 34319849 19.57% 77.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19020528 10.85% 88.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12714994 7.25% 95.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4949443 2.82% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2083502 1.19% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 542650 0.31% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 111135 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 192452166 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 175377754 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 103783 3.80% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2313613 84.82% 88.62% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 310319 11.38% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 91290 3.51% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2230006 85.80% 89.31% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 277845 10.69% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1202882 0.42% 0.42% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 186701896 64.99% 65.40% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.40% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1648118 0.57% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 73212241 25.48% 91.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 24531075 8.54% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1212979 0.45% 0.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 176351426 65.07% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1596977 0.59% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 68342169 25.22% 91.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 23505474 8.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 287296212 # Type of FU issued -system.cpu.iq.rate 1.492196 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2727715 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009494 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 764505561 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 564134434 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 277997574 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5504974 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 5363501 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2644368 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 286052729 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2768316 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18967849 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 271009025 # Type of FU issued +system.cpu.iq.rate 1.544606 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2599141 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009591 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 714934206 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 462829464 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 263397424 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 5313282 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4873666 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2553131 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 269732632 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2662555 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18949841 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 47345048 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 33748 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 344727 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16655557 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 33149310 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 29835 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 306343 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12610434 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 48770 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 47714 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 23582874 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 506702 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 199063 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 395558376 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 136305 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 103994638 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 37171273 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1768 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 106766 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 14420 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 344727 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2499729 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 593078 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3092807 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 283409034 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 71642320 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3887178 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 16991499 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 515293 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 247384 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 344630194 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 299081 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 89798900 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 33126150 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1841 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 161274 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 32917 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 306343 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1299828 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1028827 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2328655 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 267903545 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 67266011 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3105480 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 95673519 # number of memory reference insts executed -system.cpu.iew.exec_branches 15642768 # Number of branches executed -system.cpu.iew.exec_stores 24031199 # Number of stores executed -system.cpu.iew.exec_rate 1.472006 # Inst execution rate -system.cpu.iew.wb_sent 281921944 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 280641942 # cumulative count of insts written-back -system.cpu.iew.wb_producers 227553614 # num instructions producing a value -system.cpu.iew.wb_consumers 378165457 # num instructions consuming a value +system.cpu.iew.exec_refs 90381113 # number of memory reference insts executed +system.cpu.iew.exec_branches 14784987 # Number of branches executed +system.cpu.iew.exec_stores 23115102 # Number of stores executed +system.cpu.iew.exec_rate 1.526907 # Inst execution rate +system.cpu.iew.wb_sent 266831657 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 265950555 # cumulative count of insts written-back +system.cpu.iew.wb_producers 214539100 # num instructions producing a value +system.cpu.iew.wb_consumers 362277288 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.457634 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.601730 # average fanout of values written-back +system.cpu.iew.wb_rate 1.515776 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.592196 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 132071227 # The number of committed instructions system.cpu.commit.commitCommittedOps 221363017 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 174222633 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 123379420 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2892920 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 168869292 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.310854 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.745147 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2210265 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158386255 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.397615 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.796088 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 63124360 37.38% 37.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 62150025 36.80% 74.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15630374 9.26% 83.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11975959 7.09% 90.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 5416595 3.21% 93.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2994905 1.77% 95.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2021663 1.20% 96.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1189804 0.70% 97.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4365607 2.59% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 54200924 34.22% 34.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 60421756 38.15% 72.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15533803 9.81% 82.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12711410 8.03% 90.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4532649 2.86% 93.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2958963 1.87% 94.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2077692 1.31% 96.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1244602 0.79% 97.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4704456 2.97% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 168869292 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 158386255 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071227 # Number of instructions committed system.cpu.commit.committedOps 221363017 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -269,64 +269,64 @@ system.cpu.commit.branches 12326943 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339606 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4365607 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4704456 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 560089335 # The number of ROB reads -system.cpu.rob.rob_writes 814800236 # The number of ROB writes -system.cpu.timesIdled 1747 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 80351 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 498424236 # The number of ROB reads +system.cpu.rob.rob_writes 706514017 # The number of ROB writes +system.cpu.timesIdled 1681 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 77309 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071227 # Number of Instructions Simulated system.cpu.committedOps 221363017 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071227 # Number of Instructions Simulated -system.cpu.cpi 1.457793 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.457793 # CPI: Total CPI of All Threads -system.cpu.ipc 0.685968 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.685968 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 530367480 # number of integer regfile reads -system.cpu.int_regfile_writes 288604591 # number of integer regfile writes -system.cpu.fp_regfile_reads 3608788 # number of floating regfile reads -system.cpu.fp_regfile_writes 2298113 # number of floating regfile writes -system.cpu.misc_regfile_reads 149639402 # number of misc regfile reads +system.cpu.cpi 1.328488 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.328488 # CPI: Total CPI of All Threads +system.cpu.ipc 0.752735 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.752735 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 511675262 # number of integer regfile reads +system.cpu.int_regfile_writes 274174484 # number of integer regfile writes +system.cpu.fp_regfile_reads 3515494 # number of floating regfile reads +system.cpu.fp_regfile_writes 2227241 # number of floating regfile writes +system.cpu.misc_regfile_reads 139504609 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.icache.replacements 4205 # number of replacements -system.cpu.icache.tagsinuse 1597.649860 # Cycle average of tags in use -system.cpu.icache.total_refs 28751182 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 6167 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4662.101832 # Average number of references to valid blocks. +system.cpu.icache.replacements 5602 # number of replacements +system.cpu.icache.tagsinuse 1631.479553 # Cycle average of tags in use +system.cpu.icache.total_refs 25817139 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7573 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 3409.103262 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1597.649860 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.780102 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.780102 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 28751182 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 28751182 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 28751182 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 28751182 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 28751182 # number of overall hits -system.cpu.icache.overall_hits::total 28751182 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 7479 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 7479 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 7479 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 7479 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 7479 # number of overall misses -system.cpu.icache.overall_misses::total 7479 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 173725000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 173725000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 173725000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 173725000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 173725000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 173725000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 28758661 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 28758661 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 28758661 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 28758661 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 28758661 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 28758661 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000260 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000260 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000260 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23228.372777 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23228.372777 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23228.372777 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1631.479553 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.796621 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.796621 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25817139 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25817139 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25817139 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25817139 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25817139 # number of overall hits +system.cpu.icache.overall_hits::total 25817139 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 9097 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 9097 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 9097 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 9097 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 9097 # number of overall misses +system.cpu.icache.overall_misses::total 9097 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 188035000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 188035000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 188035000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 188035000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 188035000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 188035000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25826236 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25826236 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25826236 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25826236 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25826236 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25826236 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000352 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000352 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000352 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20670.001099 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20670.001099 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20670.001099 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -335,80 +335,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1119 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1119 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1119 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1119 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1119 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1119 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6360 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 6360 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 6360 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6360 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6360 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6360 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 125233500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 125233500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 125233500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 125233500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 125233500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 125233500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000221 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000221 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000221 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19690.801887 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19690.801887 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19690.801887 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1378 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1378 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1378 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1378 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1378 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1378 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7719 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 7719 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 7719 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 7719 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 7719 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 7719 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 130954500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 130954500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 130954500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 130954500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 130954500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 130954500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16965.215702 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16965.215702 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16965.215702 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 56 # number of replacements -system.cpu.dcache.tagsinuse 1415.486536 # Cycle average of tags in use -system.cpu.dcache.total_refs 72938173 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1987 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 36707.686462 # Average number of references to valid blocks. +system.cpu.dcache.replacements 54 # number of replacements +system.cpu.dcache.tagsinuse 1429.840369 # Cycle average of tags in use +system.cpu.dcache.total_refs 68659767 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1998 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34364.247748 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1415.486536 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.345578 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.345578 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 52423955 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 52423955 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513973 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513973 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 72937928 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 72937928 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 72937928 # number of overall hits -system.cpu.dcache.overall_hits::total 72937928 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 771 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 771 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1757 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1757 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2528 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2528 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2528 # number of overall misses -system.cpu.dcache.overall_misses::total 2528 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24605500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24605500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 66582500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 66582500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 91188000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 91188000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 91188000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 91188000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 52424726 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 52424726 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 1429.840369 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.349082 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.349082 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 48145557 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 48145557 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20514023 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20514023 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 68659580 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 68659580 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 68659580 # number of overall hits +system.cpu.dcache.overall_hits::total 68659580 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 765 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 765 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1707 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1707 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2472 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2472 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2472 # number of overall misses +system.cpu.dcache.overall_misses::total 2472 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24609000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24609000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 64758500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 64758500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 89367500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 89367500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 89367500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 89367500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 48146322 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 48146322 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 72940456 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 72940456 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 72940456 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 72940456 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000015 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000086 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000035 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000035 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31913.748379 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37895.560615 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36071.202532 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36071.202532 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 68662052 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 68662052 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 68662052 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 68662052 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000016 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000083 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000036 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000036 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32168.627451 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37937.024019 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36151.901294 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36151.901294 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -419,119 +419,119 @@ system.cpu.dcache.fast_writes 0 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 167607000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106751500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 60855500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 167607000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.454377 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.931973 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994882 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.544511 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980392 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.544511 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980392 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31023.079214 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30982.278481 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994869 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.454377 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.981000 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.454377 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.981000 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31023.394362 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31006.082725 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31017.684887 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31023.079214 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31010.512821 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31023.079214 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31010.512821 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31019.987105 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31023.394362 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31017.074414 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31023.394362 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31017.074414 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |