diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
| commit | 4f8d1a4cef2b23b423ea083078cd933c66c88e2a (patch) | |
| tree | c6d7d7567ead8bc2fe34bbf35604cc10d50dd72c /tests/long/se/70.twolf/ref/x86/linux | |
| parent | 542d0ceebca1d24bfb433ce9fe916b0586f8d029 (diff) | |
| download | gem5-4f8d1a4cef2b23b423ea083078cd933c66c88e2a.tar.xz | |
stats: update stats for insts/ops and master id changes
Diffstat (limited to 'tests/long/se/70.twolf/ref/x86/linux')
9 files changed, 609 insertions, 405 deletions
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini index 9f72e3b54..82a282d96 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -136,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -442,20 +435,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -494,20 +480,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -531,12 +510,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing +cwd=build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf +executable=/dist/m5/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout index 0b6a80ec2..99b3e7f21 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout @@ -1,14 +1,10 @@ -Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 9 2012 12:45:55 -gem5 started Feb 9 2012 12:46:40 -gem5 executing on ribera.cs.wisc.edu -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2 +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 15:02:46 +gem5 executing on zizzer +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 2a68affc2..0aeabdea4 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.096266 # Nu sim_ticks 96266258000 # Number of ticks simulated final_tick 96266258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 60515 # Simulator instruction rate (inst/s) -host_tick_rate 26316743 # Simulator tick rate (ticks/s) -host_mem_usage 262352 # Number of bytes of host memory used -host_seconds 3657.99 # Real time elapsed on the host -sim_insts 221363017 # Number of instructions simulated +host_inst_rate 89516 # Simulator instruction rate (inst/s) +host_op_rate 150037 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 65247901 # Simulator tick rate (ticks/s) +host_mem_usage 229524 # Number of bytes of host memory used +host_seconds 1475.39 # Real time elapsed on the host +sim_insts 132071227 # Number of instructions simulated +sim_ops 221363017 # Number of ops (including micro ops) simulated system.physmem.bytes_read 339712 # Number of bytes read from this memory system.physmem.bytes_inst_read 214912 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -235,7 +237,8 @@ system.cpu.iew.wb_penalized 0 # nu system.cpu.iew.wb_rate 1.457634 # insts written-back per cycle system.cpu.iew.wb_fanout 0.601730 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions +system.cpu.commit.commitCommittedInsts 132071227 # The number of committed instructions +system.cpu.commit.commitCommittedOps 221363017 # The number of committed instructions system.cpu.commit.commitSquashedInsts 174222633 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 2892920 # The number of times a branch was mispredicted @@ -256,7 +259,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 168869292 # Number of insts commited each cycle -system.cpu.commit.count 221363017 # Number of instructions committed +system.cpu.commit.committedInsts 132071227 # Number of instructions committed +system.cpu.commit.committedOps 221363017 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 77165306 # Number of memory references committed system.cpu.commit.loads 56649590 # Number of loads committed @@ -271,12 +275,13 @@ system.cpu.rob.rob_reads 560089335 # Th system.cpu.rob.rob_writes 814800236 # The number of ROB writes system.cpu.timesIdled 1747 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 80351 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 221363017 # Number of Instructions Simulated -system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated -system.cpu.cpi 0.869759 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.869759 # CPI: Total CPI of All Threads -system.cpu.ipc 1.149744 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.149744 # IPC: Total IPC of All Threads +system.cpu.committedInsts 132071227 # Number of Instructions Simulated +system.cpu.committedOps 221363017 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 132071227 # Number of Instructions Simulated +system.cpu.cpi 1.457793 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.457793 # CPI: Total CPI of All Threads +system.cpu.ipc 0.685968 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.685968 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 530367480 # number of integer regfile reads system.cpu.int_regfile_writes 288604591 # number of integer regfile writes system.cpu.fp_regfile_reads 3608788 # number of floating regfile reads @@ -289,26 +294,39 @@ system.cpu.icache.total_refs 28751182 # To system.cpu.icache.sampled_refs 6167 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 4662.101832 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1597.649860 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.780102 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 28751182 # number of ReadReq hits -system.cpu.icache.demand_hits 28751182 # number of demand (read+write) hits -system.cpu.icache.overall_hits 28751182 # number of overall hits -system.cpu.icache.ReadReq_misses 7479 # number of ReadReq misses -system.cpu.icache.demand_misses 7479 # number of demand (read+write) misses -system.cpu.icache.overall_misses 7479 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 173725000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 173725000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 173725000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 28758661 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 28758661 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 28758661 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000260 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000260 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000260 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 23228.372777 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 23228.372777 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 23228.372777 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1597.649860 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.780102 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.780102 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 28751182 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 28751182 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 28751182 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 28751182 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 28751182 # number of overall hits +system.cpu.icache.overall_hits::total 28751182 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 7479 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 7479 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 7479 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 7479 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 7479 # number of overall misses +system.cpu.icache.overall_misses::total 7479 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 173725000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 173725000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 173725000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 173725000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 173725000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 173725000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 28758661 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 28758661 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 28758661 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 28758661 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 28758661 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 28758661 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000260 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000260 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000260 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23228.372777 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23228.372777 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23228.372777 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -317,27 +335,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1119 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1119 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1119 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 6360 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 6360 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 6360 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 125233500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 125233500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 125233500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000221 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000221 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000221 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 19690.801887 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 19690.801887 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 19690.801887 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1119 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1119 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1119 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1119 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1119 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1119 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6360 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 6360 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 6360 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 6360 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 6360 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 6360 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 125233500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 125233500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 125233500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 125233500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 125233500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 125233500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000221 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000221 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000221 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19690.801887 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19690.801887 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19690.801887 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 56 # number of replacements system.cpu.dcache.tagsinuse 1415.486536 # Cycle average of tags in use @@ -345,32 +366,49 @@ system.cpu.dcache.total_refs 72938173 # To system.cpu.dcache.sampled_refs 1987 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 36707.686462 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1415.486536 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.345578 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 52423955 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 20513973 # number of WriteReq hits -system.cpu.dcache.demand_hits 72937928 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 72937928 # number of overall hits -system.cpu.dcache.ReadReq_misses 771 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1757 # number of WriteReq misses -system.cpu.dcache.demand_misses 2528 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2528 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 24605500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 66582500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 91188000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 91188000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 52424726 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 72940456 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 72940456 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000015 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000086 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000035 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000035 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 31913.748379 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 37895.560615 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 36071.202532 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 36071.202532 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 1415.486536 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.345578 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.345578 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 52423955 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 52423955 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513973 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513973 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 72937928 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 72937928 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 72937928 # number of overall hits +system.cpu.dcache.overall_hits::total 72937928 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 771 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 771 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1757 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1757 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2528 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2528 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2528 # number of overall misses +system.cpu.dcache.overall_misses::total 2528 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24605500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24605500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 66582500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 66582500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 91188000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 91188000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 91188000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 91188000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 52424726 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 52424726 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 72940456 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 72940456 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 72940456 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 72940456 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000015 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000086 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000035 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000035 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31913.748379 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37895.560615 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36071.202532 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36071.202532 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -379,32 +417,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 13 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 344 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 2 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 346 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 346 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 427 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1755 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2182 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2182 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 14039500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 61244500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 75284000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 75284000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000086 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000030 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000030 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32879.391101 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34897.150997 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34502.291476 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34502.291476 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 13 # number of writebacks +system.cpu.dcache.writebacks::total 13 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 344 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 344 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 346 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 346 # 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Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 1.944495 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.076138 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000059 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 2840 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 13 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 8 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 2848 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 2848 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3753 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 193 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 1555 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 5308 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 5308 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 128533500 # 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miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.650809 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.650809 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34248.201439 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34126.366559 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34212.509420 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34212.509420 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 1.944495 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2209.976363 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 284.903826 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000059 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.067443 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.008695 # 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number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1989 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 8156 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 6167 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1989 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 8156 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.544511 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.927230 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994882 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.544511 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.980392 # 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number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -453,34 +540,48 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3753 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 193 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1555 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 5308 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 5308 # 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number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3753 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 193 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 193 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1555 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1555 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3358 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1950 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5308 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3358 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1950 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5308 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104175500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12238000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 116413500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5983000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5983000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48232500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48232500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104175500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 60470500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 164646000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104175500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 60470500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 164646000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.544511 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.927230 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994882 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.544511 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980392 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.544511 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980392 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31023.079214 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30982.278481 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31017.684887 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31023.079214 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31010.512821 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31023.079214 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31010.512821 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini index 4d9868de9..1355f971a 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -52,11 +62,34 @@ icache_port=system.membus.port[2] [system.cpu.dtb] type=X86TLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +system=system +port=system.membus.port[5] + +[system.cpu.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_port=system.membus.port[7] +pio=system.membus.port[6] [system.cpu.itb] type=X86TLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +system=system +port=system.membus.port[4] [system.cpu.tracer] type=ExeTracer @@ -64,7 +97,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic +cwd=build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-atomic egid=100 env= errout=cerr @@ -88,7 +121,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port [system.physmem] type=PhysicalMemory diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout index 3217ab200..d61c2b9aa 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:08:34 -gem5 started Jan 23 2012 08:24:02 +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 15:27:33 gem5 executing on zizzer -command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sav -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sv2 +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt index 39967f660..0e7ef2e19 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.131393 # Nu sim_ticks 131393100000 # Number of ticks simulated final_tick 131393100000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1953897 # Simulator instruction rate (inst/s) -host_tick_rate 1159762651 # Simulator tick rate (ticks/s) -host_mem_usage 211876 # Number of bytes of host memory used -host_seconds 113.29 # Real time elapsed on the host -sim_insts 221363018 # Number of instructions simulated +host_inst_rate 1741959 # Simulator instruction rate (inst/s) +host_op_rate 2919677 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1733014386 # Simulator tick rate (ticks/s) +host_mem_usage 217356 # Number of bytes of host memory used +host_seconds 75.82 # Real time elapsed on the host +sim_insts 132071228 # Number of instructions simulated +sim_ops 221363018 # Number of ops (including micro ops) simulated system.physmem.bytes_read 1698379042 # Number of bytes read from this memory system.physmem.bytes_inst_read 1387955288 # Number of instructions bytes read from this memory system.physmem.bytes_written 99822189 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 400 # Nu system.cpu.numCycles 262786201 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 221363018 # Number of instructions executed +system.cpu.committedInsts 132071228 # Number of instructions committed +system.cpu.committedOps 221363018 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini index d7a510398..62a1aa7b0 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -81,7 +84,14 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] type=X86TLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.toL2Bus.port[3] [system.cpu.icache] type=BaseCache @@ -94,20 +104,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,9 +118,25 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_port=system.membus.port[4] +pio=system.membus.port[3] + [system.cpu.itb] type=X86TLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.toL2Bus.port[2] [system.cpu.l2cache] type=BaseCache @@ -130,25 +149,18 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] +cpu_side=system.cpu.toL2Bus.port[4] mem_side=system.membus.port[2] [system.cpu.toL2Bus] @@ -159,7 +171,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side [system.cpu.tracer] type=ExeTracer @@ -167,7 +179,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing +cwd=build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing egid=100 env= errout=cerr @@ -191,7 +203,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port [system.physmem] type=PhysicalMemory diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout index a3170a407..fff65e67f 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:08:34 -gem5 started Jan 23 2012 08:26:06 +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 15:28:59 gem5 executing on zizzer -command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sav -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sv2 +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index 1c9d2c1e6..6e3725588 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.250961 # Nu sim_ticks 250960631000 # Number of ticks simulated final_tick 250960631000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1263573 # Simulator instruction rate (inst/s) -host_tick_rate 1432520595 # Simulator tick rate (ticks/s) -host_mem_usage 220856 # Number of bytes of host memory used -host_seconds 175.19 # Real time elapsed on the host -sim_insts 221363018 # Number of instructions simulated +host_inst_rate 1043901 # Simulator instruction rate (inst/s) +host_op_rate 1749670 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1983612036 # Simulator tick rate (ticks/s) +host_mem_usage 226268 # Number of bytes of host memory used +host_seconds 126.52 # Real time elapsed on the host +sim_insts 132071228 # Number of instructions simulated +sim_ops 221363018 # Number of ops (including micro ops) simulated system.physmem.bytes_read 303040 # Number of bytes read from this memory system.physmem.bytes_inst_read 181760 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -22,7 +24,8 @@ system.cpu.workload.num_syscalls 400 # Nu system.cpu.numCycles 501921262 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 221363018 # Number of instructions executed +system.cpu.committedInsts 132071228 # Number of instructions committed +system.cpu.committedOps 221363018 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured @@ -46,26 +49,39 @@ system.cpu.icache.total_refs 173489718 # To system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 36959.888794 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1455.289108 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.710590 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 173489718 # number of ReadReq hits -system.cpu.icache.demand_hits 173489718 # number of demand (read+write) hits -system.cpu.icache.overall_hits 173489718 # number of overall hits -system.cpu.icache.ReadReq_misses 4694 # number of ReadReq misses -system.cpu.icache.demand_misses 4694 # number of demand (read+write) misses -system.cpu.icache.overall_misses 4694 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 185041500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 185041500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 185041500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 173494412 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 173494412 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 173494412 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000027 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000027 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 39420.856412 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 39420.856412 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 39420.856412 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1455.289108 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.710590 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.710590 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 173489718 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 173489718 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 173489718 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 173489718 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 173489718 # number of overall hits +system.cpu.icache.overall_hits::total 173489718 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4694 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4694 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4694 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses +system.cpu.icache.overall_misses::total 4694 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 185041500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 185041500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 185041500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 185041500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 185041500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 185041500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 173494412 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 173494412 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 173494412 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 173494412 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 173494412 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 173494412 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39420.856412 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 39420.856412 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 39420.856412 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -74,26 +90,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 4694 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 4694 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 4694 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 170928000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 170928000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 170928000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000027 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000027 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000027 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 36414.145718 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4694 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4694 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4694 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170928000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 170928000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170928000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 170928000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170928000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 170928000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36414.145718 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36414.145718 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.145718 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 41 # number of replacements system.cpu.dcache.tagsinuse 1363.451495 # Cycle average of tags in use @@ -101,32 +115,49 @@ system.cpu.dcache.total_refs 77195833 # To system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 40522.746982 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1363.451495 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.332874 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 56681681 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 20514152 # number of WriteReq hits -system.cpu.dcache.demand_hits 77195833 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 77195833 # number of overall hits -system.cpu.dcache.ReadReq_misses 327 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1578 # number of WriteReq misses -system.cpu.dcache.demand_misses 1905 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1905 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 18020000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 88242000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 106262000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 106262000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 56682008 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 77197738 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 77197738 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000077 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 55107.033639 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 55920.152091 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 55780.577428 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 55780.577428 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 1363.451495 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.332874 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.332874 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 56681681 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 56681681 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20514152 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20514152 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 77195833 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 77195833 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 77195833 # number of overall hits +system.cpu.dcache.overall_hits::total 77195833 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1578 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1905 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses +system.cpu.dcache.overall_misses::total 1905 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18020000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18020000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 88242000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 88242000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 106262000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 106262000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 106262000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 106262000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 56682008 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 56682008 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 77197738 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 77197738 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 77197738 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 77197738 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55107.033639 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55920.152091 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55780.577428 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55780.577428 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -135,30 +166,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 7 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 327 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1578 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1905 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1905 # 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average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52920.152091 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52780.314961 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 52780.314961 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 7 # number of writebacks +system.cpu.dcache.writebacks::total 7 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 327 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 327 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1578 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1578 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1905 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17038500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17038500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83508000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 83508000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 100546500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 100546500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 100546500 # 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number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1864 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3160 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 1575 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 4735 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 4735 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 164335500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 81900000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 246235500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 246235500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 5021 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 7 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 6599 # 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number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1895 # number of overall misses +system.cpu.l2cache.overall_misses::total 4735 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 147694000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16641500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 164335500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 81900000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 81900000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 147694000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 98541500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 246235500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 147694000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 98541500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 246235500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 4694 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 327 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 5021 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 7 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 7 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1578 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1578 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 4694 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 6599 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4694 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 6599 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.605028 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.978593 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.998099 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.605028 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.994751 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52004.929577 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52004.687500 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52004.929577 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.791557 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52004.929577 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.791557 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -204,30 +276,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3160 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1575 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 4735 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 4735 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 126400000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 63000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 189400000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 189400000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.629357 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.998099 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.717533 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.717533 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2840 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 320 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3160 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1575 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1575 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2840 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1895 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 4735 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2840 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1895 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4735 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 113600000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12800000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 126400000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63000000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63000000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 113600000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 75800000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 189400000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 113600000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 75800000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 189400000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.978593 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.998099 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |