diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-25 13:14:42 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-25 13:14:42 -0400 |
| commit | 8fe556338db4cc50a3f1ba20306bc5e464941f2b (patch) | |
| tree | d95b1933c18d142f9c533f32ac7b84bd1f2d0da5 /tests/long/se/70.twolf/ref/x86/linux | |
| parent | 66e331c7bb7d503c35808325e1bfaa9f18f4bdb9 (diff) | |
| download | gem5-8fe556338db4cc50a3f1ba20306bc5e464941f2b.tar.xz | |
stats: Update stats to reflect use of SimpleDRAM
This patch bumps the stats to match the use of SimpleDRAM instead of
SimpleMemory in all inorder and O3 regressions, and also all
full-system regressions. A number of performance-related stats change,
and a whole bunch of stats are added for the memory controller.
Diffstat (limited to 'tests/long/se/70.twolf/ref/x86/linux')
| -rw-r--r-- | tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt | 1197 |
1 files changed, 677 insertions, 520 deletions
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index d3a442923..17b1f3559 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,166 +1,325 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.084599 # Number of seconds simulated -sim_ticks 84599483500 # Number of ticks simulated -final_tick 84599483500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.084594 # Number of seconds simulated +sim_ticks 84594088000 # Number of ticks simulated +final_tick 84594088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 50330 # Simulator instruction rate (inst/s) -host_op_rate 84358 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32239425 # Simulator tick rate (ticks/s) -host_mem_usage 239332 # Number of bytes of host memory used -host_seconds 2624.10 # Real time elapsed on the host +host_inst_rate 94248 # Simulator instruction rate (inst/s) +host_op_rate 157968 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60367706 # Simulator tick rate (ticks/s) +host_mem_usage 238096 # Number of bytes of host memory used +host_seconds 1401.31 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221362960 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 220032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 124672 # Number of bytes read from this memory -system.physmem.bytes_read::total 344704 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 220032 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 220032 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3438 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1948 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5386 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2600867 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1473673 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4074540 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2600867 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2600867 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2600867 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1473673 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4074540 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 220544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 124864 # Number of bytes read from this memory +system.physmem.bytes_read::total 345408 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 220544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 220544 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3446 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1951 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5397 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2607085 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1476037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4083122 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2607085 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2607085 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2607085 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1476037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4083122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5399 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 5664 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 345408 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 345408 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 265 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 309 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 318 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 319 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 318 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 313 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 372 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 333 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 312 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 261 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 280 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 363 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 438 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 441 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 357 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 367 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 298 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 84594067000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 5399 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 265 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 4217 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 943 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 188 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 16379877 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 123109877 # Sum of mem lat for all requests +system.physmem.totBusLat 21596000 # Total cycles spent in databus access +system.physmem.totBankLat 85134000 # Total cycles spent in bank access +system.physmem.avgQLat 3033.87 # Average queueing delay per request +system.physmem.avgBankLat 15768.48 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 22802.35 # Average memory access latency +system.physmem.avgRdBW 4.08 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 4.08 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.00 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 4777 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 88.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 15668469.53 # Average gap between requests system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 169198968 # number of cpu cycles simulated +system.cpu.numCycles 169188177 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 20690463 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 20690463 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2250102 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 15079710 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 13739283 # Number of BTB hits +system.cpu.BPredUnit.lookups 20680258 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 20680258 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2246160 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 15085015 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 13721428 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 27218141 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 227440359 # Number of instructions fetch has processed -system.cpu.fetch.Branches 20690463 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13739283 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 59726319 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 19306281 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 65395131 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 224 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1651 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 25701311 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 473765 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 169122323 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.213301 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.334482 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27164568 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 227213982 # Number of instructions fetch has processed +system.cpu.fetch.Branches 20680258 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13721428 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 59660749 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 19257155 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 65568957 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 236 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1768 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 25653013 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 474244 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 169131808 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.211225 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.333765 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 111062519 65.67% 65.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3230504 1.91% 67.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2469579 1.46% 69.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3091757 1.83% 70.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3527779 2.09% 72.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3730060 2.21% 75.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4582508 2.71% 77.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2803800 1.66% 79.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 34623817 20.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 111136116 65.71% 65.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3216747 1.90% 67.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2468197 1.46% 69.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3082745 1.82% 70.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3525528 2.08% 72.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3731818 2.21% 75.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4565922 2.70% 77.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2807540 1.66% 79.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 34597195 20.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 169122323 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.122285 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.344218 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 40123368 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 55633776 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 46741593 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9842729 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 16780857 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 365282924 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 16780857 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 47679812 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14629061 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 22937 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 48366453 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 41643203 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 356095908 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 40 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 17377193 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22149388 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 410376112 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 987879370 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 977929387 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9949983 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 169131808 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.122232 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.342966 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 40083092 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 55790408 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 46646195 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9876583 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 16735530 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 364948187 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 16735530 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 47642140 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14699446 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 23267 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 48304644 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 41726781 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 355757826 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 35 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 17417112 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22198638 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 51 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 410011414 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 986948203 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 977030227 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9917976 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259428603 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 150947509 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1877 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1873 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 89979833 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 89683170 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 32866708 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 59054771 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 19177166 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 343137266 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5038 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 271920674 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 307949 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 121254430 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 247003349 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3792 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 169122323 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.607834 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.514763 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 150582811 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1844 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1841 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 90083407 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89641616 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 32814586 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 59002795 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 19228439 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 342836678 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4827 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 271794183 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 309279 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 120959244 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 246380396 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3581 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 169131808 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.606996 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.512238 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 47444811 28.05% 28.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 46907027 27.74% 55.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 33033517 19.53% 75.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20154930 11.92% 87.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 13461767 7.96% 95.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4965301 2.94% 98.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2426983 1.44% 99.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 577544 0.34% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 150443 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 47364329 28.00% 28.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 46969212 27.77% 55.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 33133132 19.59% 75.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20170100 11.93% 87.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 13409099 7.93% 95.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4965437 2.94% 98.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2407480 1.42% 99.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 564206 0.33% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 148813 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 169122323 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 169131808 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 134207 5.09% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2238473 84.87% 89.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 264949 10.04% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 133221 5.02% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2254463 85.01% 90.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 264273 9.97% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1212573 0.45% 0.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 177106081 65.13% 65.58% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.58% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1583088 0.58% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1212759 0.45% 0.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 177009113 65.13% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1584136 0.58% 66.16% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.16% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.16% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.16% # Type of FU issued @@ -186,84 +345,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.16% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.16% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.16% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 68507215 25.19% 91.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 23511717 8.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 68507132 25.21% 91.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 23481043 8.64% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 271920674 # Type of FU issued -system.cpu.iq.rate 1.607106 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2637629 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009700 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 710614385 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 460072874 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 264170911 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5294864 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4624558 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2540762 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 270691856 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2653874 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 19027871 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 271794183 # Type of FU issued +system.cpu.iq.rate 1.606461 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2651957 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009757 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 710390564 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 459507075 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 264054683 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 5290846 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4594594 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2539782 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 270581714 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2651667 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 19012084 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 33033584 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 33172 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 306303 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12350992 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 32992030 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 32876 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 306652 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12298870 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 49574 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 49471 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 16780857 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 570141 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 256886 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 343142304 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 262882 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 89683170 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 32866708 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1845 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 170649 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 30071 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 306303 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1331965 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1023841 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2355806 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 268743201 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 67386869 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3177473 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 16735530 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 583808 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 272322 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 342841505 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 257255 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 89641616 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 32814586 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1824 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 184475 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 30365 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 306652 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1330858 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1021453 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2352311 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 268621044 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 67379328 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3173139 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 90490770 # number of memory reference insts executed -system.cpu.iew.exec_branches 14773340 # Number of branches executed -system.cpu.iew.exec_stores 23103901 # Number of stores executed -system.cpu.iew.exec_rate 1.588326 # Inst execution rate -system.cpu.iew.wb_sent 267665043 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 266711673 # cumulative count of insts written-back -system.cpu.iew.wb_producers 215305025 # num instructions producing a value -system.cpu.iew.wb_consumers 378544002 # num instructions consuming a value +system.cpu.iew.exec_refs 90456785 # number of memory reference insts executed +system.cpu.iew.exec_branches 14766526 # Number of branches executed +system.cpu.iew.exec_stores 23077457 # Number of stores executed +system.cpu.iew.exec_rate 1.587706 # Inst execution rate +system.cpu.iew.wb_sent 267534302 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 266594465 # cumulative count of insts written-back +system.cpu.iew.wb_producers 215217179 # num instructions producing a value +system.cpu.iew.wb_consumers 378376353 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.576320 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.568771 # average fanout of values written-back +system.cpu.iew.wb_rate 1.575728 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.568791 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 121862932 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 121559121 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2250269 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 152341466 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.453071 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.928588 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2246323 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 152396278 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.452548 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.926116 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 52729760 34.61% 34.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57497101 37.74% 72.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14043120 9.22% 81.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11929275 7.83% 89.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4291590 2.82% 92.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2949185 1.94% 94.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1071112 0.70% 94.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 989747 0.65% 95.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6840576 4.49% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 52678390 34.57% 34.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57577424 37.78% 72.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14059718 9.23% 81.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11956991 7.85% 89.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4305123 2.82% 92.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2949818 1.94% 94.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1066386 0.70% 94.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 992195 0.65% 95.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6810233 4.47% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 152341466 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 152396278 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221362960 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -274,70 +433,70 @@ system.cpu.commit.branches 12326938 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339549 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6840576 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6810233 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 488726782 # The number of ROB reads -system.cpu.rob.rob_writes 703273689 # The number of ROB writes -system.cpu.timesIdled 1665 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 76645 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 488508126 # The number of ROB reads +system.cpu.rob.rob_writes 702620216 # The number of ROB writes +system.cpu.timesIdled 1506 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 56369 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221362960 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated -system.cpu.cpi 1.281119 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.281119 # CPI: Total CPI of All Threads -system.cpu.ipc 0.780567 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.780567 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 567776084 # number of integer regfile reads -system.cpu.int_regfile_writes 302793169 # number of integer regfile writes -system.cpu.fp_regfile_reads 3492670 # number of floating regfile reads -system.cpu.fp_regfile_writes 2212557 # number of floating regfile writes -system.cpu.misc_regfile_reads 139469476 # number of misc regfile reads +system.cpu.cpi 1.281038 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.281038 # CPI: Total CPI of All Threads +system.cpu.ipc 0.780617 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.780617 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 567639196 # number of integer regfile reads +system.cpu.int_regfile_writes 302703765 # number of integer regfile writes +system.cpu.fp_regfile_reads 3495797 # number of floating regfile reads +system.cpu.fp_regfile_writes 2211250 # number of floating regfile writes +system.cpu.misc_regfile_reads 139399302 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.icache.replacements 5445 # number of replacements -system.cpu.icache.tagsinuse 1641.882453 # Cycle average of tags in use -system.cpu.icache.total_refs 25692314 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 7414 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3465.378203 # Average number of references to valid blocks. +system.cpu.icache.replacements 5641 # number of replacements +system.cpu.icache.tagsinuse 1641.401127 # Cycle average of tags in use +system.cpu.icache.total_refs 25643925 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7612 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 3368.881372 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1641.882453 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.801700 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.801700 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25692314 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25692314 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25692314 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25692314 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25692314 # number of overall hits -system.cpu.icache.overall_hits::total 25692314 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8997 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8997 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8997 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8997 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8997 # number of overall misses -system.cpu.icache.overall_misses::total 8997 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 180939500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 180939500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 180939500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 180939500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 180939500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 180939500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25701311 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25701311 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25701311 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25701311 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25701311 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25701311 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000350 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000350 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000350 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000350 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000350 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000350 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20111.092586 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20111.092586 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20111.092586 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20111.092586 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20111.092586 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20111.092586 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1641.401127 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.801465 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.801465 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25643925 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25643925 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25643925 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25643925 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25643925 # number of overall hits +system.cpu.icache.overall_hits::total 25643925 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 9088 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 9088 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 9088 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 9088 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 9088 # number of overall misses +system.cpu.icache.overall_misses::total 9088 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 147639500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 147639500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 147639500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 147639500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 147639500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 147639500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25653013 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25653013 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25653013 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25653013 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25653013 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25653013 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000354 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000354 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000354 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000354 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000354 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000354 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16245.543574 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16245.543574 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16245.543574 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16245.543574 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16245.543574 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16245.543574 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -346,94 +505,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1358 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1358 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1358 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1358 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1358 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1358 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7639 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 7639 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 7639 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 7639 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 7639 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 7639 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 132852000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 132852000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 132852000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 132852000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 132852000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 132852000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000297 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000297 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000297 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000297 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000297 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000297 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17391.281581 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17391.281581 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17391.281581 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17391.281581 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17391.281581 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17391.281581 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1211 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1211 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1211 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1211 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1211 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1211 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7877 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 7877 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 7877 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 7877 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 7877 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 7877 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 110101000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 110101000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 110101000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 110101000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 110101000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 110101000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000307 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000307 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000307 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13977.529516 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13977.529516 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13977.529516 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13977.529516 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13977.529516 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13977.529516 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 56 # number of replacements -system.cpu.dcache.tagsinuse 1423.300553 # Cycle average of tags in use -system.cpu.dcache.total_refs 68703636 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1986 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34593.975831 # Average number of references to valid blocks. +system.cpu.dcache.replacements 57 # number of replacements +system.cpu.dcache.tagsinuse 1426.186042 # Cycle average of tags in use +system.cpu.dcache.total_refs 68712448 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1990 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34528.868342 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1423.300553 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.347485 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.347485 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 48189408 # 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number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2608 # number of overall misses -system.cpu.dcache.overall_misses::total 2608 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 26356000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 26356000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 66785500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 66785500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 93141500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 93141500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 93141500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 93141500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 48190227 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 48190227 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 1426.186042 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.348190 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.348190 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 48198272 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 48198272 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513902 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513902 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 68712174 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 68712174 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 68712174 # number of overall hits +system.cpu.dcache.overall_hits::total 68712174 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 735 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 735 # 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miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000087 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000087 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000038 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000038 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000038 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000038 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32180.708181 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32180.708181 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37331.190609 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37331.190609 # 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miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000037 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000037 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000037 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000037 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37048.979592 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 37048.979592 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24669.857768 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 24669.857768 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28219.859540 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28219.859540 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28219.859540 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28219.859540 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -442,140 +601,138 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 14 # number of writebacks -system.cpu.dcache.writebacks::total 14 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 394 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 394 # 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number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2257 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2257 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2257 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2257 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17292000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17292000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 41315500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 41315500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 58607500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 58607500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 58607500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 58607500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000087 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34780 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34780 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35332.680470 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35332.680470 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35226.491863 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 35226.491863 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35226.491863 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 35226.491863 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000033 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 24714.079365 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 24746.270420 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |