diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-01-31 07:49:16 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-01-31 07:49:16 -0500 |
| commit | fce3433b2eb764d9519ffbc4c7e95049f3200ba3 (patch) | |
| tree | 26e90c5190c4751532683d1f4b5bf6094e6ba4b7 /tests/long/se/70.twolf/ref/x86/linux | |
| parent | c4898b15bcf5458e35f17cb0c3b4185cec0081aa (diff) | |
| download | gem5-fce3433b2eb764d9519ffbc4c7e95049f3200ba3.tar.xz | |
stats: Update stats for regressions using SimpleDDR3
This patch updates the regression stats to reflect that they are using
the SimpleDDR3 controller by default.
Diffstat (limited to 'tests/long/se/70.twolf/ref/x86/linux')
| -rw-r--r-- | tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt | 1090 |
1 files changed, 545 insertions, 545 deletions
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index daaac056b..ea454cb40 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.082648 # Number of seconds simulated -sim_ticks 82648140000 # Number of ticks simulated -final_tick 82648140000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.082836 # Number of seconds simulated +sim_ticks 82836235000 # Number of ticks simulated +final_tick 82836235000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 59257 # Simulator instruction rate (inst/s) -host_op_rate 99320 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37082179 # Simulator tick rate (ticks/s) -host_mem_usage 321776 # Number of bytes of host memory used -host_seconds 2228.78 # Real time elapsed on the host +host_inst_rate 72340 # Simulator instruction rate (inst/s) +host_op_rate 121249 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45372545 # Simulator tick rate (ticks/s) +host_mem_usage 275820 # Number of bytes of host memory used +host_seconds 1825.69 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221362961 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 217728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 124416 # Number of bytes read from this memory -system.physmem.bytes_read::total 342144 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 217728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 217728 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3402 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1944 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5346 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2634397 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1505370 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4139766 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2634397 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2634397 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2634397 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1505370 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4139766 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5348 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 218368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 124544 # Number of bytes read from this memory +system.physmem.bytes_read::total 342912 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 218368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 218368 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3412 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1946 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5358 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2636141 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1503497 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4139638 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2636141 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2636141 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2636141 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1503497 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4139638 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5362 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 5502 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 342144 # Total number of bytes read from memory +system.physmem.cpureqs 5515 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 342912 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 342144 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 342912 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 154 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 306 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 318 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 313 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 318 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 308 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 368 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 328 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 306 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 260 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 277 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 361 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 434 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 435 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 352 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 369 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 295 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 153 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 275 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 290 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 321 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 274 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 310 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 367 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 377 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 379 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 371 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 376 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 367 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 353 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 361 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 338 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 355 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 248 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 82648109000 # Total gap between requests +system.physmem.totGap 82836206000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 5348 # Categorize read packet sizes +system.physmem.readPktSize::6 5362 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -95,15 +95,15 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 154 # categorize neither packet sizes +system.physmem.neitherpktsize::6 153 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 4185 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 926 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 200 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 943 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 199 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 43 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -164,164 +164,164 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 16873822 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 122447822 # Sum of mem lat for all requests -system.physmem.totBusLat 21392000 # Total cycles spent in databus access -system.physmem.totBankLat 84182000 # Total cycles spent in bank access -system.physmem.avgQLat 3155.16 # Average queueing delay per request -system.physmem.avgBankLat 15740.84 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22896.00 # Average memory access latency +system.physmem.totQLat 15727084 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 132185834 # Sum of mem lat for all requests +system.physmem.totBusLat 26795000 # Total cycles spent in databus access +system.physmem.totBankLat 89663750 # Total cycles spent in bank access +system.physmem.avgQLat 2933.06 # Average queueing delay per request +system.physmem.avgBankLat 16722.07 # Average bank access latency per request +system.physmem.avgBusLat 4997.20 # Average bus latency per request +system.physmem.avgMemAccLat 24652.34 # Average memory access latency system.physmem.avgRdBW 4.14 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 4.14 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4742 # Number of row buffer hits during reads +system.physmem.readRowHits 4538 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.67 # Row buffer hit rate for reads +system.physmem.readRowHitRate 84.63 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 15454021.88 # Average gap between requests -system.cpu.branchPred.lookups 19953215 # Number of BP lookups -system.cpu.branchPred.condPredicted 19953215 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2011335 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 13840594 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13098591 # Number of BTB hits +system.physmem.avgGap 15448751.59 # Average gap between requests +system.cpu.branchPred.lookups 19976706 # Number of BP lookups +system.cpu.branchPred.condPredicted 19976706 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2014402 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 13812152 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13105283 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.638937 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 94.882267 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 165296281 # number of cpu cycles simulated +system.cpu.numCycles 165672471 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 25831000 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 218891152 # Number of instructions fetch has processed -system.cpu.fetch.Branches 19953215 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13098591 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 57573712 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 17632764 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 66415443 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 240 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1579 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 24446053 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 431779 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 165175969 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.190116 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.327383 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 25870668 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 219126869 # Number of instructions fetch has processed +system.cpu.fetch.Branches 19976706 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13105283 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 57628355 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 17696017 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 66630701 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 278 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2007 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 114 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 24475842 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 426793 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 165546176 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.187647 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.326502 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 109199449 66.11% 66.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3061509 1.85% 67.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2383315 1.44% 69.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2892599 1.75% 71.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3450171 2.09% 73.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3573015 2.16% 75.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4309284 2.61% 78.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2725915 1.65% 79.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 33580712 20.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 109520431 66.16% 66.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3059143 1.85% 68.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2383042 1.44% 69.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2888379 1.74% 71.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3450462 2.08% 73.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3573116 2.16% 75.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4323051 2.61% 78.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2727876 1.65% 79.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 33620676 20.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 165175969 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.120712 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.324235 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 38701150 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 56465114 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 44698220 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9957565 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 15353920 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 353610105 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 15353920 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 46165738 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14909579 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 23078 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 46524421 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 42199233 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 345243747 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 88 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 17893684 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22177130 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 107 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 398936501 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 960723880 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 950976963 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9746917 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 165546176 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.120580 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.322651 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 38775408 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 56644846 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 44737695 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9974174 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 15414053 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 354047911 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 15414053 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 46255302 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14979465 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 23344 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 46561207 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 42312805 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 345686471 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 102 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 18031828 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22149425 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 50 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 399403706 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 962076305 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 952204922 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9871383 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259428604 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 139507897 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1674 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1664 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 90390787 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 86672801 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 31756377 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 57758664 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 18775058 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 333623093 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3362 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 267451276 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 258403 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 111810012 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 230098900 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2117 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 165175969 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.619190 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.505359 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 139975102 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1676 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1665 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 90583210 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 86793756 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 31811808 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 57862174 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 18818230 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 334054188 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3459 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 267584091 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 253989 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 112238541 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 231222254 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2214 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 165546176 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.616371 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.504250 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 44964626 27.22% 27.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 46539597 28.18% 55.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 32801785 19.86% 75.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 19824720 12.00% 87.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 13230335 8.01% 95.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4791341 2.90% 98.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2351721 1.42% 99.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 529174 0.32% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 142670 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 45159771 27.28% 27.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 46666031 28.19% 55.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 32872103 19.86% 75.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19858979 12.00% 87.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 13194353 7.97% 95.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4779249 2.89% 98.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2330620 1.41% 99.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 541020 0.33% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 144050 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 165175969 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 165546176 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 137826 5.20% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2250902 84.86% 90.05% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 263908 9.95% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 132244 4.97% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2258982 84.96% 89.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 267651 10.07% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1212134 0.45% 0.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 174151286 65.12% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1212144 0.45% 0.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 174232004 65.11% 65.57% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.57% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1593879 0.60% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1599138 0.60% 66.16% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.16% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.16% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.16% # Type of FU issued @@ -347,84 +347,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.16% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.16% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.16% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 67229168 25.14% 91.30% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 23264809 8.70% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 67256463 25.13% 91.30% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 23284342 8.70% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 267451276 # Type of FU issued -system.cpu.iq.rate 1.618011 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2652636 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009918 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 697648502 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 441157156 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 260237459 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5341058 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4570848 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2570585 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266205797 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2685981 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 19039823 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 267584091 # Type of FU issued +system.cpu.iq.rate 1.615139 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2658877 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009937 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 698266747 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 441935949 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 260335869 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 5360477 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4651988 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2579879 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266334819 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2696005 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 19019917 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 30023215 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 29490 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 296813 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11240660 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 30144170 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 29191 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 297029 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11296091 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 49425 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 49411 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 15353920 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 582358 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 260686 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 333626455 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 190123 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 86672801 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 31756377 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1654 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 146774 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 31153 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 296813 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1177159 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 916050 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2093209 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 264577691 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 66245889 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2873585 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 15414053 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 584332 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 268197 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 334057647 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 187603 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 86793756 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 31811808 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1663 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 154006 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 31822 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 297029 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1177472 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 918811 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2096283 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 264704604 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 66268952 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2879487 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 89117815 # number of memory reference insts executed -system.cpu.iew.exec_branches 14597039 # Number of branches executed -system.cpu.iew.exec_stores 22871926 # Number of stores executed -system.cpu.iew.exec_rate 1.600627 # Inst execution rate -system.cpu.iew.wb_sent 263630467 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 262808044 # cumulative count of insts written-back -system.cpu.iew.wb_producers 212084858 # num instructions producing a value -system.cpu.iew.wb_consumers 375096623 # num instructions consuming a value +system.cpu.iew.exec_refs 89158933 # number of memory reference insts executed +system.cpu.iew.exec_branches 14605846 # Number of branches executed +system.cpu.iew.exec_stores 22889981 # Number of stores executed +system.cpu.iew.exec_rate 1.597759 # Inst execution rate +system.cpu.iew.wb_sent 263752937 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 262915748 # cumulative count of insts written-back +system.cpu.iew.wb_producers 212158955 # num instructions producing a value +system.cpu.iew.wb_consumers 375269860 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.589921 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.565414 # average fanout of values written-back +system.cpu.iew.wb_rate 1.586961 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.565350 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 112301239 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 112734910 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2011502 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149822049 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.477506 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.946000 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2014608 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 150132123 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.474454 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.942401 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 50722618 33.86% 33.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57116806 38.12% 71.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13820755 9.22% 81.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12019830 8.02% 89.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4145175 2.77% 91.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2956577 1.97% 93.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1072909 0.72% 94.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 994916 0.66% 95.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6972463 4.65% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 50871002 33.88% 33.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57276171 38.15% 72.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13824598 9.21% 81.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12056402 8.03% 89.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4136994 2.76% 92.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2958422 1.97% 94.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1072501 0.71% 94.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 994968 0.66% 95.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6941065 4.62% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149822049 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 150132123 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221362961 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -435,198 +435,198 @@ system.cpu.commit.branches 12326938 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339551 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6972463 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6941065 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 476513786 # The number of ROB reads -system.cpu.rob.rob_writes 682717187 # The number of ROB writes -system.cpu.timesIdled 2881 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 120312 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 477288929 # The number of ROB reads +system.cpu.rob.rob_writes 683644230 # The number of ROB writes +system.cpu.timesIdled 2956 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 126295 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221362961 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated -system.cpu.cpi 1.251570 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.251570 # CPI: Total CPI of All Threads -system.cpu.ipc 0.798997 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.798997 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 562635091 # number of integer regfile reads -system.cpu.int_regfile_writes 298739906 # number of integer regfile writes -system.cpu.fp_regfile_reads 3520410 # number of floating regfile reads -system.cpu.fp_regfile_writes 2230055 # number of floating regfile writes -system.cpu.misc_regfile_reads 137014018 # number of misc regfile reads +system.cpu.cpi 1.254418 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.254418 # CPI: Total CPI of All Threads +system.cpu.ipc 0.797182 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.797182 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 562757952 # number of integer regfile reads +system.cpu.int_regfile_writes 298813122 # number of integer regfile writes +system.cpu.fp_regfile_reads 3531630 # number of floating regfile reads +system.cpu.fp_regfile_writes 2237821 # number of floating regfile writes +system.cpu.misc_regfile_reads 137110805 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.icache.replacements 4732 # number of replacements -system.cpu.icache.tagsinuse 1624.168426 # Cycle average of tags in use -system.cpu.icache.total_refs 24437101 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 6701 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3646.784211 # Average number of references to valid blocks. +system.cpu.icache.replacements 4901 # number of replacements +system.cpu.icache.tagsinuse 1627.835837 # Cycle average of tags in use +system.cpu.icache.total_refs 24466683 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 6871 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 3560.862029 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1624.168426 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.793051 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.793051 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 24437101 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 24437101 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 24437101 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 24437101 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 24437101 # number of overall hits -system.cpu.icache.overall_hits::total 24437101 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8952 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8952 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8952 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8952 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8952 # number of overall misses -system.cpu.icache.overall_misses::total 8952 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 259465998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 259465998 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 259465998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 259465998 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 259465998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 259465998 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 24446053 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 24446053 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 24446053 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 24446053 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 24446053 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 24446053 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000366 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000366 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000366 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000366 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000366 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000366 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28984.137399 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28984.137399 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28984.137399 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28984.137399 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28984.137399 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28984.137399 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 676 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1627.835837 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.794842 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.794842 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 24466683 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 24466683 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 24466683 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 24466683 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 24466683 # number of overall hits +system.cpu.icache.overall_hits::total 24466683 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 9159 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 9159 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 9159 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 9159 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 9159 # number of overall misses +system.cpu.icache.overall_misses::total 9159 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 269675497 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 269675497 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 269675497 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 269675497 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 269675497 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 269675497 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 24475842 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 24475842 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 24475842 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24475842 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24475842 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 24475842 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000374 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000374 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000374 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000374 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000374 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000374 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29443.770827 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 29443.770827 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 29443.770827 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 29443.770827 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 29443.770827 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 29443.770827 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 864 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 21 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 26 # 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number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6855 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 6855 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 6855 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6855 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6855 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6855 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 198302998 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 198302998 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 198302998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 198302998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 198302998 # 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number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 7026 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 7026 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 7026 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 205371497 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 205371497 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 205371497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 205371497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 205371497 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 205371497 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000287 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000287 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000287 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000287 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000287 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000287 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29230.215912 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29230.215912 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29230.215912 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 29230.215912 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29230.215912 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 29230.215912 # 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Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 274.236526 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000028 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.068200 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.008369 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.076596 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 3299 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::writebacks 1.438884 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2246.558475 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 283.750928 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000044 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.068560 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.008659 # 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number of replacements +system.cpu.dcache.tagsinuse 1416.460930 # Cycle average of tags in use +system.cpu.dcache.total_refs 67604390 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1983 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34091.976803 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1411.367257 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.344572 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.344572 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 47046789 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 47046789 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20514009 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20514009 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 67560798 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 67560798 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 67560798 # number of overall hits -system.cpu.dcache.overall_hits::total 67560798 # number of overall hits +system.cpu.dcache.occ_blocks::cpu.data 1416.460930 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.345816 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.345816 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 47090189 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 47090189 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20514015 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20514015 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 67604204 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 67604204 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 67604204 # number of overall hits +system.cpu.dcache.overall_hits::total 67604204 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 791 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 791 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1722 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1722 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2513 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2513 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2513 # number of overall misses -system.cpu.dcache.overall_misses::total 2513 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 37144000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 37144000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 76853000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 76853000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 113997000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 113997000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 113997000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 113997000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 47047580 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 47047580 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 1716 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1716 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2507 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2507 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2507 # number of overall misses +system.cpu.dcache.overall_misses::total 2507 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 39751500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 39751500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 77402500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 77402500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 117154000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 117154000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 117154000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 117154000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 47090980 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 47090980 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 67563311 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 67563311 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 67563311 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 67563311 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 67606711 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 67606711 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 67606711 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 67606711 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000084 # miss rate for WriteReq accesses @@ -737,48 +737,48 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000037 system.cpu.dcache.demand_miss_rate::total 0.000037 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000037 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000037 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46958.280657 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 46958.280657 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44630.081301 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44630.081301 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45362.912853 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45362.912853 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45362.912853 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45362.912853 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 86 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50254.740834 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50254.740834 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45106.351981 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45106.351981 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 46730.753889 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 46730.753889 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 46730.753889 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 46730.753889 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 35 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 43 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 17.500000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 14 # number of writebacks -system.cpu.dcache.writebacks::total 14 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 374 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 374 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 376 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 376 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 376 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 376 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 417 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 417 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1720 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1720 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2137 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2137 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2137 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2137 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22474000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 22474000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73299500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 73299500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 95773500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 95773500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 95773500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 95773500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 13 # number of writebacks +system.cpu.dcache.writebacks::total 13 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 367 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 367 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 368 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 368 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 368 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 368 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 424 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 424 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1715 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1715 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2139 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2139 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2139 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2139 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24221500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24221500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73937000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 73937000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 98158500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 98158500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 98158500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 98158500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for WriteReq accesses @@ -787,14 +787,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53894.484412 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53894.484412 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42615.988372 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42615.988372 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44816.799251 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44816.799251 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44816.799251 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44816.799251 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57126.179245 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57126.179245 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43111.953353 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43111.953353 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45889.901823 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 45889.901823 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45889.901823 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 45889.901823 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |