diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
| commit | 55ed9609f1056280404a8dc49e53e4ba33ae51dd (patch) | |
| tree | 6e50ced504e91a6d9dadff1b43b89a0911df3d7a /tests/long/se/70.twolf/ref | |
| parent | ee7d8fdcb2226139fd1d6a6f0cde987721ea3699 (diff) | |
| download | gem5-55ed9609f1056280404a8dc49e53e4ba33ae51dd.tar.xz | |
stats: Update to match classic memory changes
Diffstat (limited to 'tests/long/se/70.twolf/ref')
5 files changed, 2485 insertions, 2479 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index 78502d1ca..d3e370d8a 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.053345 # Number of seconds simulated -sim_ticks 53344764500 # Number of ticks simulated -final_tick 53344764500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.053349 # Number of seconds simulated +sim_ticks 53349450500 # Number of ticks simulated +final_tick 53349450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 260335 # Simulator instruction rate (inst/s) -host_op_rate 260335 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 151110624 # Simulator tick rate (ticks/s) -host_mem_usage 253412 # Number of bytes of host memory used -host_seconds 353.02 # Real time elapsed on the host +host_inst_rate 273465 # Simulator instruction rate (inst/s) +host_op_rate 273465 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 158745564 # Simulator tick rate (ticks/s) +host_mem_usage 258296 # Number of bytes of host memory used +host_seconds 336.07 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 202880 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 137728 # Number of bytes read from this memory system.physmem.bytes_read::total 340608 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 202880 # Nu system.physmem.num_reads::cpu.inst 3170 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2152 # Number of read requests responded to by this memory system.physmem.num_reads::total 5322 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3803185 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2581847 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6385031 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3803185 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3803185 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3803185 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2581847 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6385031 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 3802851 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2581620 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6384471 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3802851 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3802851 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3802851 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2581620 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6384471 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 5322 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 5322 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 53344677500 # Total gap between requests +system.physmem.totGap 53349362500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -92,8 +92,8 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 4932 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 379 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 380 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -187,29 +187,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 989 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 343.749242 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 211.692592 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 325.528362 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 314 31.75% 31.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 216 21.84% 53.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 88 8.90% 62.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 117 11.83% 74.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 52 5.26% 79.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 40 4.04% 83.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 29 2.93% 86.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 21 2.12% 88.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 112 11.32% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 989 # Bytes accessed per row activation -system.physmem.totQLat 40222250 # Total ticks spent queuing -system.physmem.totMemAccLat 140009750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 982 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 345.743381 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 213.338865 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.606559 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 303 30.86% 30.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 220 22.40% 53.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 94 9.57% 62.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 105 10.69% 73.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 62 6.31% 79.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 36 3.67% 83.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 29 2.95% 86.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 22 2.24% 88.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 111 11.30% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 982 # Bytes accessed per row activation +system.physmem.totQLat 40016750 # Total ticks spent queuing +system.physmem.totMemAccLat 139804250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26610000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7557.73 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7519.12 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26307.73 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 6.39 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26269.12 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 6.38 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 6.39 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.38 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage @@ -217,49 +217,49 @@ system.physmem.busUtilRead 0.05 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4331 # Number of row buffer hits during reads +system.physmem.readRowHits 4333 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.38 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.42 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 10023426.81 # Average gap between requests -system.physmem.pageHitRate 81.38 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3538080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1930500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 20022600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 10024307.12 # Average gap between requests +system.physmem.pageHitRate 81.42 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3462480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1889250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 19843200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 3484144560 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1791514845 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 30434811000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 35735961585 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.917071 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 50627942250 # Time in different power states +system.physmem_0.actBackEnergy 1795262310 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 30431523750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 35736125550 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.920144 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 50622338000 # Time in different power states system.physmem_0.memoryStateTime::REF 1781260000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 934855250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 940274500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3938760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2149125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 21411000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3923640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2140875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 21247200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 3484144560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1835182260 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 30396506250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 35743331955 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.055238 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 50563679500 # Time in different power states +system.physmem_1.actBackEnergy 1822659075 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 30407483250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 35741598600 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.022916 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 50582866250 # Time in different power states system.physmem_1.memoryStateTime::REF 1781260000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 998933000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 980601250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 11450644 # Number of BP lookups -system.cpu.branchPred.condPredicted 8210940 # Number of conditional branches predicted +system.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 11450641 # Number of BP lookups +system.cpu.branchPred.condPredicted 8210938 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 765018 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 6085193 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5320740 # Number of BTB hits +system.cpu.branchPred.BTBLookups 6085190 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5320739 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.437490 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1176675 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 87.437516 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1176674 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 26315 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 24242 # Number of indirect target hits. @@ -270,22 +270,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20415220 # DTB read hits +system.cpu.dtb.read_hits 20415218 # DTB read hits system.cpu.dtb.read_misses 43383 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20458603 # DTB read accesses +system.cpu.dtb.read_accesses 20458601 # DTB read accesses system.cpu.dtb.write_hits 6579912 # DTB write hits system.cpu.dtb.write_misses 276 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 6580188 # DTB write accesses -system.cpu.dtb.data_hits 26995132 # DTB hits +system.cpu.dtb.data_hits 26995130 # DTB hits system.cpu.dtb.data_misses 43659 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 27038791 # DTB accesses -system.cpu.itb.fetch_hits 22968620 # ITB hits +system.cpu.dtb.data_accesses 27038789 # DTB accesses +system.cpu.itb.fetch_hits 22968614 # ITB hits system.cpu.itb.fetch_misses 90 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 22968710 # ITB accesses +system.cpu.itb.fetch_accesses 22968704 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -299,16 +299,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 53344764500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 106689529 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 53349450500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 106698901 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 91903089 # Number of instructions committed system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2191325 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2191321 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.160892 # CPI: cycles per instruction -system.cpu.ipc 0.861407 # IPC: instructions per cycle +system.cpu.cpi 1.160994 # CPI: cycles per instruction +system.cpu.ipc 0.861331 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 7723353 8.40% 8.40% # Class of committed instruction system.cpu.op_class_0::IntAlu 51001454 55.49% 63.90% # Class of committed instruction system.cpu.op_class_0::IntMult 458252 0.50% 64.40% # Class of committed instruction @@ -344,16 +344,16 @@ system.cpu.op_class_0::MemWrite 6501126 7.07% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 91903089 # Class of committed instruction -system.cpu.tickCycles 103791732 # Number of cycles that the object actually ticked -system.cpu.idleCycles 2897797 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 103791781 # Number of cycles that the object actually ticked +system.cpu.idleCycles 2907120 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1447.584436 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26572205 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1447.584590 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26572201 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2231 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11910.445988 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11910.444195 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1447.584436 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1447.584590 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.353414 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.353414 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2074 # Occupied blocks per task id @@ -363,41 +363,41 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 228 system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1379 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.506348 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 53153443 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 53153443 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 20074007 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20074007 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6498198 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6498198 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26572205 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26572205 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26572205 # number of overall hits -system.cpu.dcache.overall_hits::total 26572205 # number of overall hits +system.cpu.dcache.tags.tag_accesses 53153439 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 53153439 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 20074005 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20074005 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6498196 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6498196 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26572201 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26572201 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26572201 # number of overall hits +system.cpu.dcache.overall_hits::total 26572201 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 496 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 496 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2905 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2905 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3401 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3401 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3401 # number of overall misses -system.cpu.dcache.overall_misses::total 3401 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 37448500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 37448500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 219755500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 219755500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 257204000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 257204000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 257204000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 257204000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20074503 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20074503 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 2907 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2907 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3403 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3403 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3403 # number of overall misses +system.cpu.dcache.overall_misses::total 3403 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 37687000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 37687000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 223750000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 223750000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 261437000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 261437000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 261437000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 261437000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20074501 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20074501 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 26575606 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 26575606 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 26575606 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 26575606 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 26575604 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26575604 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 26575604 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26575604 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000447 # miss rate for WriteReq accesses @@ -406,14 +406,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000128 system.cpu.dcache.demand_miss_rate::total 0.000128 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000128 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000128 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75501.008065 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75501.008065 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75647.332186 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 75647.332186 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 75625.992355 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 75625.992355 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 75625.992355 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 75625.992355 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75981.854839 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 75981.854839 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76969.384245 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76969.384245 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76825.448134 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76825.448134 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76825.448134 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76825.448134 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -424,12 +424,12 @@ system.cpu.dcache.writebacks::writebacks 107 # nu system.cpu.dcache.writebacks::total 107 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1162 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1162 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1170 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1170 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1170 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1170 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1164 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1164 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1172 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1172 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1172 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1172 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 488 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 488 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1743 # number of WriteReq MSHR misses @@ -438,14 +438,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2231 system.cpu.dcache.demand_mshr_misses::total 2231 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2231 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2231 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36544000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36544000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 137282000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 137282000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 173826000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 173826000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 173826000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 173826000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36777500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36777500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 140150000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 140150000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 176927500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 176927500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 176927500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 176927500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses @@ -454,24 +454,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74885.245902 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74885.245902 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78761.904762 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78761.904762 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77913.939937 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77913.939937 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77913.939937 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77913.939937 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75363.729508 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75363.729508 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80407.343660 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80407.343660 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79304.123711 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 79304.123711 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79304.123711 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 79304.123711 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 13865 # number of replacements -system.cpu.icache.tags.tagsinuse 1642.714068 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22952789 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1642.701416 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22952783 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15830 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1449.955085 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1449.954706 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1642.714068 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.802106 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.802106 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1642.701416 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.802100 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.802100 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id @@ -479,45 +479,45 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 670 system.cpu.icache.tags.age_task_id_blocks_1024::3 150 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 947 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45953070 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45953070 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 22952789 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22952789 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22952789 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22952789 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22952789 # number of overall hits -system.cpu.icache.overall_hits::total 22952789 # number of overall hits +system.cpu.icache.tags.tag_accesses 45953058 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45953058 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 22952783 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22952783 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22952783 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22952783 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22952783 # number of overall hits +system.cpu.icache.overall_hits::total 22952783 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 15831 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 15831 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 15831 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 15831 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15831 # number of overall misses system.cpu.icache.overall_misses::total 15831 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 409090000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 409090000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 409090000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 409090000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 409090000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 409090000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22968620 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22968620 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22968620 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22968620 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22968620 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22968620 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 411111000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 411111000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 411111000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 411111000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 411111000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 411111000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22968614 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22968614 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22968614 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22968614 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22968614 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22968614 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000689 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000689 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000689 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000689 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000689 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000689 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25841.071316 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25841.071316 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25841.071316 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25841.071316 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25841.071316 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25841.071316 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25968.732234 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25968.732234 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25968.732234 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25968.732234 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25968.732234 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25968.732234 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -532,48 +532,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15831 system.cpu.icache.demand_mshr_misses::total 15831 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15831 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15831 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 393260000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 393260000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 393260000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 393260000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 393260000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 393260000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 395281000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 395281000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 395281000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 395281000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 395281000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 395281000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000689 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000689 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000689 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24841.134483 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24841.134483 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24841.134483 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 24841.134483 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24841.134483 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 24841.134483 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24968.795401 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24968.795401 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24968.795401 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24968.795401 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24968.795401 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24968.795401 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2482.282304 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 26642 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3671 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.257423 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 3575.444447 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 26761 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5322 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 5.028373 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.761061 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2102.458659 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 362.062585 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000542 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2102.450993 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1472.993454 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064162 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.011049 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.075753 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3671 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 771 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 183 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2509 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.112030 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 262078 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 262078 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_percent::cpu.data 0.044952 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.109114 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 5322 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 920 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 569 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3605 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.162415 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 261986 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 261986 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 13865 # number of WritebackClean hits @@ -602,18 +600,18 @@ system.cpu.l2cache.demand_misses::total 5322 # nu system.cpu.l2cache.overall_misses::cpu.inst 3170 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2152 # number of overall misses system.cpu.l2cache.overall_misses::total 5322 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 134394000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 134394000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 236583500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 236583500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 35249500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 35249500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 236583500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 169643500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 406227000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 236583500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 169643500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 406227000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 137262000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 137262000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 238604500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 238604500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 35483000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 35483000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 238604500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 172745000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 411349500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 238604500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 172745000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 411349500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 107 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 107 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 13865 # number of WritebackClean accesses(hits+misses) @@ -642,18 +640,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.294668 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200253 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964590 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.294668 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78272.568433 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78272.568433 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74632.018927 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74632.018927 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81033.333333 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81033.333333 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74632.018927 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78830.622677 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76329.763247 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74632.018927 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78830.622677 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76329.763247 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79942.923704 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79942.923704 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75269.558360 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75269.558360 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81570.114943 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81570.114943 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75269.558360 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80271.840149 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77292.277339 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75269.558360 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80271.840149 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77292.277339 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -672,18 +670,18 @@ system.cpu.l2cache.demand_mshr_misses::total 5322 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3170 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2152 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5322 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 117224000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 117224000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 204883500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 204883500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30899500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30899500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 204883500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 148123500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 353007000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 204883500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 148123500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 353007000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 120092000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 120092000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 206904500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 206904500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31133000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31133000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 206904500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151225000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 358129500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 206904500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151225000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 358129500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985083 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985083 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.200253 # mshr miss rate for ReadCleanReq accesses @@ -696,25 +694,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.294668 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200253 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964590 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.294668 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68272.568433 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68272.568433 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64632.018927 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64632.018927 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71033.333333 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71033.333333 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64632.018927 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68830.622677 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66329.763247 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64632.018927 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68830.622677 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66329.763247 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69942.923704 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69942.923704 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65269.558360 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65269.558360 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71570.114943 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71570.114943 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65269.558360 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70271.840149 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67292.277339 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65269.558360 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70271.840149 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67292.277339 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 32083 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 14022 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 16318 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 13865 # Transaction distribution @@ -748,7 +746,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 23745000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3346500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 5322 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 3605 # Transaction distribution system.membus.trans_dist::ReadExReq 1717 # Transaction distribution system.membus.trans_dist::ReadExResp 1717 # Transaction distribution @@ -769,9 +773,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 5322 # Request fanout histogram -system.membus.reqLayer0.occupancy 6419500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6421000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 28179750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 28180500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 002e3eec9..720778178 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.021909 # Number of seconds simulated -sim_ticks 21909208500 # Number of ticks simulated -final_tick 21909208500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.021906 # Number of seconds simulated +sim_ticks 21906070500 # Number of ticks simulated +final_tick 21906070500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 183723 # Simulator instruction rate (inst/s) -host_op_rate 183723 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47816944 # Simulator tick rate (ticks/s) -host_mem_usage 254944 # Number of bytes of host memory used -host_seconds 458.19 # Real time elapsed on the host +host_inst_rate 201237 # Simulator instruction rate (inst/s) +host_op_rate 201237 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52367931 # Simulator tick rate (ticks/s) +host_mem_usage 260088 # Number of bytes of host memory used +host_seconds 418.31 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 195968 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 138560 # Number of bytes read from this memory system.physmem.bytes_read::total 334528 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 195968 # Nu system.physmem.num_reads::cpu.inst 3062 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2165 # Number of read requests responded to by this memory system.physmem.num_reads::total 5227 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8944550 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6324281 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15268831 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8944550 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8944550 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8944550 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6324281 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15268831 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 8945831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6325187 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15271018 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8945831 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8945831 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8945831 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6325187 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15271018 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 5227 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 5227 # Number of DRAM read bursts, including those serviced by the write queue @@ -43,7 +43,7 @@ system.physmem.servicedByWrQ 0 # Nu system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 470 # Per bank write bursts -system.physmem.perBankRdBursts::1 291 # Per bank write bursts +system.physmem.perBankRdBursts::1 292 # Per bank write bursts system.physmem.perBankRdBursts::2 302 # Per bank write bursts system.physmem.perBankRdBursts::3 523 # Per bank write bursts system.physmem.perBankRdBursts::4 220 # Per bank write bursts @@ -55,7 +55,7 @@ system.physmem.perBankRdBursts::9 278 # Pe system.physmem.perBankRdBursts::10 249 # Per bank write bursts system.physmem.perBankRdBursts::11 251 # Per bank write bursts system.physmem.perBankRdBursts::12 395 # Per bank write bursts -system.physmem.perBankRdBursts::13 339 # Per bank write bursts +system.physmem.perBankRdBursts::13 338 # Per bank write bursts system.physmem.perBankRdBursts::14 492 # Per bank write bursts system.physmem.perBankRdBursts::15 449 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21909113500 # Total gap between requests +system.physmem.totGap 21905974500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,11 +91,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3269 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1202 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 507 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 232 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1193 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 513 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 227 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 857 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 387.435239 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 233.348968 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 357.138574 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 246 28.70% 28.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 186 21.70% 50.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 85 9.92% 60.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 65 7.58% 67.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 37 4.32% 72.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 35 4.08% 76.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 34 3.97% 80.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 49 5.72% 86.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 120 14.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 857 # Bytes accessed per row activation -system.physmem.totQLat 42496500 # Total ticks spent queuing -system.physmem.totMemAccLat 140502750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 862 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 385.707657 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 229.399691 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 360.883028 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 260 30.16% 30.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 179 20.77% 50.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 93 10.79% 61.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 57 6.61% 68.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 30 3.48% 71.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 37 4.29% 76.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 31 3.60% 79.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 50 5.80% 85.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 125 14.50% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 862 # Bytes accessed per row activation +system.physmem.totQLat 40339750 # Total ticks spent queuing +system.physmem.totMemAccLat 138346000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26135000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8130.19 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7717.57 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26880.19 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26467.57 # Average memory access latency per DRAM burst system.physmem.avgRdBW 15.27 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 15.27 # Average system read bandwidth in MiByte/s @@ -217,75 +217,75 @@ system.physmem.busUtilRead 0.12 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4359 # Number of row buffer hits during reads +system.physmem.readRowHits 4357 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.39 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.36 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4191527.36 # Average gap between requests -system.physmem.pageHitRate 83.39 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3076920 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1678875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 19468800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 4190926.82 # Average gap between requests +system.physmem.pageHitRate 83.36 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3129840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1707750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 19570200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1430579280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 930163050 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 12325856250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14710823175 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.635656 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 20502630500 # Time in different power states +system.physmem_0.actBackEnergy 905463810 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 12347522250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14707973130 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.505534 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 20538678250 # Time in different power states system.physmem_0.memoryStateTime::REF 731380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 668984500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 632936750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3341520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1823250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 20771400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3333960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1819125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 20779200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1430579280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 904676355 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 12348213000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 14709404805 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.570899 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 20540502500 # Time in different power states +system.physmem_1.actBackEnergy 902236185 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 12350353500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14709101250 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.557040 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 20543762750 # Time in different power states system.physmem_1.memoryStateTime::REF 731380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 632027000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 628284250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 16102191 # Number of BP lookups -system.cpu.branchPred.condPredicted 11688099 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 930994 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8963309 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7508263 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 16102243 # Number of BP lookups +system.cpu.branchPred.condPredicted 11688063 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 931000 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8962915 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7507921 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.766642 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1594548 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 465 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 29370 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 25724 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 3646 # Number of indirect misses. +system.cpu.branchPred.BTBHitPct 83.766509 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1594308 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 466 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 29379 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 25730 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 3649 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 560 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 24064579 # DTB read hits -system.cpu.dtb.read_misses 206327 # DTB read misses -system.cpu.dtb.read_acv 4 # DTB read access violations -system.cpu.dtb.read_accesses 24270906 # DTB read accesses -system.cpu.dtb.write_hits 7168860 # DTB write hits -system.cpu.dtb.write_misses 1193 # DTB write misses +system.cpu.dtb.read_hits 24059471 # DTB read hits +system.cpu.dtb.read_misses 206747 # DTB read misses +system.cpu.dtb.read_acv 6 # DTB read access violations +system.cpu.dtb.read_accesses 24266218 # DTB read accesses +system.cpu.dtb.write_hits 7167964 # DTB write hits +system.cpu.dtb.write_misses 1190 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 7170053 # DTB write accesses -system.cpu.dtb.data_hits 31233439 # DTB hits -system.cpu.dtb.data_misses 207520 # DTB misses -system.cpu.dtb.data_acv 4 # DTB access violations -system.cpu.dtb.data_accesses 31440959 # DTB accesses -system.cpu.itb.fetch_hits 15932703 # ITB hits +system.cpu.dtb.write_accesses 7169154 # DTB write accesses +system.cpu.dtb.data_hits 31227435 # DTB hits +system.cpu.dtb.data_misses 207937 # DTB misses +system.cpu.dtb.data_acv 6 # DTB access violations +system.cpu.dtb.data_accesses 31435372 # DTB accesses +system.cpu.itb.fetch_hits 15930202 # ITB hits system.cpu.itb.fetch_misses 79 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 15932782 # ITB accesses +system.cpu.itb.fetch_accesses 15930281 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -299,140 +299,140 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 21909208500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 43818418 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 21906070500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 43812142 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 16643559 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 137979359 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16102191 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9128535 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 25956071 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1939868 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 165 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2614 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 15932703 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 367699 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 43572351 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.166672 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.433625 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 16640800 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 137955116 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16102243 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9127959 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 25951378 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1939862 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 140 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2284 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 28 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 15930202 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 367997 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 43564561 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.166682 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.433652 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19392056 44.51% 44.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2618542 6.01% 50.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1330036 3.05% 53.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1934112 4.44% 58.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3001913 6.89% 64.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1292242 2.97% 67.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1355704 3.11% 70.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 886645 2.03% 73.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11761101 26.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19388904 44.51% 44.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2617971 6.01% 50.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1329653 3.05% 53.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1933242 4.44% 58.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3001866 6.89% 64.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1292154 2.97% 67.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1355153 3.11% 70.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 885983 2.03% 73.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11759635 26.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43572351 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.367475 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.148890 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12867028 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8206518 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19434084 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2106116 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 958605 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2654233 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 11853 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 132149690 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 49712 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 958605 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13986113 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4641138 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10397 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20305818 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3670280 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 128777120 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 70822 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2026790 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1359443 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 54939 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 94599417 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 167333836 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 159779688 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7554147 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 43564561 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.367529 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.148787 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12866207 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8201064 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19435677 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2103016 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 958597 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2653560 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 11864 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 132121785 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 49799 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 958597 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13983011 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4637206 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10599 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20305280 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3669868 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 128752916 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 70736 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2012785 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1367413 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 56554 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 94580122 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 167299448 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 159747069 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7552378 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 26172056 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 950 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 946 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8271760 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26904379 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8704430 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3459754 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1614105 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111855372 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1919 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 99762873 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 119457 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 27677581 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 21095041 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1530 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43572351 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.289591 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.099378 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 26152761 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 954 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 949 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8254781 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26901517 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8704631 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3463893 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1634991 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111837286 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1924 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 99746434 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 118591 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 27659500 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 21091403 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1535 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43564561 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.289623 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.099110 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11226739 25.77% 25.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 7658694 17.58% 43.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7470474 17.14% 60.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5702469 13.09% 73.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4463101 10.24% 83.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2983064 6.85% 90.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2041659 4.69% 95.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1171062 2.69% 98.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 855089 1.96% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11223672 25.76% 25.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 7655343 17.57% 43.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7467756 17.14% 60.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5704970 13.10% 73.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4467403 10.25% 83.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2981246 6.84% 90.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2039535 4.68% 95.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1169471 2.68% 98.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 855165 1.96% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43572351 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43564561 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 483998 20.16% 20.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 481664 20.16% 20.16% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 20.16% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 20.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 538 0.02% 20.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 522 0.02% 20.18% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 34928 1.45% 21.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 12187 0.51% 22.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1012495 42.17% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 694978 28.95% 93.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 161680 6.73% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 34768 1.46% 21.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 12121 0.51% 22.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1011551 42.34% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 688710 28.83% 93.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 159620 6.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60663003 60.81% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 489936 0.49% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60652801 60.81% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 489881 0.49% 61.30% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2847512 2.85% 64.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115351 0.12% 64.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2443315 2.45% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 314199 0.31% 67.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 765838 0.77% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2847832 2.86% 64.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115342 0.12% 64.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2442782 2.45% 66.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 314177 0.31% 67.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 766025 0.77% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.80% # Type of FU issued @@ -454,82 +454,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.80% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24854808 24.91% 92.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7268585 7.29% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24850091 24.91% 92.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7267177 7.29% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 99762873 # Type of FU issued -system.cpu.iq.rate 2.276734 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2400804 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024065 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 229929463 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 129921880 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 89757813 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15688895 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9653551 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7189472 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 93781732 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8381938 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1923340 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 99746434 # Type of FU issued +system.cpu.iq.rate 2.276685 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2388956 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023950 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 229877287 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 129889935 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 89741335 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15687689 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9649325 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7189295 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 93754597 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8380786 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1921314 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6908181 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11335 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 40937 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2203327 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6905319 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11494 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 40918 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2203528 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 42874 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1494 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 42875 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1512 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 958605 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3611196 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 465334 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 122779718 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 241439 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26904379 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8704430 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1919 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 38387 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 421097 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 40937 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 531949 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 502390 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1034339 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 98437326 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 24271451 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1325547 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 958597 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3610605 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 461685 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 122758059 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 241249 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 26901517 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8704631 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1924 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 38682 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 417297 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 40918 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 531922 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 502439 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1034361 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 98421413 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 24266766 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1325021 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10922427 # number of nop insts executed -system.cpu.iew.exec_refs 31441543 # number of memory reference insts executed -system.cpu.iew.exec_branches 12471856 # Number of branches executed -system.cpu.iew.exec_stores 7170092 # Number of stores executed -system.cpu.iew.exec_rate 2.246483 # Inst execution rate -system.cpu.iew.wb_sent 97646069 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 96947285 # cumulative count of insts written-back -system.cpu.iew.wb_producers 66976790 # num instructions producing a value -system.cpu.iew.wb_consumers 94960923 # num instructions consuming a value -system.cpu.iew.wb_rate 2.212478 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.705309 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 30878414 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 10918849 # number of nop insts executed +system.cpu.iew.exec_refs 31435958 # number of memory reference insts executed +system.cpu.iew.exec_branches 12470734 # Number of branches executed +system.cpu.iew.exec_stores 7169192 # Number of stores executed +system.cpu.iew.exec_rate 2.246441 # Inst execution rate +system.cpu.iew.wb_sent 97629714 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 96930630 # cumulative count of insts written-back +system.cpu.iew.wb_producers 66965531 # num instructions producing a value +system.cpu.iew.wb_consumers 94946242 # num instructions consuming a value +system.cpu.iew.wb_rate 2.212415 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.705299 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 30856710 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 919665 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 39078577 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.351750 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.919984 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 919666 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 39073158 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.352076 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.920100 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 14680368 37.57% 37.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8532696 21.83% 59.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3879932 9.93% 69.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1909819 4.89% 74.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1376650 3.52% 77.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1035169 2.65% 80.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 692226 1.77% 82.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 728499 1.86% 84.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6243218 15.98% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 14677251 37.56% 37.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8528323 21.83% 59.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3880033 9.93% 69.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1914323 4.90% 74.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1374739 3.52% 77.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1034073 2.65% 80.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 692942 1.77% 82.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 727068 1.86% 84.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6244406 15.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 39078577 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 39073158 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -575,118 +575,118 @@ system.cpu.commit.op_class_0::MemWrite 6501103 7.07% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction -system.cpu.commit.bw_lim_events 6243218 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 155615788 # The number of ROB reads -system.cpu.rob.rob_writes 250112160 # The number of ROB writes -system.cpu.timesIdled 4756 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 246067 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 6244406 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 155587477 # The number of ROB reads +system.cpu.rob.rob_writes 250066312 # The number of ROB writes +system.cpu.timesIdled 4758 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 247581 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.520534 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.520534 # CPI: Total CPI of All Threads -system.cpu.ipc 1.921103 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.921103 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 133011224 # number of integer regfile reads -system.cpu.int_regfile_writes 72905073 # number of integer regfile writes -system.cpu.fp_regfile_reads 6263399 # number of floating regfile reads -system.cpu.fp_regfile_writes 6178143 # number of floating regfile writes -system.cpu.misc_regfile_reads 719113 # number of misc regfile reads +system.cpu.cpi 0.520460 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.520460 # CPI: Total CPI of All Threads +system.cpu.ipc 1.921379 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.921379 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 132984940 # number of integer regfile reads +system.cpu.int_regfile_writes 72890464 # number of integer regfile writes +system.cpu.fp_regfile_reads 6263699 # number of floating regfile reads +system.cpu.fp_regfile_writes 6177982 # number of floating regfile writes +system.cpu.misc_regfile_reads 719169 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 158 # number of replacements -system.cpu.dcache.tags.tagsinuse 1457.375474 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28588753 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1457.358075 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28585648 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2245 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12734.411136 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12733.028062 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1457.375474 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.355805 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.355805 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1457.358075 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.355800 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.355800 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2087 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 137 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 536 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 543 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1389 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.509521 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 57198843 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 57198843 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 22095651 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22095651 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492632 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492632 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 470 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 470 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28588283 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28588283 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28588283 # number of overall hits -system.cpu.dcache.overall_hits::total 28588283 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1074 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1074 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8471 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8471 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 57192649 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 57192649 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 22092545 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22092545 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492630 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492630 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 473 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 473 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28585175 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28585175 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28585175 # number of overall hits +system.cpu.dcache.overall_hits::total 28585175 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1080 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1080 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8473 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8473 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9545 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9545 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9545 # number of overall misses -system.cpu.dcache.overall_misses::total 9545 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 71413000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 71413000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 546757246 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 546757246 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 85000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 85000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 618170246 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 618170246 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 618170246 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 618170246 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22096725 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22096725 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9553 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9553 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9553 # number of overall misses +system.cpu.dcache.overall_misses::total 9553 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 72549500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 72549500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 550211742 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 550211742 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 86000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 86000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 622761242 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 622761242 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 622761242 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 622761242 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22093625 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22093625 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 471 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 471 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28597828 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28597828 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28597828 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28597828 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 474 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 474 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28594728 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28594728 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28594728 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28594728 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000049 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000049 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001303 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001303 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002123 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002123 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002110 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002110 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000334 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000334 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000334 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000334 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66492.551210 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66492.551210 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64544.592846 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64544.592846 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64763.776427 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64763.776427 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64763.776427 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64763.776427 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32543 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 127 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 392 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67175.462963 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67175.462963 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64937.063850 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64937.063850 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 86000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 86000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65190.122684 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65190.122684 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65190.122684 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65190.122684 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 33457 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 131 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 396 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.017857 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 63.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 84.487374 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 65.500000 # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 108 # number of writebacks system.cpu.dcache.writebacks::total 108 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 559 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 559 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6742 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6742 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7301 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7301 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7301 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7301 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 565 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 565 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6744 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6744 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7309 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7309 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7309 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7309 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 515 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 515 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1729 # number of WriteReq MSHR misses @@ -697,154 +697,152 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2244 system.cpu.dcache.demand_mshr_misses::total 2244 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2244 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2244 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39779500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 39779500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 135885995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 135885995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 84000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 84000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 175665495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 175665495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 175665495 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 175665495 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40822500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 40822500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 136978995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 136978995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 85000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 85000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 177801495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 177801495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 177801495 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 177801495 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.002123 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.002123 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.002110 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.002110 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000078 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000078 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77241.747573 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77241.747573 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78592.246964 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78592.246964 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 84000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 84000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78282.306150 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78282.306150 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78282.306150 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78282.306150 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79266.990291 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79266.990291 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79224.404280 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79224.404280 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 85000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 85000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79234.177807 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 79234.177807 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79234.177807 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 79234.177807 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 9515 # number of replacements -system.cpu.icache.tags.tagsinuse 1600.928709 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 15918297 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1600.893985 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 15915792 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 11453 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1389.880119 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1389.661399 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1600.928709 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.781703 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.781703 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1600.893985 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.781687 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.781687 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1938 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 752 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 753 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 944 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 943 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.946289 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 31876857 # Number of tag accesses -system.cpu.icache.tags.data_accesses 31876857 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 15918297 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 15918297 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 15918297 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 15918297 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 15918297 # number of overall hits -system.cpu.icache.overall_hits::total 15918297 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14405 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14405 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14405 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14405 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14405 # number of overall misses -system.cpu.icache.overall_misses::total 14405 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 446574000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 446574000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 446574000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 446574000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 446574000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 446574000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 15932702 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 15932702 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 15932702 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 15932702 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 15932702 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 15932702 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000904 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000904 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000904 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000904 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000904 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000904 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31001.318986 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 31001.318986 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 31001.318986 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 31001.318986 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 31001.318986 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 31001.318986 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 636 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 31871855 # Number of tag accesses +system.cpu.icache.tags.data_accesses 31871855 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 15915792 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 15915792 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 15915792 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 15915792 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 15915792 # number of overall hits +system.cpu.icache.overall_hits::total 15915792 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14409 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14409 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14409 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14409 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14409 # number of overall misses +system.cpu.icache.overall_misses::total 14409 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 447639000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 447639000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 447639000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 447639000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 447639000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 447639000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 15930201 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 15930201 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 15930201 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 15930201 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 15930201 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 15930201 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000905 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000905 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000905 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000905 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000905 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000905 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31066.625026 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 31066.625026 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 31066.625026 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 31066.625026 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 31066.625026 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 31066.625026 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 446 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 159 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 89.200000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 9515 # number of writebacks system.cpu.icache.writebacks::total 9515 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2951 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2951 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2951 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2951 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2951 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2951 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2955 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2955 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2955 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2955 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2955 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2955 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11454 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 11454 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 11454 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 11454 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 11454 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 11454 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 336702000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 336702000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 336702000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 336702000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 336702000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 336702000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 337628000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 337628000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 337628000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 337628000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 337628000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 337628000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000719 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000719 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000719 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000719 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000719 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000719 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29396.018858 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29396.018858 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29396.018858 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 29396.018858 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29396.018858 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 29396.018858 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29476.863978 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29476.863978 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29476.863978 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 29476.863978 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29476.863978 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 29476.863978 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2407.364249 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 18027 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3589 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 5.022848 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 3490.224517 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 18145 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5227 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 3.471399 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.652891 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2008.506649 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 381.204708 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000539 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061295 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.011633 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.073467 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3589 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 909 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.515587 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1482.708930 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061265 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.045249 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.106513 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 5227 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 263 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1371 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.109528 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 192294 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 192294 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3517 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.159515 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 192203 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 192203 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 108 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 108 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 9515 # number of WritebackClean hits @@ -873,18 +871,18 @@ system.cpu.l2cache.demand_misses::total 5227 # nu system.cpu.l2cache.overall_misses::cpu.inst 3062 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2165 # number of overall misses system.cpu.l2cache.overall_misses::total 5227 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 132876500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 132876500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 231097000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 231097000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 38506000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 38506000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 231097000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 171382500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 402479500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 231097000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 171382500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 402479500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 133969500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 133969500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 232023500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 232023500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 39550000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 39550000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 232023500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 173519500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 405543000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 232023500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 173519500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 405543000 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 108 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 108 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 9515 # number of WritebackClean accesses(hits+misses) @@ -913,18 +911,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.381561 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.267330 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964365 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.381561 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78024.955960 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78024.955960 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75472.566950 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75472.566950 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83346.320346 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83346.320346 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75472.566950 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79160.508083 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77000.095657 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75472.566950 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79160.508083 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77000.095657 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78666.764533 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78666.764533 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75775.146963 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75775.146963 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85606.060606 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85606.060606 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75775.146963 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80147.575058 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77586.187105 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75775.146963 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80147.575058 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77586.187105 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -943,18 +941,18 @@ system.cpu.l2cache.demand_mshr_misses::total 5227 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3062 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2165 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5227 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 115846500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 115846500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 200477000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 200477000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 33886000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 33886000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 200477000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 149732500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 350209500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 200477000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 149732500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 350209500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 116939500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 116939500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 201403500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 201403500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 34930000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 34930000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 201403500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151869500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 353273000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 201403500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151869500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 353273000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984962 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984962 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.267330 # mshr miss rate for ReadCleanReq accesses @@ -967,25 +965,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.381561 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.267330 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964365 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.381561 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68024.955960 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68024.955960 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65472.566950 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65472.566950 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73346.320346 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73346.320346 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65472.566950 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69160.508083 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67000.095657 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65472.566950 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69160.508083 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67000.095657 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68666.764533 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68666.764533 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65775.146963 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65775.146963 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75606.060606 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75606.060606 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65775.146963 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70147.575058 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67586.187105 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65775.146963 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70147.575058 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67586.187105 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 23372 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 9673 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 11969 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 108 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 9515 # Transaction distribution @@ -1019,7 +1017,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 17179500 # La system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3367500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 5227 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 3524 # Transaction distribution system.membus.trans_dist::ReadExReq 1703 # Transaction distribution system.membus.trans_dist::ReadExResp 1703 # Transaction distribution @@ -1040,9 +1044,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 5227 # Request fanout histogram -system.membus.reqLayer0.occupancy 6276500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6278000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 27456000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 27461750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index 91b6b6b0a..9382954d5 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.132486 # Number of seconds simulated -sim_ticks 132485848500 # Number of ticks simulated -final_tick 132485848500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.132488 # Number of seconds simulated +sim_ticks 132487590500 # Number of ticks simulated +final_tick 132487590500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 159309 # Simulator instruction rate (inst/s) -host_op_rate 167937 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 122483807 # Simulator tick rate (ticks/s) -host_mem_usage 270152 # Number of bytes of host memory used -host_seconds 1081.66 # Real time elapsed on the host +host_inst_rate 200266 # Simulator instruction rate (inst/s) +host_op_rate 211113 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 153975874 # Simulator tick rate (ticks/s) +host_mem_usage 275560 # Number of bytes of host memory used +host_seconds 860.44 # Real time elapsed on the host sim_insts 172317810 # Number of instructions simulated sim_ops 181650743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 138240 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory system.physmem.bytes_read::total 247552 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 138240 # Nu system.physmem.num_reads::cpu.inst 2160 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory system.physmem.num_reads::total 3868 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1043432 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 825084 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1868517 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1043432 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1043432 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1043432 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 825084 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1868517 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1043418 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 825073 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1868492 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1043418 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1043418 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1043418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 825073 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1868492 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 3868 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 3868 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 132485754500 # Total gap between requests +system.physmem.totGap 132487495500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,8 +91,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 238 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3626 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 233 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 929 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 264.680301 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 173.140302 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 275.634226 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 285 30.68% 30.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 355 38.21% 68.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 86 9.26% 78.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 48 5.17% 83.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 35 3.77% 87.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 24 2.58% 89.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 21 2.26% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 19 2.05% 93.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 56 6.03% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 929 # Bytes accessed per row activation -system.physmem.totQLat 30291250 # Total ticks spent queuing -system.physmem.totMemAccLat 102816250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 926 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 265.468683 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.726650 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 275.485307 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 276 29.81% 29.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 359 38.77% 68.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 87 9.40% 77.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 56 6.05% 84.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 31 3.35% 87.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 22 2.38% 89.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 18 1.94% 91.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 16 1.73% 93.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 61 6.59% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 926 # Bytes accessed per row activation +system.physmem.totQLat 28381250 # Total ticks spent queuing +system.physmem.totMemAccLat 100906250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 19340000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7831.24 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7337.45 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26581.24 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26087.45 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.87 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.87 # Average system read bandwidth in MiByte/s @@ -217,56 +217,56 @@ system.physmem.busUtilRead 0.01 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 2934 # Number of row buffer hits during reads +system.physmem.readRowHits 2936 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.85 # Row buffer hit rate for reads +system.physmem.readRowHitRate 75.90 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34251746.25 # Average gap between requests -system.physmem.pageHitRate 75.85 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3182760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1736625 # Energy for precharge commands per rank (pJ) +system.physmem.avgGap 34252196.35 # Average gap between requests +system.physmem.pageHitRate 75.90 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3190320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1740750 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 16161600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 8653148400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3626588520 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 76308756000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 88609573905 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.835850 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 126944435250 # Time in different power states +system.physmem_0.actBackEnergy 3615176835 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 76318766250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 88608184155 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.825360 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 126962854750 # Time in different power states system.physmem_0.memoryStateTime::REF 4423900000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1115186250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1098483750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3825360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2087250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 13790400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3795120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2070750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13782600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 8653148400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3635416395 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 76301020500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 88609288305 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.833625 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 126931702750 # Time in different power states +system.physmem_1.actBackEnergy 3628387440 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 76307186250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 88608370560 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.826698 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 126942838750 # Time in different power states system.physmem_1.memoryStateTime::REF 4423900000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1127787750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1117460750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 49693791 # Number of BP lookups -system.cpu.branchPred.condPredicted 39499604 # Number of conditional branches predicted +system.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 49693795 # Number of BP lookups +system.cpu.branchPred.condPredicted 39499605 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 5516746 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24160971 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 24160974 # Number of BTB lookups system.cpu.branchPred.BTBHits 22899506 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.778914 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1894448 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 94.778903 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1894449 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 142 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 213843 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 208090 # Number of indirect target hits. system.cpu.branchPred.indirectMisses 5753 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 40382 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -296,7 +296,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -326,7 +326,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -356,7 +356,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -387,16 +387,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 132485848500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 264971697 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 132487590500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 264975181 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 172317810 # Number of instructions committed system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed -system.cpu.discardedOps 11524051 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 11524054 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.537692 # CPI: cycles per instruction -system.cpu.ipc 0.650325 # IPC: instructions per cycle +system.cpu.cpi 1.537712 # CPI: cycles per instruction +system.cpu.ipc 0.650317 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 138988213 76.51% 76.51% # Class of committed instruction system.cpu.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction @@ -432,18 +432,18 @@ system.cpu.op_class_0::MemWrite 12644635 6.96% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 181650743 # Class of committed instruction -system.cpu.tickCycles 256731546 # Number of cycles that the object actually ticked -system.cpu.idleCycles 8240151 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 256731939 # Number of cycles that the object actually ticked +system.cpu.idleCycles 8243242 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1378.678714 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40755400 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1378.670840 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40755401 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1811 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22504.362231 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22504.362783 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1378.678714 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.336591 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.336591 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1378.670840 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.336590 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.336590 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1769 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id @@ -451,11 +451,11 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1359 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.431885 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 81517417 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 81517417 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 28347488 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28347488 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 81517419 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 81517419 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 28347489 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28347489 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 12362636 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 12362636 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits @@ -464,10 +464,10 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40710124 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40710124 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40710586 # number of overall hits -system.cpu.dcache.overall_hits::total 40710586 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 40710125 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40710125 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40710587 # number of overall hits +system.cpu.dcache.overall_hits::total 40710587 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 751 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 751 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1651 # number of WriteReq misses @@ -478,16 +478,16 @@ system.cpu.dcache.demand_misses::cpu.data 2402 # n system.cpu.dcache.demand_misses::total 2402 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2403 # number of overall misses system.cpu.dcache.overall_misses::total 2403 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 55315500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 55315500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 127182500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 127182500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 182498000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 182498000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 182498000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 182498000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28348239 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28348239 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 55860000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 55860000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 128578000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 128578000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 184438000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 184438000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 184438000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 184438000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28348240 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28348240 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses) @@ -496,10 +496,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 40712526 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 40712526 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 40712989 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 40712989 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 40712527 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 40712527 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 40712990 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 40712990 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000134 # miss rate for WriteReq accesses @@ -510,14 +510,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000059 system.cpu.dcache.demand_miss_rate::total 0.000059 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000059 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000059 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73655.792277 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 73655.792277 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77033.615990 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 77033.615990 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 75977.518734 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 75977.518734 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 75945.900957 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 75945.900957 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74380.825566 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 74380.825566 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77878.861296 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77878.861296 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76785.179017 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76785.179017 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76753.225135 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76753.225135 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -544,16 +544,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1810 system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1811 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1811 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52182500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 52182500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86133500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 86133500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 70000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 70000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 138316000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 138316000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138386000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 138386000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52704000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 52704000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 87045000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 87045000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 71000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 71000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 139749000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 139749000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 139820000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 139820000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses @@ -564,26 +564,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73393.108298 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73393.108298 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78374.431301 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78374.431301 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76417.679558 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76417.679558 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76414.135837 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76414.135837 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74126.582278 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74126.582278 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79203.821656 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79203.821656 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77209.392265 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77209.392265 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77205.963556 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77205.963556 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 2864 # number of replacements -system.cpu.icache.tags.tagsinuse 1424.966015 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1424.957423 # Cycle average of tags in use system.cpu.icache.tags.total_refs 70941364 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4663 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 15213.674459 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1424.966015 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.695784 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.695784 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1424.957423 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.695780 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.695780 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1799 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id @@ -593,7 +593,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1069 system.cpu.icache.tags.occ_task_id_percent::1024 0.878418 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 141896719 # Number of tag accesses system.cpu.icache.tags.data_accesses 141896719 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 70941364 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 70941364 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 70941364 # number of demand (read+write) hits @@ -606,12 +606,12 @@ system.cpu.icache.demand_misses::cpu.inst 4664 # n system.cpu.icache.demand_misses::total 4664 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 4664 # number of overall misses system.cpu.icache.overall_misses::total 4664 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 200959500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 200959500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 200959500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 200959500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 200959500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 200959500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 201505000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 201505000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 201505000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 201505000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 201505000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 201505000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 70946028 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 70946028 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 70946028 # number of demand (read+write) accesses @@ -624,12 +624,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43087.371355 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 43087.371355 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 43087.371355 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 43087.371355 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 43087.371355 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 43087.371355 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43204.331046 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 43204.331046 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 43204.331046 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 43204.331046 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 43204.331046 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 43204.331046 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -644,48 +644,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4664 system.cpu.icache.demand_mshr_misses::total 4664 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4664 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4664 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 196296500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 196296500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 196296500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 196296500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 196296500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 196296500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 196842000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 196842000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 196842000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 196842000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 196842000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 196842000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42087.585763 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42087.585763 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42087.585763 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 42087.585763 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42087.585763 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 42087.585763 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42204.545455 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42204.545455 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42204.545455 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 42204.545455 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42204.545455 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 42204.545455 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2000.553914 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5137 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2785 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.844524 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2835.484229 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5160 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3868 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.334023 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 3.029612 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.714154 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 489.810148 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046012 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.014948 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.061052 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 2785 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 520 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 156 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2004 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084991 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 76244 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 76244 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.704814 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1327.779416 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046011 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.040521 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.086532 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3868 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 533 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 366 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2841 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.118042 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 76228 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 76228 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 2534 # number of WritebackClean hits @@ -714,18 +712,18 @@ system.cpu.l2cache.demand_misses::total 3885 # nu system.cpu.l2cache.overall_misses::cpu.inst 2162 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1723 # number of overall misses system.cpu.l2cache.overall_misses::total 3885 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84399500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 84399500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 162646500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 162646500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 50260000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 50260000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 162646500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 134659500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 297306000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 162646500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 134659500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 297306000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 85311000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 85311000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 163192000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 163192000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 50782500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 50782500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 163192000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 136093500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 299285500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 163192000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 136093500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 299285500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 2534 # number of WritebackClean accesses(hits+misses) @@ -754,18 +752,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.600000 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463551 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.951408 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.600000 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77359.761687 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77359.761687 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75229.648474 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75229.648474 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79525.316456 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79525.316456 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75229.648474 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78154.091701 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76526.640927 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75229.648474 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78154.091701 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76526.640927 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78195.233731 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78195.233731 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75481.961147 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75481.961147 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80352.056962 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80352.056962 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75481.961147 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78986.360998 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77036.164736 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75481.961147 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78986.360998 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77036.164736 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -794,18 +792,18 @@ system.cpu.l2cache.demand_mshr_misses::total 3869 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2161 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3869 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 73489500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 73489500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 140980000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 140980000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 43051500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 43051500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 140980000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 116541000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 257521000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 140980000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 116541000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 257521000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 74401000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 74401000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 141524500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 141524500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 43559000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 43559000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 141524500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 117960000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 259484500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 141524500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 117960000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 259484500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992721 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992721 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for ReadCleanReq accesses @@ -818,25 +816,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.597529 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.597529 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67359.761687 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67359.761687 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65238.315595 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65238.315595 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69775.526742 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69775.526742 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65238.315595 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68232.435597 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66560.093047 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65238.315595 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68232.435597 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66560.093047 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68195.233731 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68195.233731 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65490.282277 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65490.282277 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70598.055105 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70598.055105 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65490.282277 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69063.231850 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67067.588524 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65490.282277 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69063.231850 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67067.588524 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 9381 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 3042 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 336 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 5375 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 2864 # Transaction distribution @@ -870,7 +868,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 6994999 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2723985 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 3868 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 2777 # Transaction distribution system.membus.trans_dist::ReadExReq 1091 # Transaction distribution system.membus.trans_dist::ReadExResp 1091 # Transaction distribution @@ -891,9 +895,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 3868 # Request fanout histogram -system.membus.reqLayer0.occupancy 4518000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4519500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 20557500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20563000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 46c589cfc..834ad990c 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.084938 # Number of seconds simulated -sim_ticks 84937723500 # Number of ticks simulated -final_tick 84937723500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.085052 # Number of seconds simulated +sim_ticks 85051506000 # Number of ticks simulated +final_tick 85051506000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 178410 # Simulator instruction rate (inst/s) -host_op_rate 188074 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 87948168 # Simulator tick rate (ticks/s) -host_mem_usage 268236 # Number of bytes of host memory used -host_seconds 965.77 # Real time elapsed on the host +host_inst_rate 137318 # Simulator instruction rate (inst/s) +host_op_rate 144756 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67782320 # Simulator tick rate (ticks/s) +host_mem_usage 272616 # Number of bytes of host memory used +host_seconds 1254.77 # Real time elapsed on the host sim_insts 172303022 # Number of instructions simulated sim_ops 181635954 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 587328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 132096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 70976 # Number of bytes read from this memory -system.physmem.bytes_read::total 790400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 587328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 587328 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 9177 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2064 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 1109 # Number of read requests responded to by this memory -system.physmem.num_reads::total 12350 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 6914807 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1555210 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 835624 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9305641 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6914807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6914807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6914807 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1555210 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 835624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9305641 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 12351 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 651584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 192256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 71040 # Number of bytes read from this memory +system.physmem.bytes_read::total 914880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 651584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 651584 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 10181 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3004 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 1110 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14295 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 7661052 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2260466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 835259 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10756776 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7661052 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7661052 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7661052 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2260466 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 835259 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10756776 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 14295 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 12351 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 14295 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 790464 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 914880 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 790464 # Total read bytes from the system interface side +system.physmem.bytesReadSys 914880 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1113 # Per bank write bursts -system.physmem.perBankRdBursts::1 381 # Per bank write bursts -system.physmem.perBankRdBursts::2 5089 # Per bank write bursts -system.physmem.perBankRdBursts::3 423 # Per bank write bursts -system.physmem.perBankRdBursts::4 1959 # Per bank write bursts +system.physmem.perBankRdBursts::0 1374 # Per bank write bursts +system.physmem.perBankRdBursts::1 495 # Per bank write bursts +system.physmem.perBankRdBursts::2 5094 # Per bank write bursts +system.physmem.perBankRdBursts::3 807 # Per bank write bursts +system.physmem.perBankRdBursts::4 2274 # Per bank write bursts system.physmem.perBankRdBursts::5 424 # Per bank write bursts -system.physmem.perBankRdBursts::6 265 # Per bank write bursts -system.physmem.perBankRdBursts::7 373 # Per bank write bursts -system.physmem.perBankRdBursts::8 266 # Per bank write bursts -system.physmem.perBankRdBursts::9 219 # Per bank write bursts -system.physmem.perBankRdBursts::10 295 # Per bank write bursts -system.physmem.perBankRdBursts::11 324 # Per bank write bursts -system.physmem.perBankRdBursts::12 199 # Per bank write bursts -system.physmem.perBankRdBursts::13 249 # Per bank write bursts -system.physmem.perBankRdBursts::14 229 # Per bank write bursts -system.physmem.perBankRdBursts::15 543 # Per bank write bursts +system.physmem.perBankRdBursts::6 384 # Per bank write bursts +system.physmem.perBankRdBursts::7 621 # Per bank write bursts +system.physmem.perBankRdBursts::8 270 # Per bank write bursts +system.physmem.perBankRdBursts::9 230 # Per bank write bursts +system.physmem.perBankRdBursts::10 354 # Per bank write bursts +system.physmem.perBankRdBursts::11 348 # Per bank write bursts +system.physmem.perBankRdBursts::12 319 # Per bank write bursts +system.physmem.perBankRdBursts::13 267 # Per bank write bursts +system.physmem.perBankRdBursts::14 239 # Per bank write bursts +system.physmem.perBankRdBursts::15 795 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -80,14 +80,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 84937714500 # Total gap between requests +system.physmem.totGap 85051447500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 12351 # Read request sizes (log2) +system.physmem.readPktSize::6 14295 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -95,15 +95,15 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 10935 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 975 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 12841 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1014 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 173 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 85 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see @@ -191,86 +191,86 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 7250 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 108.738207 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 85.269087 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 131.624325 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 5249 72.40% 72.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 1564 21.57% 93.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 167 2.30% 96.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 93 1.28% 97.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 42 0.58% 98.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 24 0.33% 98.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 18 0.25% 98.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 21 0.29% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 72 0.99% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 7250 # Bytes accessed per row activation -system.physmem.totQLat 171430514 # Total ticks spent queuing -system.physmem.totMemAccLat 403011764 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 61755000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13879.89 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 8758 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 104.242978 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 83.732821 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 121.093987 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 6415 73.25% 73.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 1879 21.45% 94.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 191 2.18% 96.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 97 1.11% 97.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 35 0.40% 98.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 31 0.35% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 21 0.24% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 17 0.19% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 72 0.82% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 8758 # Bytes accessed per row activation +system.physmem.totQLat 205669486 # Total ticks spent queuing +system.physmem.totMemAccLat 473700736 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 71475000 # Total ticks spent in databus transfers +system.physmem.avgQLat 14387.51 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32629.89 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 9.31 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 33137.51 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 10.76 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 9.31 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 10.76 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.07 # Data bus utilization in percentage -system.physmem.busUtilRead 0.07 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.08 # Data bus utilization in percentage +system.physmem.busUtilRead 0.08 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 5094 # Number of row buffer hits during reads +system.physmem.readRowHits 5530 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 41.24 # Row buffer hit rate for reads +system.physmem.readRowHitRate 38.68 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 6876990.89 # Average gap between requests -system.physmem.pageHitRate 41.24 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 48452040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 26437125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 78179400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 5949734.00 # Average gap between requests +system.physmem.pageHitRate 38.68 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 56571480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 30867375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 89442600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5547372480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 16645874445 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 36357960750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 58704276240 # Total energy per rank (pJ) -system.physmem_0.averagePower 691.186004 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 60381088491 # Time in different power states -system.physmem_0.memoryStateTime::REF 2836080000 # Time in different power states +system.physmem_0.refreshEnergy 5555000880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 17335593540 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 35823020250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 58890496125 # Total energy per rank (pJ) +system.physmem_0.averagePower 692.426384 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 59484367239 # Time in different power states +system.physmem_0.memoryStateTime::REF 2839980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 21718991509 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22725351261 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6335280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3456750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 17877600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 9616320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 5247000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 21801000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5547372480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3295031490 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 48069226500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 56939300100 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.405119 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 79958437412 # Time in different power states -system.physmem_1.memoryStateTime::REF 2836080000 # Time in different power states +system.physmem_1.refreshEnergy 5555000880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4216606920 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 47330903250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 57139175370 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.834595 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 78723898183 # Time in different power states +system.physmem_1.memoryStateTime::REF 2839980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2138239588 # Time in different power states +system.physmem_1.memoryStateTime::ACT 3485604317 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 85626366 # Number of BP lookups -system.cpu.branchPred.condPredicted 68177013 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5935452 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 39946926 # Number of BTB lookups -system.cpu.branchPred.BTBHits 38187698 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 85633597 # Number of BP lookups +system.cpu.branchPred.condPredicted 68181299 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5935035 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 39958046 # Number of BTB lookups +system.cpu.branchPred.BTBHits 38197568 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.596087 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3683716 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 81912 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 681689 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 653746 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 27943 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 40316 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 95.594184 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3683467 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 81914 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 681978 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 654112 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 27866 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 40296 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -300,7 +300,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -330,7 +330,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -360,7 +360,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -391,97 +391,97 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 84937723500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 169875448 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 85051506000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 170103013 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5671940 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 347162762 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85626366 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42525160 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 157499775 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 11884731 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 2609 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 5682904 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 347166765 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85633597 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42535147 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 157608501 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11884039 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2048 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 3808 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 78326624 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 18246 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 169120520 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.147875 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.049260 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3989 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 78333693 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 18018 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 169239484 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.146393 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.050401 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 17456404 10.32% 10.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30071791 17.78% 28.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31598997 18.68% 46.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 89993328 53.21% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 17572638 10.38% 10.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30072408 17.77% 28.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31601234 18.67% 46.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 89993204 53.18% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 169120520 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.504054 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.043631 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17509987 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 17244874 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 121866560 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6731455 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5767644 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11064434 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 189777 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 304997911 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27240618 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5767644 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37477523 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8502539 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 578983 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 108355768 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8438063 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 277420851 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13180734 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3058487 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 843003 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2280960 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 36243 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 27083 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 481449871 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1187780717 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 296461789 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3004325 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 169239484 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.503422 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.040921 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17519961 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 17356982 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 121861075 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6734206 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5767260 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11064637 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 189821 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 304987544 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27243895 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5767260 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37487022 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8574296 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 598391 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 108353196 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8459319 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 277412346 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13179472 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3059617 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 843440 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2298708 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 38369 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 27077 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 481431446 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1187749796 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 296450503 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3005240 # Number of floating rename lookups system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 188472942 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 23603 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23603 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13353784 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 33915046 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14407100 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2540378 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1803003 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 263798584 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 45955 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 214411803 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5187874 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 82208585 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 216955908 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 739 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 169120520 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.267805 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.017994 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 188454517 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 23636 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23644 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13356506 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 33916395 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14406588 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2541453 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1809916 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 263792468 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 45987 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 214404594 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5189732 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 82202501 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 216956580 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 771 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 169239484 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.266871 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.018138 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52408217 30.99% 30.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 35940187 21.25% 52.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 65510990 38.74% 90.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 13642635 8.07% 99.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1570936 0.93% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 47343 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 212 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52525006 31.04% 31.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 35947009 21.24% 52.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 65510390 38.71% 90.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13639375 8.06% 99.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1570056 0.93% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 47432 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 216 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 169120520 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 169239484 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35659439 66.16% 66.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 153265 0.28% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35663808 66.17% 66.17% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 153282 0.28% 66.45% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 66.45% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.45% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.45% # attempts to use FU when none available @@ -500,22 +500,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.45% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 66.45% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.45% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 1066 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 1064 0.00% 66.45% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 35730 0.07% 66.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 240 0.00% 66.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 35736 0.07% 66.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 239 0.00% 66.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.52% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 958 0.00% 66.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 34286 0.06% 66.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 14056522 26.08% 92.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3955910 7.34% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 34308 0.06% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 14056089 26.08% 92.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3953676 7.34% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 166992897 77.88% 77.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 919175 0.43% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 166984371 77.88% 77.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 919276 0.43% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.31% # Type of FU issued @@ -534,91 +534,91 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.31% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33015 0.02% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33022 0.02% 78.33% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 165179 0.08% 78.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 245702 0.11% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 460499 0.21% 78.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206683 0.10% 78.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 165180 0.08% 78.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 245718 0.11% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 460481 0.21% 78.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206631 0.10% 78.87% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.90% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 31868874 14.86% 93.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13371819 6.24% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 31870339 14.86% 93.76% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13371616 6.24% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 214411803 # Type of FU issued -system.cpu.iq.rate 1.262171 # Inst issue rate -system.cpu.iq.fu_busy_cnt 53897621 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.251374 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 653076785 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 344050437 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 204251594 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3952836 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2009578 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1806333 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266175663 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2133761 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1598827 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 214404594 # Type of FU issued +system.cpu.iq.rate 1.260440 # Inst issue rate +system.cpu.iq.fu_busy_cnt 53899365 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.251391 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 653186184 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 344036614 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 204245973 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3951585 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2011286 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1806392 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266171590 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2132369 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1599233 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6018902 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7447 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7034 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1762466 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6020251 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7425 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7087 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1761954 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 25527 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 769 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 25499 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 790 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5767644 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5618767 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 62916 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 263864756 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 5767260 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5621824 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 63176 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 263858489 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 33915046 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14407100 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23547 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3855 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 55872 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7034 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3149041 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3246654 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6395695 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 207125960 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 30633355 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7285843 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 33916395 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14406588 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23579 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3874 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 56135 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 7087 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3147809 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3246868 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6394677 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 207120469 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 30635063 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7284125 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 20217 # number of nop insts executed -system.cpu.iew.exec_refs 43771495 # number of memory reference insts executed -system.cpu.iew.exec_branches 44852998 # Number of branches executed -system.cpu.iew.exec_stores 13138140 # Number of stores executed -system.cpu.iew.exec_rate 1.219281 # Inst execution rate -system.cpu.iew.wb_sent 206368045 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 206057927 # cumulative count of insts written-back -system.cpu.iew.wb_producers 129397136 # num instructions producing a value -system.cpu.iew.wb_consumers 221651580 # num instructions consuming a value -system.cpu.iew.wb_rate 1.212994 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.583786 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 68672645 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 20034 # number of nop insts executed +system.cpu.iew.exec_refs 43773548 # number of memory reference insts executed +system.cpu.iew.exec_branches 44851099 # Number of branches executed +system.cpu.iew.exec_stores 13138485 # Number of stores executed +system.cpu.iew.exec_rate 1.217618 # Inst execution rate +system.cpu.iew.wb_sent 206362307 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 206052365 # cumulative count of insts written-back +system.cpu.iew.wb_producers 129396792 # num instructions producing a value +system.cpu.iew.wb_consumers 221653711 # num instructions consuming a value +system.cpu.iew.wb_rate 1.211339 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.583779 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 68665439 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5760731 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 157823719 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.150970 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.652577 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5760276 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 157944348 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.150091 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.652266 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 73232232 46.40% 46.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 41142749 26.07% 72.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 22534270 14.28% 86.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9514853 6.03% 92.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3552076 2.25% 95.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2143258 1.36% 96.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1327703 0.84% 97.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1008942 0.64% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3367636 2.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 73354007 46.44% 46.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 41142542 26.05% 72.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 22532573 14.27% 86.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9515365 6.02% 92.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3551587 2.25% 95.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2142504 1.36% 96.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1329210 0.84% 97.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1010049 0.64% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3366511 2.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 157823719 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 157944348 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317410 # Number of instructions committed system.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -664,83 +664,83 @@ system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 181650342 # Class of committed instruction -system.cpu.commit.bw_lim_events 3367636 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 404773869 # The number of ROB reads -system.cpu.rob.rob_writes 511956769 # The number of ROB writes -system.cpu.timesIdled 9030 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 754928 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3366511 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 404888417 # The number of ROB reads +system.cpu.rob.rob_writes 511940612 # The number of ROB writes +system.cpu.timesIdled 9843 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 863529 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303022 # Number of Instructions Simulated system.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.985911 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.985911 # CPI: Total CPI of All Threads -system.cpu.ipc 1.014290 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.014290 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 218725741 # number of integer regfile reads -system.cpu.int_regfile_writes 114168991 # number of integer regfile writes -system.cpu.fp_regfile_reads 2904222 # number of floating regfile reads -system.cpu.fp_regfile_writes 2441435 # number of floating regfile writes -system.cpu.cc_regfile_reads 708194084 # number of cc regfile reads -system.cpu.cc_regfile_writes 229512691 # number of cc regfile writes -system.cpu.misc_regfile_reads 57440842 # number of misc regfile reads +system.cpu.cpi 0.987232 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.987232 # CPI: Total CPI of All Threads +system.cpu.ipc 1.012933 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.012933 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 218721236 # number of integer regfile reads +system.cpu.int_regfile_writes 114166498 # number of integer regfile writes +system.cpu.fp_regfile_reads 2904044 # number of floating regfile reads +system.cpu.fp_regfile_writes 2441835 # number of floating regfile writes +system.cpu.cc_regfile_reads 708181937 # number of cc regfile reads +system.cpu.cc_regfile_writes 229500026 # number of cc regfile writes +system.cpu.misc_regfile_reads 57441519 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 72581 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.413915 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 41031177 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 73093 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 561.355766 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 508221500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.413915 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998855 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998855 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 72593 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.410345 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 41032184 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 73105 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 561.277396 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 509673500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.410345 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998848 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998848 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 229 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 160 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 230 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 44 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 82360603 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 82360603 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 28644947 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28644947 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12341311 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12341311 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 82362697 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 82362697 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 28645946 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28645946 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12341320 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12341320 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 364 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 364 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22148 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22148 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22147 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22147 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40986258 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40986258 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40986622 # number of overall hits -system.cpu.dcache.overall_hits::total 40986622 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89227 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89227 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 22976 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 22976 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 40987266 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40987266 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40987630 # number of overall hits +system.cpu.dcache.overall_hits::total 40987630 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89269 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89269 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 22967 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22967 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 116 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 116 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 259 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 259 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 112203 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 112203 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 112319 # number of overall misses -system.cpu.dcache.overall_misses::total 112319 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1066843000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1066843000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 241030499 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 241030499 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2297500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 2297500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1307873499 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1307873499 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1307873499 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1307873499 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28734174 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28734174 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_misses::cpu.data 260 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 260 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 112236 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 112236 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 112352 # number of overall misses +system.cpu.dcache.overall_misses::total 112352 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1192862000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1192862000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 244207999 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 244207999 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2309000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 2309000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1437069999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1437069999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1437069999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1437069999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28735215 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28735215 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 480 # number of SoftPFReq accesses(hits+misses) @@ -749,70 +749,70 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41098461 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41098461 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41098941 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41098941 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003105 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003105 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 41099502 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41099502 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41099982 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41099982 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003107 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003107 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001858 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001858 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.241667 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.241667 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011559 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011559 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002730 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002730 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002733 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002733 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11956.504197 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11956.504197 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10490.533557 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10490.533557 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8870.656371 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8870.656371 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 11656.314885 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 11656.314885 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 11644.276561 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 11644.276561 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 166 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 10738 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011604 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011604 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002731 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002731 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002734 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002734 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13362.555870 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13362.555870 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10632.995123 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10632.995123 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8880.769231 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8880.769231 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12804.002272 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12804.002272 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12790.782532 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12790.782532 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 168 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 10626 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 864 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 83 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 12.428241 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 72581 # number of writebacks -system.cpu.dcache.writebacks::total 72581 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24802 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 24802 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14421 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 14421 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 259 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 259 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 39223 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 39223 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 39223 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 39223 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64425 # 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Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 278 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 49 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 156707315 # Number of tag accesses -system.cpu.icache.tags.data_accesses 156707315 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 78269055 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78269055 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78269055 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78269055 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78269055 # 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average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 73195 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 27 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3246 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21637.884494 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21637.884494 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21637.884494 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21637.884494 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21637.884494 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21637.884494 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 76503 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 31 # 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average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19208.778853 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19208.778853 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 9269 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 9269 # number of prefetch candidates identified +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20772.141274 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20772.141274 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20772.141274 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20772.141274 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20772.141274 # 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Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 121 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 2706 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 24 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 87 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 141 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 856 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 162 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1653 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.015503 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 199 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 957 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.007385 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.165161 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 4005348 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4005348 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 64707 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 64707 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 51067 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 51067 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 8388 # 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number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 17183500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 17183500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 720935500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 720935500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 202978500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 202978500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 720935500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 220162000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 941097500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 720935500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 220162000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 66910636 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1008008136 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027140 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027140 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.169536 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.169536 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.028385 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.028385 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.169536 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.028238 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.088360 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.169536 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.028238 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027365 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027365 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.188015 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.188015 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.042927 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.042927 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.188015 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.041092 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.103611 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.188015 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.041092 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.104135 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34294.294469 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 34294.294469 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70476.495726 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70476.495726 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69132.327304 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69132.327304 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71733.333333 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71733.333333 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69132.327304 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71590.843023 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69583.703967 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69132.327304 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71590.843023 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34294.294469 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64237.953732 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 253433 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 126224 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10473 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 11905 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3377 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 8528 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 118606 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 64698 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 61506 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 11007 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 2350 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 8622 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 8622 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 54136 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 64471 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 161894 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218767 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 380661 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6896512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9323136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 16219648 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 13357 # Total snoops (count) +system.cpu.l2cache.overall_mshr_miss_rate::total 0.119437 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33222.758689 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 33222.758689 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72811.440678 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72811.440678 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70811.855417 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70811.855417 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73330.382948 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73330.382948 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70811.855417 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73289.613848 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71376.374668 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70811.855417 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73289.613848 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33222.758689 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66320.687940 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 253485 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 126250 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10456 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 904 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 903 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 118630 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 64707 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 61523 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 2352 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 8624 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 8624 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 54150 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 64481 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 161936 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218803 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 380739 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6898304 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9324672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 16222976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2352 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 140586 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.219979 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.541213 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 129607 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.087812 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.283049 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 118188 84.07% 84.07% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 13870 9.87% 93.93% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 8528 6.07% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 118227 91.22% 91.22% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 11379 8.78% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 140586 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 252920500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 129607 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 252972500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 81207989 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 81228989 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 109644490 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 109661492 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 12116 # Transaction distribution -system.membus.trans_dist::ReadExReq 234 # Transaction distribution -system.membus.trans_dist::ReadExResp 234 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 12117 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 24701 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 24701 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 790400 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 790400 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 14295 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 10463 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 14059 # Transaction distribution +system.membus.trans_dist::ReadExReq 236 # Transaction distribution +system.membus.trans_dist::ReadExResp 236 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 14059 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 28590 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28590 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 914880 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 914880 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 12351 # Request fanout histogram +system.membus.snoop_fanout::samples 14295 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 12351 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 14295 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 12351 # Request fanout histogram -system.membus.reqLayer0.occupancy 15618188 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 14295 # Request fanout histogram +system.membus.reqLayer0.occupancy 18052130 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 66520835 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 77159307 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index d24e062d1..c2d15923a 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.103324 # Number of seconds simulated -sim_ticks 103324153500 # Number of ticks simulated -final_tick 103324153500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.103278 # Number of seconds simulated +sim_ticks 103278421500 # Number of ticks simulated +final_tick 103278421500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 51505 # Simulator instruction rate (inst/s) -host_op_rate 86327 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40294413 # Simulator tick rate (ticks/s) -host_mem_usage 304184 # Number of bytes of host memory used -host_seconds 2564.23 # Real time elapsed on the host +host_inst_rate 68420 # Simulator instruction rate (inst/s) +host_op_rate 114678 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53503682 # Simulator tick rate (ticks/s) +host_mem_usage 309068 # Number of bytes of host memory used +host_seconds 1930.31 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 231488 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 232192 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 130496 # Number of bytes read from this memory -system.physmem.bytes_read::total 361984 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 231488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 231488 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3617 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 362688 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 232192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 232192 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3628 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2039 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5656 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2240405 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1262977 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3503382 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2240405 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2240405 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2240405 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1262977 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3503382 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5656 # Number of read requests accepted +system.physmem.num_reads::total 5667 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2248214 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1263536 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3511750 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2248214 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2248214 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2248214 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1263536 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3511750 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5668 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5656 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5668 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 361984 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 362752 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 361984 # Total read bytes from the system interface side +system.physmem.bytesReadSys 362752 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 310 # Per bank write bursts -system.physmem.perBankRdBursts::1 382 # Per bank write bursts -system.physmem.perBankRdBursts::2 476 # Per bank write bursts -system.physmem.perBankRdBursts::3 358 # Per bank write bursts -system.physmem.perBankRdBursts::4 362 # Per bank write bursts -system.physmem.perBankRdBursts::5 335 # Per bank write bursts -system.physmem.perBankRdBursts::6 419 # Per bank write bursts -system.physmem.perBankRdBursts::7 385 # Per bank write bursts +system.physmem.perBankRdBursts::0 314 # Per bank write bursts +system.physmem.perBankRdBursts::1 385 # Per bank write bursts +system.physmem.perBankRdBursts::2 471 # Per bank write bursts +system.physmem.perBankRdBursts::3 359 # Per bank write bursts +system.physmem.perBankRdBursts::4 360 # Per bank write bursts +system.physmem.perBankRdBursts::5 334 # Per bank write bursts +system.physmem.perBankRdBursts::6 420 # Per bank write bursts +system.physmem.perBankRdBursts::7 393 # Per bank write bursts system.physmem.perBankRdBursts::8 389 # Per bank write bursts -system.physmem.perBankRdBursts::9 295 # Per bank write bursts -system.physmem.perBankRdBursts::10 260 # Per bank write bursts -system.physmem.perBankRdBursts::11 270 # Per bank write bursts -system.physmem.perBankRdBursts::12 228 # Per bank write bursts -system.physmem.perBankRdBursts::13 484 # Per bank write bursts -system.physmem.perBankRdBursts::14 420 # Per bank write bursts +system.physmem.perBankRdBursts::9 296 # Per bank write bursts +system.physmem.perBankRdBursts::10 257 # Per bank write bursts +system.physmem.perBankRdBursts::11 272 # Per bank write bursts +system.physmem.perBankRdBursts::12 232 # Per bank write bursts +system.physmem.perBankRdBursts::13 487 # Per bank write bursts +system.physmem.perBankRdBursts::14 416 # Per bank write bursts system.physmem.perBankRdBursts::15 283 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 103323899000 # Total gap between requests +system.physmem.totGap 103278386000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5656 # Read request sizes (log2) +system.physmem.readPktSize::6 5668 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,12 +91,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4508 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 949 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4530 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 947 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -187,321 +187,321 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1264 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 286.278481 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 164.439317 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 318.670037 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 554 43.83% 43.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 264 20.89% 64.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 105 8.31% 73.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 69 5.46% 78.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 45 3.56% 82.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 57 4.51% 86.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 28 2.22% 88.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 17 1.34% 90.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 125 9.89% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1264 # Bytes accessed per row activation -system.physmem.totQLat 43672750 # Total ticks spent queuing -system.physmem.totMemAccLat 149722750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 28280000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7721.49 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1276 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 283.335423 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 163.570090 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 315.354372 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 562 44.04% 44.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 260 20.38% 64.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 126 9.87% 74.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 65 5.09% 79.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 38 2.98% 82.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 52 4.08% 86.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 32 2.51% 88.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 25 1.96% 90.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 116 9.09% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1276 # Bytes accessed per row activation +system.physmem.totQLat 44968750 # Total ticks spent queuing +system.physmem.totMemAccLat 151243750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 28340000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7933.79 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26471.49 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.50 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26683.79 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.51 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.50 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4391 # Number of row buffer hits during reads +system.physmem.readRowHits 4387 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.63 # Row buffer hit rate for reads +system.physmem.readRowHitRate 77.40 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 18268016.09 # Average gap between requests -system.physmem.pageHitRate 77.63 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5624640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3069000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 23610600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 18221310.16 # Average gap between requests +system.physmem.pageHitRate 77.40 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5677560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3097875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 23649600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 6748591200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3147948405 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 59232949500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 69161793345 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.369133 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 98535205500 # Time in different power states -system.physmem_0.memoryStateTime::REF 3450200000 # Time in different power states +system.physmem_0.refreshEnergy 6745539840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3123252585 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 59226559500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 69127776960 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.342795 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 98524507750 # Time in different power states +system.physmem_0.memoryStateTime::REF 3448640000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1338454000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1303957250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3931200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2145000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 20490600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3969000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2165625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 20412600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 6748591200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2964574845 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 59393774250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 69133507095 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.095685 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 98803806250 # Time in different power states -system.physmem_1.memoryStateTime::REF 3450200000 # Time in different power states +system.physmem_1.refreshEnergy 6745539840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3000772125 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 59333991750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 69106850940 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.140248 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 98704275500 # Time in different power states +system.physmem_1.memoryStateTime::REF 3448640000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1069805000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1124404000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 40908032 # Number of BP lookups -system.cpu.branchPred.condPredicted 40908032 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6741329 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 35316490 # Number of BTB lookups +system.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 40909998 # Number of BP lookups +system.cpu.branchPred.condPredicted 40909998 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6747980 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 35338690 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3206071 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 604531 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 35316490 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 9869044 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 25447446 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 5035252 # Number of mispredicted indirect branches. +system.cpu.branchPred.usedRAS 3198330 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 606499 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 35338690 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 9879284 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 25459406 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 5040736 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 103324153500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 206648308 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 103278421500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 206556844 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 46351281 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 420030465 # Number of instructions fetch has processed -system.cpu.fetch.Branches 40908032 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13075115 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 152558958 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14935189 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 126 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 5881 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 68758 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 764 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 179 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 41261989 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1525874 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 8 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 206453541 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.416062 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.660543 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 46378865 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 420308215 # Number of instructions fetch has processed +system.cpu.fetch.Branches 40909998 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13077614 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 152415438 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14966481 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 135 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 5953 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 72789 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 564 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 110 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 41283191 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1528436 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 206357094 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.419964 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.660932 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 99211398 48.06% 48.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5135847 2.49% 50.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5374620 2.60% 53.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5328555 2.58% 55.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 6013612 2.91% 58.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5856529 2.84% 61.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5733209 2.78% 64.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4747222 2.30% 66.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 69052549 33.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 99044157 48.00% 48.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5139433 2.49% 50.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5380650 2.61% 53.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5336666 2.59% 55.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 6016483 2.92% 58.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5851353 2.84% 61.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5736237 2.78% 64.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4733991 2.29% 66.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 69118124 33.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 206453541 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.197960 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.032586 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32305475 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 86547165 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 62440790 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 17692517 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 7467594 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 591140753 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 7467594 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 42099614 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 46622929 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 29580 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 68917298 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 41316526 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 552365156 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1615 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 36415427 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4818042 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 146051 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 629691896 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1486514399 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 974943820 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 15152274 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 206357094 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.198057 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.034831 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32325248 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 86371056 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 62511253 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 17666297 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 7483240 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 591444337 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 7483240 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 42110583 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 46566289 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 29410 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 68967744 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 41199828 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 552624215 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1533 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 36277086 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4842177 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 151976 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 630066400 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1487530571 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 975657611 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 15077279 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 370262446 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2381 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2386 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 89347483 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 128815998 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 45923960 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 77358410 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 25275137 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 490566423 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 62065 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 338414549 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1099553 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 269265104 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 527048763 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 60820 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 206453541 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.639180 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.804126 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 370636950 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2363 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2376 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 89140950 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 128894590 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 45939948 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 77227738 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 25186602 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 490698604 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 59973 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 338566221 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1098463 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 269395193 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 527209931 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 58728 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 206357094 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.640681 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.805896 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 73345677 35.53% 35.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 46646037 22.59% 58.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 32854801 15.91% 74.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20905072 10.13% 84.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 15063521 7.30% 91.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8409386 4.07% 95.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5213188 2.53% 98.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2363320 1.14% 99.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1652539 0.80% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 73312584 35.53% 35.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 46573584 22.57% 58.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 32816576 15.90% 74.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20907210 10.13% 84.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 15065478 7.30% 91.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8412685 4.08% 95.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5234413 2.54% 98.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2370472 1.15% 99.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1664092 0.81% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 206453541 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 206357094 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 758238 19.31% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2733075 69.60% 88.91% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 435620 11.09% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 762770 19.47% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2718793 69.40% 88.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 436106 11.13% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1211810 0.36% 0.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 216608884 64.01% 64.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 799973 0.24% 64.60% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7048329 2.08% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1813849 0.54% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 84312637 24.91% 92.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 26619067 7.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1211777 0.36% 0.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 216613901 63.98% 64.34% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 799985 0.24% 64.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7047582 2.08% 66.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1810682 0.53% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 84424015 24.94% 92.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 26658279 7.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 338414549 # Type of FU issued -system.cpu.iq.rate 1.637635 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3926933 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011604 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 880106724 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 745207821 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 316030450 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 8202401 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 15512263 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 3567674 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 337013730 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 4115942 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18154732 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 338566221 # Type of FU issued +system.cpu.iq.rate 1.639095 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3917669 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011571 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 880328489 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 745561228 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 316131833 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 8177179 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 15427221 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 3556889 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 337169115 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 4102998 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18179072 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 72166411 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 54986 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 863760 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 25408243 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 72245003 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 55572 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 872144 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 25424231 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 50543 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 50651 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 53 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 7467594 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 35770303 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 592137 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 490628488 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1259959 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 128815998 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 45923960 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 22654 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 545800 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 38626 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 863760 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1294864 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 6880130 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8174994 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 326485130 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 80685795 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 11929419 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 7483240 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 35798970 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 583606 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 490758577 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1261619 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 128894590 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 45939948 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 21909 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 539997 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 37637 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 872144 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1294345 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 6884684 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8179029 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 326602378 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 80777118 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 11963843 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 106318426 # number of memory reference insts executed -system.cpu.iew.exec_branches 18939296 # Number of branches executed -system.cpu.iew.exec_stores 25632631 # Number of stores executed -system.cpu.iew.exec_rate 1.579907 # Inst execution rate -system.cpu.iew.wb_sent 322610085 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 319598124 # cumulative count of insts written-back -system.cpu.iew.wb_producers 256503247 # num instructions producing a value -system.cpu.iew.wb_consumers 435667509 # num instructions consuming a value -system.cpu.iew.wb_rate 1.546580 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.588759 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 269290512 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 106442155 # number of memory reference insts executed +system.cpu.iew.exec_branches 18940356 # Number of branches executed +system.cpu.iew.exec_stores 25665037 # Number of stores executed +system.cpu.iew.exec_rate 1.581174 # Inst execution rate +system.cpu.iew.wb_sent 322715986 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 319688722 # cumulative count of insts written-back +system.cpu.iew.wb_producers 256576217 # num instructions producing a value +system.cpu.iew.wb_consumers 435723594 # num instructions consuming a value +system.cpu.iew.wb_rate 1.547703 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.588851 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 269420821 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6746174 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 163890954 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.350675 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.933271 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6753005 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 163742250 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.351901 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.936120 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 67206524 41.01% 41.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 54940140 33.52% 74.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13261155 8.09% 82.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 10687834 6.52% 89.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 5446779 3.32% 92.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 3132108 1.91% 94.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1092307 0.67% 95.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1156922 0.71% 95.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6967185 4.25% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 67180478 41.03% 41.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 54846489 33.50% 74.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13227508 8.08% 82.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 10675855 6.52% 89.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5434961 3.32% 92.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3126709 1.91% 94.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1096647 0.67% 95.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1147781 0.70% 95.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7005822 4.28% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 163890954 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 163742250 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -547,478 +547,469 @@ system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction -system.cpu.commit.bw_lim_events 6967185 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 647577665 # The number of ROB reads -system.cpu.rob.rob_writes 1024269930 # The number of ROB writes -system.cpu.timesIdled 2819 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 194767 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 7005822 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 647520633 # The number of ROB reads +system.cpu.rob.rob_writes 1024585644 # The number of ROB writes +system.cpu.timesIdled 2803 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 199750 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.564674 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.564674 # CPI: Total CPI of All Threads -system.cpu.ipc 0.639111 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.639111 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 524516370 # number of integer regfile reads -system.cpu.int_regfile_writes 289029189 # number of integer regfile writes -system.cpu.fp_regfile_reads 4536413 # number of floating regfile reads -system.cpu.fp_regfile_writes 3331836 # number of floating regfile writes -system.cpu.cc_regfile_reads 107017358 # number of cc regfile reads -system.cpu.cc_regfile_writes 65774990 # number of cc regfile writes -system.cpu.misc_regfile_reads 176892429 # number of misc regfile reads +system.cpu.cpi 1.563981 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.563981 # CPI: Total CPI of All Threads +system.cpu.ipc 0.639394 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.639394 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 524858514 # number of integer regfile reads +system.cpu.int_regfile_writes 289109549 # number of integer regfile writes +system.cpu.fp_regfile_reads 4527972 # number of floating regfile reads +system.cpu.fp_regfile_writes 3322072 # number of floating regfile writes +system.cpu.cc_regfile_reads 107078976 # number of cc regfile reads +system.cpu.cc_regfile_writes 65816113 # number of cc regfile writes +system.cpu.misc_regfile_reads 177007720 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 72 # number of replacements -system.cpu.dcache.tags.tagsinuse 1525.498489 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 82766316 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2113 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 39170.050166 # Average number of references to valid blocks. +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 77 # number of replacements +system.cpu.dcache.tags.tagsinuse 1524.395872 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 82831685 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2117 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 39126.917808 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1525.498489 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.372436 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.372436 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2041 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 101 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 409 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1484 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.498291 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 165539971 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 165539971 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 62251936 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 62251936 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513707 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513707 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 82765643 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 82765643 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 82765643 # number of overall hits -system.cpu.dcache.overall_hits::total 82765643 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1262 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1262 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2024 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2024 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3286 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3286 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3286 # number of overall misses -system.cpu.dcache.overall_misses::total 3286 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 84231000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 84231000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 131983500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 131983500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 216214500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 216214500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 216214500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 216214500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 62253198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 62253198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 1524.395872 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.372167 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.372167 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2040 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 411 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1479 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 165670739 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 165670739 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 62317357 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 62317357 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513773 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513773 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 82831130 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 82831130 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 82831130 # number of overall hits +system.cpu.dcache.overall_hits::total 82831130 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1223 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1223 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1958 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1958 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3181 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3181 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3181 # number of overall misses +system.cpu.dcache.overall_misses::total 3181 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 77985000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 77985000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 124974000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 124974000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 202959000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 202959000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 202959000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 202959000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 62318580 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 62318580 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 82768929 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 82768929 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 82768929 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 82768929 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 82834311 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 82834311 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 82834311 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 82834311 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000099 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000099 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000040 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000040 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000040 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000040 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66744.057052 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66744.057052 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65209.239130 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65209.239130 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65798.691418 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65798.691418 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65798.691418 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65798.691418 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 369 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 73 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000095 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000095 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000038 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000038 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000038 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000038 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63765.331153 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63765.331153 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63827.374872 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63827.374872 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63803.520905 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63803.520905 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63803.520905 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63803.520905 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 403 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 40 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.125000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 36.500000 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 18 # number of writebacks -system.cpu.dcache.writebacks::total 18 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 661 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 661 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 7 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 7 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 668 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 668 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 668 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 668 # number of overall MSHR hits +system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.777778 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 16 # number of writebacks +system.cpu.dcache.writebacks::total 16 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 622 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 622 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 8 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 8 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 630 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 630 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 630 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 630 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 601 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 601 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2017 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2017 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2618 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2618 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2618 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2618 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47710000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 47710000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 129636500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 129636500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 177346500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 177346500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 177346500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 177346500 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1950 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1950 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2551 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2551 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2551 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2551 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47286500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 47286500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 122663000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 122663000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 169949500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 169949500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 169949500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 169949500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000098 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000098 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79384.359401 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79384.359401 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64271.938523 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64271.938523 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67741.214668 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67741.214668 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67741.214668 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67741.214668 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 6515 # number of replacements -system.cpu.icache.tags.tagsinuse 1663.291735 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 41248897 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 8499 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4853.382398 # Average number of references to valid blocks. +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000095 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000095 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000031 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000031 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78679.700499 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78679.700499 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62904.102564 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62904.102564 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66620.736966 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66620.736966 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66620.736966 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66620.736966 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 6489 # number of replacements +system.cpu.icache.tags.tagsinuse 1681.757073 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 41270224 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8478 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 4867.919792 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1663.291735 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.812154 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.812154 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1984 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 845 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 155 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 736 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.968750 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 82532972 # Number of tag accesses -system.cpu.icache.tags.data_accesses 82532972 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 41248897 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 41248897 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 41248897 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 41248897 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 41248897 # number of overall hits -system.cpu.icache.overall_hits::total 41248897 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13089 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 13089 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 13089 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13089 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13089 # number of overall misses -system.cpu.icache.overall_misses::total 13089 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 485791000 # 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average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 37114.447246 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2090 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 305 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 30 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 69.666667 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 305 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 6515 # number of writebacks -system.cpu.icache.writebacks::total 6515 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4088 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4088 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4088 # 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average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37852.238640 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37852.238640 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37852.238640 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37852.238640 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37852.238640 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.occ_blocks::cpu.inst 1681.757073 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.821170 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.821170 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1989 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 832 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 147 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 747 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.971191 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 82575282 # Number of tag accesses +system.cpu.icache.tags.data_accesses 82575282 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 41270227 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 41270227 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 41270227 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 41270227 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 41270227 # number of overall hits +system.cpu.icache.overall_hits::total 41270227 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12961 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12961 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12961 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12961 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12961 # number of overall misses +system.cpu.icache.overall_misses::total 12961 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 483569000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 483569000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 483569000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 483569000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 483569000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 483569000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 41283188 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 41283188 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 41283188 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 41283188 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 41283188 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 41283188 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000314 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000314 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000314 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000314 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000314 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000314 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37309.544017 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 37309.544017 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 37309.544017 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 37309.544017 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 37309.544017 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 37309.544017 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1349 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # 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number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8907 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 8907 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 8907 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 8907 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 8907 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 8907 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 345609000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 345609000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 345609000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 345609000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 345609000 # 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average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 38801.953520 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38801.953520 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 38801.953520 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2796.844278 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 11471 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4155 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.760770 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 3906.658043 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 11874 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5667 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.095289 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 4.971138 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2402.103394 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 389.769746 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073306 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.011895 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.085353 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 4155 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 992 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 147 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2824 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.126801 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 146881 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 146881 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 18 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 18 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 6469 # 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mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.428133 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.881469 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.881469 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.428133 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963173 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.535121 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.428133 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963173 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.535121 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65943.783069 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65943.783069 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67314.911797 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67314.911797 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76051.136364 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76051.136364 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67314.911797 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68559.803922 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67762.967537 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67314.911797 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68559.803922 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67762.967537 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 18024 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 7043 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 478 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 9600 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 18 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 6515 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 54 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 505 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 505 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1513 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1513 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 9001 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 600 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24009 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5308 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 29317 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 960512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 136384 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1096896 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 507 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 32448 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11619 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.094328 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.292297 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 9504 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 6489 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 61 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 433 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 433 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 8907 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 599 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23869 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5178 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 29047 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 957568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 136512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1094080 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 433 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 27712 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 11458 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.082912 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.275760 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 10523 90.57% 90.57% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1096 9.43% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 10508 91.71% 91.71% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 950 8.29% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11619 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 15636499 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11458 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 15517998 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 13500000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 13359000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3422499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3392501 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 4149 # Transaction distribution -system.membus.trans_dist::UpgradeReq 500 # Transaction distribution -system.membus.trans_dist::ReadExReq 1507 # Transaction distribution -system.membus.trans_dist::ReadExResp 1507 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 4149 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11812 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11812 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11812 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 361984 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 361984 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 361984 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 5668 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 4155 # Transaction distribution +system.membus.trans_dist::ReadExReq 1512 # Transaction distribution +system.membus.trans_dist::ReadExResp 1512 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 4156 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11335 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11335 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11335 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 362688 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 362688 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 362688 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 6156 # Request fanout histogram +system.membus.snoop_fanout::samples 5668 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 6156 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5668 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 6156 # Request fanout histogram -system.membus.reqLayer0.occupancy 7649501 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5668 # Request fanout histogram +system.membus.reqLayer0.occupancy 7074000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 30011250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 30060000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |