summaryrefslogtreecommitdiff
path: root/tests/long/se/70.twolf/ref
diff options
context:
space:
mode:
authorSteve Reinhardt <steve.reinhardt@amd.com>2014-07-19 19:04:58 -0700
committerSteve Reinhardt <steve.reinhardt@amd.com>2014-07-19 19:04:58 -0700
commit040fa23d01109c68d194d2517df777844e4e2f13 (patch)
tree822b7da72458db435480c20c1a3448f6158c62aa /tests/long/se/70.twolf/ref
parent06bb6a473157a204bb7e77ea28e618aa08d2d811 (diff)
downloadgem5-040fa23d01109c68d194d2517df777844e4e2f13.tar.xz
stats: update for syscall DPRINTF change
Only printing one rather than two args for the ignored syscall warning means the count of register accesses has changed on a few runs. Oddly only Alpha Tru64 seems to have any ignored syscalls in the regression tests.
Diffstat (limited to 'tests/long/se/70.twolf/ref')
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini14
-rwxr-xr-xtests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr2
-rwxr-xr-xtests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout6
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt12
4 files changed, 22 insertions, 12 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
index 104ffdb52..91fb4fb7f 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
[system]
type=System
-children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
+children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
@@ -37,7 +37,9 @@ system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
+domain_id=-1
eventq_index=0
+init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
@@ -615,9 +617,19 @@ uid=100
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
+domain_id=-1
eventq_index=0
+init_perf_level=0
voltage_domain=system.voltage_domain
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
[system.membus]
type=CoherentBus
clk_domain=system.clk_domain
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr
index 506aa6e28..de77515a1 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr
@@ -2,4 +2,4 @@ warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
-warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+warn: ignoring syscall sigprocmask(1, ...)
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
index 2cc52ce3f..f7d4d117a 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
@@ -1,10 +1,8 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 10:36:29
-gem5 started Jun 21 2014 12:55:52
+gem5 compiled Jul 19 2014 12:27:06
+gem5 started Jul 19 2014 12:27:28
gem5 executing on phenom
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
index 22a3b525f..35ce90696 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.023058 # Nu
sim_ticks 23058360500 # Number of ticks simulated
final_tick 23058360500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 185322 # Simulator instruction rate (inst/s)
-host_op_rate 185322 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 50763012 # Simulator tick rate (ticks/s)
-host_mem_usage 226392 # Number of bytes of host memory used
-host_seconds 454.24 # Real time elapsed on the host
+host_inst_rate 185744 # Simulator instruction rate (inst/s)
+host_op_rate 185744 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 50878767 # Simulator tick rate (ticks/s)
+host_mem_usage 227216 # Number of bytes of host memory used
+host_seconds 453.20 # Real time elapsed on the host
sim_insts 84179709 # Number of instructions simulated
sim_ops 84179709 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -575,7 +575,7 @@ system.cpu.cpi 0.547837 # CP
system.cpu.cpi_total 0.547837 # CPI: Total CPI of All Threads
system.cpu.ipc 1.825362 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.825362 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 130779467 # number of integer regfile reads
+system.cpu.int_regfile_reads 130779466 # number of integer regfile reads
system.cpu.int_regfile_writes 71543363 # number of integer regfile writes
system.cpu.fp_regfile_reads 6233836 # number of floating regfile reads
system.cpu.fp_regfile_writes 6101151 # number of floating regfile writes