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authorAndreas Hansson <andreas.hansson@arm.com>2014-09-03 07:42:56 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2014-09-03 07:42:56 -0400
commit351e146b37c61481152ef3ad551b2dd30aa6127a (patch)
treec3efe5e53ccfe3c0d30718b599b5f6c3972f5e3a /tests/long/se/70.twolf/ref
parent83a46bfc09cbfd8b7e117fc7bdb14ad907438f6f (diff)
downloadgem5-351e146b37c61481152ef3ad551b2dd30aa6127a.tar.xz
alpha: Stop using 'inorder' and rely entirely on 'minor'
This patch avoids building the 'inorder' CPU model for any permutation of ALPHA, and also removes the ALPHA regressions using the 'inorder' CPU. The 'minor' CPU is already providing a broader test coverage.
Diffstat (limited to 'tests/long/se/70.twolf/ref')
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini346
-rwxr-xr-xtests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simerr5
-rwxr-xr-xtests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout26
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.out276
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pin17
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl111
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl22
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.sav18
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.sv219
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.twf29
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt724
11 files changed, 0 insertions, 1473 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
deleted file mode 100644
index 1547a2d4b..000000000
--- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
+++ /dev/null
@@ -1,346 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-num_work_ids=16
-readfile=
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=InOrderCPU
-children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-activity=0
-branchPred=system.cpu.branchPred
-cachePorts=2
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-div16Latency=1
-div16RepeatRate=1
-div24Latency=1
-div24RepeatRate=1
-div32Latency=1
-div32RepeatRate=1
-div8Latency=1
-div8RepeatRate=1
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-fetchBuffSize=4
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-memBlockSize=64
-multLatency=1
-multRepeatRate=1
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-stageTracing=false
-stageWidth=4
-switched_out=false
-system=system
-threadModel=SMT
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.branchPred]
-type=BranchPredictor
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
-numThreads=1
-predType=tournament
-
-[system.cpu.dcache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=262144
-system=system
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=262144
-
-[system.cpu.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu.icache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=131072
-system=system
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=131072
-
-[system.cpu.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu.l2cache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=8
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-forward_snoops=true
-hit_latency=20
-is_top_level=false
-max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=2097152
-system=system
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=20
-sequential_access=false
-size=2097152
-
-[system.cpu.toL2Bus]
-type=CoherentBus
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-header_cycles=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=twolf smred
-cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing
-egid=100
-env=
-errout=cerr
-euid=100
-eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
-gid=100
-input=cin
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentBus
-clk_domain=system.clk_domain
-eventq_index=0
-header_cycles=1
-system=system
-use_default_range=false
-width=8
-master=system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=DRAMCtrl
-activation_limit=4
-addr_mapping=RoRaBaChCo
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-device_bus_width=8
-device_rowbuffer_size=1024
-devices_per_rank=8
-eventq_index=0
-in_addr_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-page_policy=open_adaptive
-range=0:134217727
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCK=1250
-tCL=13750
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simerr
deleted file mode 100755
index de77515a1..000000000
--- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simerr
+++ /dev/null
@@ -1,5 +0,0 @@
-warn: Sockets disabled, not accepting gdb connections
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-warn: ignoring syscall sigprocmask(1, ...)
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout
deleted file mode 100755
index 2875d7c3b..000000000
--- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout
+++ /dev/null
@@ -1,26 +0,0 @@
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jan 22 2014 16:27:55
-gem5 started Jan 22 2014 19:03:25
-gem5 executing on u200540-lin
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing
-Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sav
-Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sv2
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
- 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
- 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
- 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
- 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
- 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
- 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
-106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 41681685000 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.out b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.out
deleted file mode 100644
index 98777e0af..000000000
--- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.out
+++ /dev/null
@@ -1,276 +0,0 @@
-
-TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
-Standard Cell Placement and Global Routing Program
-Authors: Carl Sechen, Bill Swartz
- Yale University
-
-
-NOTE: Restart file .rs2 not used
-
-TimberWolf will perform a global route step
-rowSep: 1.000000
-feedThruWidth: 4
-
-******************
-BLOCK DATA
-block:1 desire:85
-block:2 desire:85
-Total Desired Length: 170
-total cell length: 168
-total block length: 168
-block x-span:84 block y-span:78
-implicit feed thru range: -84
-Using default value of bin.penalty.control:1.000000
-numBins automatically set to:5
-binWidth = average_cell_width + 0 sigma= 17
-average_cell_width is:16
-standard deviation of cell length is:23.6305
-TimberWolfSC starting from the beginning
-
-
-
-THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
-The number of nets with 1 pin is 4
-The number of nets with 2 pin is 9
-The number of nets with 3 pin is 0
-The number of nets with 4 pin is 2
-The number of nets with 5 pin is 0
-The number of nets with 6 pin is 0
-The number of nets with 7 pin is 0
-The number of nets with 8 pin is 0
-The number of nets with 9 pin is 0
-The number of nets with 10 pin or more is 0
-
-New Cost Function: Initial Horizontal Cost:242
-New Cost Function: FEEDS:0 MISSING_ROWS:-46
-
-bdxlen:86 bdylen:78
-l:0 t:78 r:86 b:0
-
-
-
-THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
-
-
-
-THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
-
-The rand generator seed was at utemp() : 1
-
-
- tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
- tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
- tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
- tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
-
- I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
- 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
- 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
- 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.3 0.0 0 46
- 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
- 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
- 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
- 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
- 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
- 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
- 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
- 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
- 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
- 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
- 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
- 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
- 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
- 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
- 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
- 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
- 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
- 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
- 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
- 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
- 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
- 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
- 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
- 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
- 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
- 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
- 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
- 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
- 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
- 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
- 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
- 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
- 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
- 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
- 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
- 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
- 40 251 8 741 104 159 0.0 0.8 0.5 36.3 47.5 0.0 0 48
- 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
- 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
- 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
- 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
- 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
- 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
- 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
- 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
- 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
- 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
- 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
- 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
- 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
- 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
- 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
- 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
- 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
- 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
- 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
- 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
- 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
- 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
- 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
- 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
- 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
- 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
- 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
- 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
- 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
- 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
- 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
- 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
- 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
- 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
- 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
- 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
- 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
- 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
- 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
- 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
- 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
- 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
- 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
- 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
- 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
- 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
- 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
- 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
- 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
- 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
- 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
- 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
- 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
- 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
- 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
- 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
- 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
- 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
- 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
-100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
-101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
-102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
-103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
-104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
-105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
-106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
-107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
-108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
-109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
-110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
-111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
-112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
-113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
-114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
-115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
-116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
-117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
-118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
-119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
-120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
-121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
-
-Initial Wiring Cost: 645 Final Wiring Cost: 732
-############## Percent Wire Cost Reduction: -13
-
-
-Initial Wire Length: 645 Final Wire Length: 732
-************** Percent Wire Length Reduction: -13
-
-
-Initial Horiz. Wire: 216 Final Horiz. Wire: 147
-$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
-
-
-Initial Vert. Wire: 429 Final Vert. Wire: 585
-@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
-
-Before Feeds are Added:
-BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
- 1 82 -20
- 2 86 -16
-
-LONGEST Block is:2 Its length is:86
-BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
- 1 86 -16
- 2 86 -16
-
-LONGEST Block is:1 Its length is:86
-Added: 1 feed-through cells
-
-Removed the cell overlaps --- Will do neighbor interchanges only now
-
-TOTAL INTERCONNECT LENGTH: 994
-OVERLAP PENALTY: 0
-
-initialRowControl: 1.650
-finalRowControl: 0.300
-iter T Wire accept
- 122 0.001 976 16%
- 123 0.001 971 0%
- 124 0.001 971 0%
-Total Feed-Alignment Movement (Pass 1): 0
-Total Feed-Alignment Movement (Pass 2): 0
-Total Feed-Alignment Movement (Pass 3): 0
-Total Feed-Alignment Movement (Pass 4): 0
-Total Feed-Alignment Movement (Pass 5): 0
-Total Feed-Alignment Movement (Pass 6): 0
-Total Feed-Alignment Movement (Pass 7): 0
-Total Feed-Alignment Movement (Pass 8): 0
-
-The rand generator seed was at globroute() : 987654321
-
-
-Total Number of Net Segments: 9
-Number of Switchable Net Segments: 0
-
-Number of channels: 3
-
-
-
-THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
-
-
-no. of accepted flips: 0
-no. of attempted flips: 0
-THIS IS THE NUMBER OF TRACKS: 5
-
-
-
-FINAL NUMBER OF ROUTING TRACKS: 5
-
-MAX OF CHANNEL: 1 is: 0
-MAX OF CHANNEL: 2 is: 4
-MAX OF CHANNEL: 3 is: 1
-FINAL TOTAL INTERCONNECT LENGTH: 978
-FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
-MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
-
-
-cost_scale_factor:3.90616
-
-Number of Feed Thrus: 0
-Number of Implicit Feed Thrus: 0
-
-Statistics:
-Number of Standard Cells: 10
-Number of Pads: 0
-Number of Nets: 15
-Number of Pins: 46
-Usage statistics not available
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pin b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pin
deleted file mode 100644
index 62b922e4e..000000000
--- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pin
+++ /dev/null
@@ -1,17 +0,0 @@
-$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
-$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
-B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
-B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
-B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
-B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
-B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
-B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
-B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
-$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
-$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
-$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
-$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
-$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
-$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
-$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
-$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl1 b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl1
deleted file mode 100644
index bdc569e39..000000000
--- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl1
+++ /dev/null
@@ -1,11 +0,0 @@
-$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
-$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
-$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
-ACOUNT_1 14 0 18 26 2 1
-twfeed1 18 0 22 26 0 1
-$COUNT_1/$FJK3_1 22 0 86 26 0 1
-$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
-$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
-$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
-$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
-$COUNT_1/$FJK3_2 22 52 86 78 0 2
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl2 b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl2
deleted file mode 100644
index 6e2601e82..000000000
--- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl2
+++ /dev/null
@@ -1,2 +0,0 @@
-1 0 0 86 26 0 0
-2 0 52 86 78 0 0
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.sav b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.sav
deleted file mode 100644
index 04c8e9935..000000000
--- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.sav
+++ /dev/null
@@ -1,18 +0,0 @@
-0.009592
-121
-0
-1
-0.000000
-0.500000
-3.906156
-1
-1 1 2 37 13
-2 2 0 34 65
-3 2 2 63 65
-4 1 0 59 13
-5 1 2 32 13
-6 2 0 23 65
-7 1 2 12 13
-8 2 0 6 65
-9 1 0 70 13
-10 2 0 70 65
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.sv2 b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.sv2
deleted file mode 100644
index 9dd68ecdb..000000000
--- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.sv2
+++ /dev/null
@@ -1,19 +0,0 @@
-0.001000
-123
-0
-2
-0.000000
-0.500000
-3.906156
-1
-1 1 2 16 13
-2 2 2 19 65
-3 2 2 14 65
-4 1 0 11 13
-5 1 2 6 13
-6 2 0 3 65
-7 1 0 2 13
-8 2 2 9 65
-9 1 0 50 13
-10 2 0 54 65
-11 1 0 84 13
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.twf b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.twf
deleted file mode 100644
index a4c2eac35..000000000
--- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.twf
+++ /dev/null
@@ -1,29 +0,0 @@
-net 1
-segment channel 2
- pin1 1 pin2 7 0 0
-net 2
-segment channel 3
-pin1 41 pin2 42 0 0
-segment channel 2
-pin1 12 pin2 3 0 0
-net 3
-segment channel 2
-pin1 35 pin2 36 0 0
-segment channel 2
-pin1 19 pin2 35 0 0
-net 4
-segment channel 2
- pin1 5 pin2 38 0 0
-net 5
-net 7
-segment channel 2
- pin1 14 pin2 43 0 0
-net 8
-segment channel 2
- pin1 23 pin2 17 0 0
-net 9
-net 11
-segment channel 2
- pin1 25 pin2 31 0 0
-net 14
-net 15
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
deleted file mode 100644
index bb082f445..000000000
--- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
+++ /dev/null
@@ -1,724 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.041682 # Number of seconds simulated
-sim_ticks 41681685000 # Number of ticks simulated
-final_tick 41681685000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 117228 # Simulator instruction rate (inst/s)
-host_op_rate 117228 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 53167547 # Simulator tick rate (ticks/s)
-host_mem_usage 270132 # Number of bytes of host memory used
-host_seconds 783.97 # Real time elapsed on the host
-sim_insts 91903056 # Number of instructions simulated
-sim_ops 91903056 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 137216 # Number of bytes read from this memory
-system.physmem.bytes_read::total 316032 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 178816 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 178816 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 4290038 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3291997 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 7582035 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 4290038 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 4290038 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 4290038 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3291997 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 7582035 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 4938 # Number of read requests accepted
-system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 4938 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 316032 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
-system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 316032 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 443 # Per bank write bursts
-system.physmem.perBankRdBursts::1 270 # Per bank write bursts
-system.physmem.perBankRdBursts::2 295 # Per bank write bursts
-system.physmem.perBankRdBursts::3 499 # Per bank write bursts
-system.physmem.perBankRdBursts::4 209 # Per bank write bursts
-system.physmem.perBankRdBursts::5 212 # Per bank write bursts
-system.physmem.perBankRdBursts::6 207 # Per bank write bursts
-system.physmem.perBankRdBursts::7 265 # Per bank write bursts
-system.physmem.perBankRdBursts::8 219 # Per bank write bursts
-system.physmem.perBankRdBursts::9 249 # Per bank write bursts
-system.physmem.perBankRdBursts::10 238 # Per bank write bursts
-system.physmem.perBankRdBursts::11 236 # Per bank write bursts
-system.physmem.perBankRdBursts::12 379 # Per bank write bursts
-system.physmem.perBankRdBursts::13 325 # Per bank write bursts
-system.physmem.perBankRdBursts::14 469 # Per bank write bursts
-system.physmem.perBankRdBursts::15 423 # Per bank write bursts
-system.physmem.perBankWrBursts::0 0 # Per bank write bursts
-system.physmem.perBankWrBursts::1 0 # Per bank write bursts
-system.physmem.perBankWrBursts::2 0 # Per bank write bursts
-system.physmem.perBankWrBursts::3 0 # Per bank write bursts
-system.physmem.perBankWrBursts::4 0 # Per bank write bursts
-system.physmem.perBankWrBursts::5 0 # Per bank write bursts
-system.physmem.perBankWrBursts::6 0 # Per bank write bursts
-system.physmem.perBankWrBursts::7 0 # Per bank write bursts
-system.physmem.perBankWrBursts::8 0 # Per bank write bursts
-system.physmem.perBankWrBursts::9 0 # Per bank write bursts
-system.physmem.perBankWrBursts::10 0 # Per bank write bursts
-system.physmem.perBankWrBursts::11 0 # Per bank write bursts
-system.physmem.perBankWrBursts::12 0 # Per bank write bursts
-system.physmem.perBankWrBursts::13 0 # Per bank write bursts
-system.physmem.perBankWrBursts::14 0 # Per bank write bursts
-system.physmem.perBankWrBursts::15 0 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 41681611000 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 0 # Read request sizes (log2)
-system.physmem.readPktSize::4 0 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 4938 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 0 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 3265 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 1049 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 546 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 74 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 856 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 367.551402 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 223.659981 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 343.121338 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 258 30.14% 30.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 183 21.38% 51.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 95 11.10% 62.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 63 7.36% 69.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 46 5.37% 75.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 30 3.50% 78.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 51 5.96% 84.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 22 2.57% 87.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 108 12.62% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 856 # Bytes accessed per row activation
-system.physmem.totQLat 35422000 # Total ticks spent queuing
-system.physmem.totMemAccLat 128009500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 24690000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 7173.35 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 25923.35 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 7.58 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 7.58 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.06 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.06 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 4077 # Number of row buffer hits during reads
-system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 82.56 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 8440990.48 # Average gap between requests
-system.physmem.pageHitRate 82.56 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 39211333500 # Time in different power states
-system.physmem.memoryStateTime::REF 1391780000 # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 1076956500 # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 7582035 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 3216 # Transaction distribution
-system.membus.trans_dist::ReadResp 3216 # Transaction distribution
-system.membus.trans_dist::ReadExReq 1722 # Transaction distribution
-system.membus.trans_dist::ReadExResp 1722 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9876 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 9876 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 316032 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 316032 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 316032 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 5782000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 45945000 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 13412628 # Number of BP lookups
-system.cpu.branchPred.condPredicted 9650146 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 4269214 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 7424480 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 3768498 # Number of BTB hits
-system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 50.757737 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1029619 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 126 # Number of incorrect RAS predictions.
-system.cpu.dtb.fetch_hits 0 # ITB hits
-system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.fetch_acv 0 # ITB acv
-system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 19996260 # DTB read hits
-system.cpu.dtb.read_misses 10 # DTB read misses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 19996270 # DTB read accesses
-system.cpu.dtb.write_hits 6501862 # DTB write hits
-system.cpu.dtb.write_misses 23 # DTB write misses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 6501885 # DTB write accesses
-system.cpu.dtb.data_hits 26498122 # DTB hits
-system.cpu.dtb.data_misses 33 # DTB misses
-system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 26498155 # DTB accesses
-system.cpu.itb.fetch_hits 9956951 # ITB hits
-system.cpu.itb.fetch_misses 49 # ITB misses
-system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 9957000 # ITB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_acv 0 # DTB read access violations
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_acv 0 # DTB write access violations
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.data_hits 0 # DTB hits
-system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.data_acv 0 # DTB access violations
-system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.workload.num_syscalls 389 # Number of system calls
-system.cpu.numCycles 83363371 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.predictedTaken 5905663 # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken 7506965 # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads 73570553 # Number of Reads from Int. Register File
-system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses 136146025 # Total Accesses (Read+Write) to the Int. Register File
-system.cpu.regfile_manager.floatRegFileReads 2206128 # Number of Reads from FP Register File
-system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File
-system.cpu.regfile_manager.floatRegFileAccesses 8058016 # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards 38521865 # Number of Registers Read Through Forwarding Logic
-system.cpu.agen_unit.agens 26722393 # Number of Address Generations
-system.cpu.execution_unit.predictedTakenIncorrect 3469296 # Number of Branches Incorrectly Predicted As Taken.
-system.cpu.execution_unit.predictedNotTakenIncorrect 799060 # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.execution_unit.mispredicted 4268356 # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.predicted 5972346 # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.mispredictPct 41.680307 # Percentage of Incorrect Branches Predicts
-system.cpu.execution_unit.executions 57404027 # Number of Instructions Executed.
-system.cpu.mult_div_unit.multiplies 458253 # Number of Multipy Operations Executed
-system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
-system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 82970271 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
-system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled 10393 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 7755613 # Number of cycles cpu's stages were not processed
-system.cpu.runCycles 75607758 # Number of cycles cpu stages are processed.
-system.cpu.activity 90.696618 # Percentage of cycles cpu is active
-system.cpu.comLoads 19996198 # Number of Load instructions committed
-system.cpu.comStores 6501103 # Number of Store instructions committed
-system.cpu.comBranches 10240685 # Number of Branches instructions committed
-system.cpu.comNops 7723346 # Number of Nop instructions committed
-system.cpu.comNonSpec 389 # Number of Non-Speculative instructions committed
-system.cpu.comInts 43665352 # Number of Integer instructions committed
-system.cpu.comFloats 3775974 # Number of Floating Point instructions committed
-system.cpu.committedInsts 91903056 # Number of Instructions committed (Per-Thread)
-system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread)
-system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
-system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total)
-system.cpu.cpi 0.907079 # CPI: Cycles Per Instruction (Per-Thread)
-system.cpu.smt_cpi nan # CPI: Total SMT-CPI
-system.cpu.cpi_total 0.907079 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.102439 # IPC: Instructions Per Cycle (Per-Thread)
-system.cpu.smt_ipc nan # IPC: Total SMT-IPC
-system.cpu.ipc_total 1.102439 # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles 27683021 # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles 55680350 # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization 66.792345 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles 34111687 # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles 49251684 # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization 59.080725 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles 33512024 # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles 49851347 # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization 59.800061 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles 65336871 # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles 18026500 # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization 21.624006 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles 29503616 # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles 53859755 # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization 64.608418 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.icache.tags.replacements 7635 # number of replacements
-system.cpu.icache.tags.tagsinuse 1492.194030 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 9945551 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 9520 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 1044.700735 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1492.194030 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.728610 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.728610 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 1885 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 613 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 136 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 959 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.920410 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 19923422 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 19923422 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 9945551 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 9945551 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 9945551 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 9945551 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 9945551 # number of overall hits
-system.cpu.icache.overall_hits::total 9945551 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 11400 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 11400 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 11400 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 11400 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 11400 # number of overall misses
-system.cpu.icache.overall_misses::total 11400 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 327908250 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 327908250 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 327908250 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 327908250 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 327908250 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 327908250 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 9956951 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 9956951 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 9956951 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 9956951 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 9956951 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 9956951 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001145 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.001145 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.001145 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.001145 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.001145 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.001145 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28763.881579 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 28763.881579 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 28763.881579 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 28763.881579 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 28763.881579 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 28763.881579 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1880 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 1880 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 1880 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 1880 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 1880 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 1880 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9520 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 9520 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 9520 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 9520 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 9520 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 9520 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 268503000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 268503000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 268503000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 268503000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 268503000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 268503000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000956 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.000956 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.000956 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28204.096639 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28204.096639 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28204.096639 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 28204.096639 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28204.096639 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 28204.096639 # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 18195042 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 9995 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 9995 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 1748 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19040 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4553 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 23593 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 609280 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149120 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 758400 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 758400 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 700 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 168 # Occupied blocks per task id
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-system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits
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-system.cpu.l2cache.ReadReq_accesses::total 9995 # number of ReadReq accesses(hits+misses)
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-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67928.947368 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67928.947368 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70755.005721 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70755.005721 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70151.147099 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 70151.147099 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70151.147099 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 70151.147099 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-
----------- End Simulation Statistics ----------