diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
| commit | 8909843a76c723cb9d8a0b1394eeeba4d7abadb1 (patch) | |
| tree | 446fe188000e814cbc7d23075428cab7f44868d1 /tests/long/se/70.twolf/ref | |
| parent | fc315901ff4aaae0f56c4c1b1c50ffe9bd70b4d6 (diff) | |
| download | gem5-8909843a76c723cb9d8a0b1394eeeba4d7abadb1.tar.xz | |
stats: Update stats to reflect cache and interconnect changes
This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
Diffstat (limited to 'tests/long/se/70.twolf/ref')
10 files changed, 3389 insertions, 3395 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index ae03186ae..e483ad3f0 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.052167 # Number of seconds simulated -sim_ticks 52167245000 # Number of ticks simulated -final_tick 52167245000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.052202 # Number of seconds simulated +sim_ticks 52201532500 # Number of ticks simulated +final_tick 52201532500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 211928 # Simulator instruction rate (inst/s) -host_op_rate 211928 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 120297341 # Simulator tick rate (ticks/s) -host_mem_usage 286252 # Number of bytes of host memory used -host_seconds 433.65 # Real time elapsed on the host +host_inst_rate 357575 # Simulator instruction rate (inst/s) +host_op_rate 357575 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 203104604 # Simulator tick rate (ticks/s) +host_mem_usage 300132 # Number of bytes of host memory used +host_seconds 257.02 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 202688 # Nu system.physmem.num_reads::cpu.inst 3167 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2151 # Number of read requests responded to by this memory system.physmem.num_reads::total 5318 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3885350 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2638897 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6524247 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3885350 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3885350 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3885350 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2638897 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6524247 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 3882798 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2637164 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6519962 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3882798 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3882798 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3882798 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2637164 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6519962 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 5318 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 5318 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 52167163500 # Total gap between requests +system.physmem.totGap 52201444000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 386 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4919 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 380 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 972 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 348.971193 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 211.834828 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 332.374999 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 320 32.92% 32.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 191 19.65% 52.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 96 9.88% 62.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 99 10.19% 72.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 63 6.48% 79.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 36 3.70% 82.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 24 2.47% 85.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 26 2.67% 87.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 117 12.04% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 972 # Bytes accessed per row activation -system.physmem.totQLat 32099750 # Total ticks spent queuing -system.physmem.totMemAccLat 131812250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 983 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 345.912513 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 209.979760 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.521018 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 325 33.06% 33.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 203 20.65% 53.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 90 9.16% 62.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 89 9.05% 71.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 77 7.83% 79.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 32 3.26% 83.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 28 2.85% 85.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 23 2.34% 88.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 116 11.80% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 983 # Bytes accessed per row activation +system.physmem.totQLat 33415750 # Total ticks spent queuing +system.physmem.totMemAccLat 133128250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26590000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6036.06 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6283.52 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24786.06 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25033.52 # Average memory access latency per DRAM burst system.physmem.avgRdBW 6.52 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 6.52 # Average system read bandwidth in MiByte/s @@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.05 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4338 # Number of row buffer hits during reads +system.physmem.readRowHits 4331 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.57 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.44 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9809545.60 # Average gap between requests -system.physmem.pageHitRate 81.57 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3530520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1926375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 19827600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 9815991.73 # Average gap between requests +system.physmem.pageHitRate 81.44 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3500280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1909875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 19975800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3406843440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1740830445 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29769165000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34942123380 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.898193 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49520504500 # Time in different power states -system.physmem_0.memoryStateTime::REF 1741740000 # Time in different power states +system.physmem_0.refreshEnergy 3409386240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1770933285 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29766117750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34971823230 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.967540 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49515286750 # Time in different power states +system.physmem_0.memoryStateTime::REF 1743040000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 898118000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 940967000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3772440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2058375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 21216000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3908520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2132625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 21301800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3406843440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1807143390 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29710995750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34952029395 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.088108 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49425818250 # Time in different power states -system.physmem_1.memoryStateTime::REF 1741740000 # Time in different power states +system.physmem_1.refreshEnergy 3409386240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1804216725 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29736921750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34977867660 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.083336 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49466733750 # Time in different power states +system.physmem_1.memoryStateTime::REF 1743040000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 995309750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 989849750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 11476348 # Number of BP lookups -system.cpu.branchPred.condPredicted 8235349 # Number of conditional branches predicted +system.cpu.branchPred.lookups 11476351 # Number of BP lookups +system.cpu.branchPred.condPredicted 8235351 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 785844 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 6672654 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5371509 # Number of BTB hits +system.cpu.branchPred.BTBLookups 6672655 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5371510 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.500338 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1176737 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 80.500341 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1176738 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits @@ -276,10 +276,10 @@ system.cpu.dtb.data_hits 26977004 # DT system.cpu.dtb.data_misses 47407 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 27024411 # DTB accesses -system.cpu.itb.fetch_hits 23068130 # ITB hits +system.cpu.itb.fetch_hits 23068140 # ITB hits system.cpu.itb.fetch_misses 88 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 23068218 # ITB accesses +system.cpu.itb.fetch_accesses 23068228 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,26 +293,26 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 104334490 # number of cpu cycles simulated +system.cpu.numCycles 104403065 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 91903089 # Number of instructions committed system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed system.cpu.discardedOps 2153944 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.135266 # CPI: cycles per instruction -system.cpu.ipc 0.880851 # IPC: instructions per cycle -system.cpu.tickCycles 102681434 # Number of cycles that the object actually ticked -system.cpu.idleCycles 1653056 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.136013 # CPI: cycles per instruction +system.cpu.ipc 0.880272 # IPC: instructions per cycle +system.cpu.tickCycles 102681380 # Number of cycles that the object actually ticked +system.cpu.idleCycles 1721685 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1448.700214 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26568138 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1448.443915 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26568135 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11913.963229 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11913.961883 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1448.700214 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.353687 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.353687 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1448.443915 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.353624 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.353624 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id @@ -320,16 +320,16 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 226 system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1380 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 53145366 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 53145366 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20069946 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20069946 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 53145360 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 53145360 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20069943 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20069943 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 6498192 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 6498192 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26568138 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26568138 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26568138 # number of overall hits -system.cpu.dcache.overall_hits::total 26568138 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 26568135 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26568135 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26568135 # number of overall hits +system.cpu.dcache.overall_hits::total 26568135 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 519 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 519 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 2911 # number of WriteReq misses @@ -338,22 +338,22 @@ system.cpu.dcache.demand_misses::cpu.data 3430 # n system.cpu.dcache.demand_misses::total 3430 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 3430 # number of overall misses system.cpu.dcache.overall_misses::total 3430 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 37684500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 37684500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 195045500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 195045500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 232730000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 232730000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 232730000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 232730000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20070465 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20070465 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 40365000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 40365000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 216719250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 216719250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 257084250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 257084250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 257084250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 257084250 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20070462 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20070462 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 26571568 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 26571568 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 26571568 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 26571568 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 26571565 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26571565 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 26571565 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26571565 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000448 # miss rate for WriteReq accesses @@ -362,14 +362,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000129 system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000129 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72609.826590 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72609.826590 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67002.919959 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 67002.919959 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67851.311953 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67851.311953 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67851.311953 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67851.311953 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77774.566474 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 77774.566474 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74448.385435 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 74448.385435 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 74951.676385 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 74951.676385 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 74951.676385 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 74951.676385 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -396,14 +396,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2230 system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2230 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34103500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 34103500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 117640500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 117640500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 151744000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 151744000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 151744000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 151744000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37010250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 37010250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 130741250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 130741250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 167751500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 167751500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 167751500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 167751500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses @@ -412,24 +412,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70316.494845 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70316.494845 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67415.759312 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67415.759312 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68046.636771 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68046.636771 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68046.636771 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68046.636771 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76309.793814 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76309.793814 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74923.352436 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74923.352436 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75224.887892 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75224.887892 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75224.887892 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75224.887892 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13871 # number of replacements -system.cpu.icache.tags.tagsinuse 1640.665289 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 23052294 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1640.396029 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 23052304 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15835 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1455.781118 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1455.781749 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1640.665289 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.801106 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.801106 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1640.396029 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.800975 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.800975 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1964 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id @@ -437,44 +437,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 669 system.cpu.icache.tags.age_task_id_blocks_1024::3 148 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 948 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.958984 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 46152095 # Number of tag accesses -system.cpu.icache.tags.data_accesses 46152095 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 23052294 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 23052294 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 23052294 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 23052294 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 23052294 # number of overall hits -system.cpu.icache.overall_hits::total 23052294 # number of overall hits +system.cpu.icache.tags.tag_accesses 46152115 # Number of tag accesses +system.cpu.icache.tags.data_accesses 46152115 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 23052304 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 23052304 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 23052304 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 23052304 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 23052304 # number of overall hits +system.cpu.icache.overall_hits::total 23052304 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 15836 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 15836 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 15836 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 15836 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15836 # number of overall misses system.cpu.icache.overall_misses::total 15836 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 386327750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 386327750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 386327750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 386327750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 386327750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 386327750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 23068130 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 23068130 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 23068130 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 23068130 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 23068130 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 23068130 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 409644000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 409644000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 409644000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 409644000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 409644000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 409644000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 23068140 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 23068140 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 23068140 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 23068140 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 23068140 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 23068140 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000686 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000686 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000686 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000686 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000686 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000686 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24395.538646 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 24395.538646 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 24395.538646 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 24395.538646 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 24395.538646 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 24395.538646 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25867.895933 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25867.895933 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25867.895933 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25867.895933 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25867.895933 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25867.895933 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -489,38 +489,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15836 system.cpu.icache.demand_mshr_misses::total 15836 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15836 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15836 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 353292250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 353292250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 353292250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 353292250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 353292250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 353292250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 384517500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 384517500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 384517500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 384517500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 384517500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 384517500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000686 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000686 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000686 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22309.437358 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22309.437358 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22309.437358 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22309.437358 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22309.437358 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22309.437358 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24281.226320 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24281.226320 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24281.226320 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24281.226320 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24281.226320 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24281.226320 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2479.833240 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2479.394298 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 12735 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3665 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 3.474761 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.780071 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2101.017125 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 361.036043 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 17.779390 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2100.640552 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 360.974356 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064118 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.011018 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.075679 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064106 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.011016 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.075665 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 3665 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id @@ -554,17 +554,17 @@ system.cpu.l2cache.demand_misses::total 5318 # nu system.cpu.l2cache.overall_misses::cpu.inst 3167 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2151 # number of overall misses system.cpu.l2cache.overall_misses::total 5318 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 210776750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 33082500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 243859250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 115635000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 115635000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 210776750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 148717500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 359494250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 210776750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 148717500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 359494250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 235668000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35962750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 271630750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 128723250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 128723250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 235668000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 164686000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 400354000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 235668000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 164686000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 400354000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 15835 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 485 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 16320 # number of ReadReq accesses(hits+misses) @@ -589,17 +589,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.294381 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200000 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964574 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.294381 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66554.073255 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76579.861111 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67757.502084 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67268.760908 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67268.760908 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66554.073255 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69138.772664 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67599.520496 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66554.073255 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69138.772664 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67599.520496 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74413.640669 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83247.106481 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75473.951098 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74882.635253 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74882.635253 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74413.640669 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76562.529056 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75282.813088 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74413.640669 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76562.529056 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75282.813088 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -619,17 +619,17 @@ system.cpu.l2cache.demand_mshr_misses::total 5318 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3167 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2151 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5318 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 170928750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27694500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 198623250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 93817500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 93817500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 170928750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 121512000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 292440750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 170928750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 121512000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 292440750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 196043000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 30551250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 226594250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 107188750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 107188750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 196043000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137740000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 333783000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 196043000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137740000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 333783000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200000 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.890722 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.220527 # mshr miss rate for ReadReq accesses @@ -641,17 +641,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.294381 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200000 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.294381 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53971.818756 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64107.638889 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55188.455126 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54576.788831 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54576.788831 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53971.818756 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56490.934449 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54990.739000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53971.818756 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56490.934449 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54990.739000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61901.799811 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70720.486111 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62960.336205 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62355.293775 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62355.293775 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61901.799811 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64035.332404 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62764.761188 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61901.799811 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64035.332404 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62764.761188 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 16320 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 16320 # Transaction distribution @@ -678,9 +678,9 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 # system.cpu.toL2Bus.snoop_fanout::total 18172 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 9193000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 24435250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 24439500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3734000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3770500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.trans_dist::ReadReq 3599 # Transaction distribution system.membus.trans_dist::ReadResp 3599 # Transaction distribution @@ -701,9 +701,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 5318 # Request fanout histogram -system.membus.reqLayer0.occupancy 6478000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6453000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 50027750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 28232500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index fbd001a0c..9c86c55d6 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.022159 # Number of seconds simulated -sim_ticks 22159411000 # Number of ticks simulated -final_tick 22159411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.022229 # Number of seconds simulated +sim_ticks 22228749500 # Number of ticks simulated +final_tick 22228749500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 210811 # Simulator instruction rate (inst/s) -host_op_rate 210811 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55493646 # Simulator tick rate (ticks/s) -host_mem_usage 299980 # Number of bytes of host memory used -host_seconds 399.31 # Real time elapsed on the host +host_inst_rate 212613 # Simulator instruction rate (inst/s) +host_op_rate 212613 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56143360 # Simulator tick rate (ticks/s) +host_mem_usage 300388 # Number of bytes of host memory used +host_seconds 395.93 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 196160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138688 # Number of bytes read from this memory -system.physmem.bytes_read::total 334848 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 196160 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 196160 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3065 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2167 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5232 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8852221 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6258650 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15110871 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8852221 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8852221 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8852221 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6258650 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15110871 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5232 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 196032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138560 # Number of bytes read from this memory +system.physmem.bytes_read::total 334592 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 196032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 196032 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3063 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2165 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5228 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8818850 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6233369 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15052219 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8818850 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8818850 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8818850 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6233369 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15052219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5228 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5232 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5228 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 334848 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 334592 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 334848 # Total read bytes from the system interface side +system.physmem.bytesReadSys 334592 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 471 # Per bank write bursts -system.physmem.perBankRdBursts::1 289 # Per bank write bursts +system.physmem.perBankRdBursts::0 472 # Per bank write bursts +system.physmem.perBankRdBursts::1 290 # Per bank write bursts system.physmem.perBankRdBursts::2 302 # Per bank write bursts -system.physmem.perBankRdBursts::3 527 # Per bank write bursts -system.physmem.perBankRdBursts::4 218 # Per bank write bursts +system.physmem.perBankRdBursts::3 525 # Per bank write bursts +system.physmem.perBankRdBursts::4 219 # Per bank write bursts system.physmem.perBankRdBursts::5 224 # Per bank write bursts -system.physmem.perBankRdBursts::6 217 # Per bank write bursts -system.physmem.perBankRdBursts::7 287 # Per bank write bursts -system.physmem.perBankRdBursts::8 239 # Per bank write bursts -system.physmem.perBankRdBursts::9 281 # Per bank write bursts -system.physmem.perBankRdBursts::10 249 # Per bank write bursts -system.physmem.perBankRdBursts::11 253 # Per bank write bursts -system.physmem.perBankRdBursts::12 396 # Per bank write bursts +system.physmem.perBankRdBursts::6 218 # Per bank write bursts +system.physmem.perBankRdBursts::7 285 # Per bank write bursts +system.physmem.perBankRdBursts::8 238 # Per bank write bursts +system.physmem.perBankRdBursts::9 279 # Per bank write bursts +system.physmem.perBankRdBursts::10 248 # Per bank write bursts +system.physmem.perBankRdBursts::11 252 # Per bank write bursts +system.physmem.perBankRdBursts::12 398 # Per bank write bursts system.physmem.perBankRdBursts::13 338 # Per bank write bursts -system.physmem.perBankRdBursts::14 493 # Per bank write bursts -system.physmem.perBankRdBursts::15 448 # Per bank write bursts +system.physmem.perBankRdBursts::14 491 # Per bank write bursts +system.physmem.perBankRdBursts::15 449 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22159321500 # Total gap between requests +system.physmem.totGap 22228653000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5232 # Read request sizes (log2) +system.physmem.readPktSize::6 5228 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,12 +90,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3250 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1221 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 631 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1223 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 210 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -188,27 +188,27 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 866 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 383.630485 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 228.084782 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 358.284844 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 269 31.06% 31.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 171 19.75% 50.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 88 10.16% 60.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 63 7.27% 68.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 38 4.39% 72.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 33 3.81% 76.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 35 4.04% 80.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 46 5.31% 85.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 123 14.20% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 225.895164 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 361.482180 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 274 31.64% 31.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 174 20.09% 51.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 79 9.12% 60.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 66 7.62% 68.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 29 3.35% 71.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 37 4.27% 76.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 36 4.16% 80.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 45 5.20% 85.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 126 14.55% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 866 # Bytes accessed per row activation -system.physmem.totQLat 41292000 # Total ticks spent queuing -system.physmem.totMemAccLat 139392000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26160000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7892.20 # Average queueing delay per DRAM burst +system.physmem.totQLat 39875750 # Total ticks spent queuing +system.physmem.totMemAccLat 137900750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26140000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7627.34 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26642.20 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 15.11 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26377.34 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 15.05 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 15.11 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 15.05 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.12 # Data bus utilization in percentage @@ -216,70 +216,70 @@ system.physmem.busUtilRead 0.12 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4354 # Number of row buffer hits during reads +system.physmem.readRowHits 4353 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.22 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.26 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4235344.32 # Average gap between requests -system.physmem.pageHitRate 83.22 # Row buffer hit rate, read and write combined +system.physmem.avgGap 4251846.40 # Average gap between requests +system.physmem.pageHitRate 83.26 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 3137400 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 1711875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 19453200 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 19476600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1446853200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 894020490 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 12507056250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14872232415 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.367713 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 20804380500 # Time in different power states -system.physmem_0.memoryStateTime::REF 739700000 # Time in different power states +system.physmem_0.refreshEnergy 1451430240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 894518100 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 12548665500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14918939715 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.352430 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 20873521000 # Time in different power states +system.physmem_0.memoryStateTime::REF 742040000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 608242500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 606815000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3341520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1823250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 20802600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3349080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1827375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 20794800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1446853200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 920005650 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 12484262250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 14877088470 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.586927 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 20766250250 # Time in different power states -system.physmem_1.memoryStateTime::REF 739700000 # Time in different power states +system.physmem_1.refreshEnergy 1451430240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 919030095 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 12527163750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14923595340 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.561933 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 20841181500 # Time in different power states +system.physmem_1.memoryStateTime::REF 742040000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 646430250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 642887000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 16298030 # Number of BP lookups -system.cpu.branchPred.condPredicted 11843884 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 974423 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8872850 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7618799 # Number of BTB hits +system.cpu.branchPred.lookups 16323961 # Number of BP lookups +system.cpu.branchPred.condPredicted 11865379 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 978310 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9045215 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7641567 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 85.866424 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1608574 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 439 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 84.481872 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1608650 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 453 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 24142171 # DTB read hits -system.cpu.dtb.read_misses 235539 # DTB read misses +system.cpu.dtb.read_hits 24152698 # DTB read hits +system.cpu.dtb.read_misses 236585 # DTB read misses system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 24377710 # DTB read accesses -system.cpu.dtb.write_hits 7161357 # DTB write hits -system.cpu.dtb.write_misses 1208 # DTB write misses -system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_accesses 7162565 # DTB write accesses -system.cpu.dtb.data_hits 31303528 # DTB hits -system.cpu.dtb.data_misses 236747 # DTB misses -system.cpu.dtb.data_acv 3 # DTB access violations -system.cpu.dtb.data_accesses 31540275 # DTB accesses -system.cpu.itb.fetch_hits 16127186 # ITB hits -system.cpu.itb.fetch_misses 86 # ITB misses +system.cpu.dtb.read_accesses 24389283 # DTB read accesses +system.cpu.dtb.write_hits 7160578 # DTB write hits +system.cpu.dtb.write_misses 1214 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 7161792 # DTB write accesses +system.cpu.dtb.data_hits 31313276 # DTB hits +system.cpu.dtb.data_misses 237799 # DTB misses +system.cpu.dtb.data_acv 2 # DTB access violations +system.cpu.dtb.data_accesses 31551075 # DTB accesses +system.cpu.itb.fetch_hits 16159751 # ITB hits +system.cpu.itb.fetch_misses 85 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 16127272 # ITB accesses +system.cpu.itb.fetch_accesses 16159836 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,139 +293,140 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 44318823 # number of cpu cycles simulated +system.cpu.numCycles 44457500 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 16859439 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 139373095 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16298030 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9227373 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 26218422 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2029202 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 113 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2359 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 16127186 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 380559 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 44094963 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.160749 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.432020 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 16896881 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 139613933 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16323961 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9250217 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 26293708 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2036816 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 2 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 203 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2338 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 16159751 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 382144 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 44211553 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.157861 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.431266 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19653198 44.57% 44.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2660337 6.03% 50.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1339868 3.04% 53.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1948475 4.42% 58.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3047157 6.91% 64.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1303414 2.96% 67.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1381873 3.13% 71.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 894467 2.03% 73.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11866174 26.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19722112 44.61% 44.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2663068 6.02% 50.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1345508 3.04% 53.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1957580 4.43% 58.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3052640 6.90% 65.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1306785 2.96% 67.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1385791 3.13% 71.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 896674 2.03% 73.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11881395 26.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 44094963 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.367745 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.144783 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 13063435 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8246931 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19674377 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2107337 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1002883 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2678530 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12053 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 133445502 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 49010 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1002883 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 14206625 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4728440 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8922 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20521133 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3626960 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 129917938 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 71936 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1987853 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1348485 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 46206 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 95420653 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 168813407 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 161260201 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7553205 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 44211553 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.367181 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.140391 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 13076592 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8324763 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19681975 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2121490 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1006733 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2681054 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12065 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 133596496 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 48387 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1006733 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 14226924 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4752424 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9184 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20532599 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3683689 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 130038627 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 69797 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2001155 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1372929 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 55394 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 95511389 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 168978901 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 161414982 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7563918 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 26993292 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 764 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 773 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8204907 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 27105677 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8747640 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3541499 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1618929 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 112639456 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1940 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 100102500 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 120259 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 27967887 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 21886191 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1551 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 44094963 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.270157 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.096378 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 27084028 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 772 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 782 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8280120 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 27136625 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8757663 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3565364 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1670156 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 112744524 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2237 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 100145020 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 122649 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 28075682 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 21979359 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1848 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 44211553 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.265132 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.094303 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11535006 26.16% 26.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 7754470 17.59% 43.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7555421 17.13% 60.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5737104 13.01% 73.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4489384 10.18% 84.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2977388 6.75% 90.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2013844 4.57% 95.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1160432 2.63% 98.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 871914 1.98% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11585483 26.20% 26.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 7800031 17.64% 43.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7580714 17.15% 60.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5746471 13.00% 73.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4482670 10.14% 84.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2978699 6.74% 90.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2013201 4.55% 95.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1153505 2.61% 98.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 870779 1.97% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 44094963 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44211553 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 479018 20.14% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 443 0.02% 20.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 33638 1.41% 21.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 11723 0.49% 22.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1006429 42.32% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 686405 28.86% 93.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 160330 6.74% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 481856 20.25% 20.25% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 20.25% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 20.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 350 0.01% 20.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 34531 1.45% 21.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 11644 0.49% 22.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1006485 42.29% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 687304 28.88% 93.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 157568 6.62% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60895268 60.83% 60.83% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 491428 0.49% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60921013 60.83% 60.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 491088 0.49% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2836761 2.83% 64.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115534 0.12% 64.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2437739 2.44% 66.71% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 313998 0.31% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 765483 0.76% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2841000 2.84% 64.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115643 0.12% 64.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2440640 2.44% 66.71% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 314095 0.31% 67.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 766051 0.76% 67.79% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.79% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.79% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.79% # Type of FU issued @@ -447,84 +448,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.79% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.79% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.79% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24980978 24.96% 92.74% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7264985 7.26% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24991126 24.95% 92.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7264038 7.25% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 100102500 # Type of FU issued -system.cpu.iq.rate 2.258690 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2377986 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023756 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 231175586 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 131029945 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 90008848 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15622622 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9621224 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7166740 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 94135370 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8345109 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1908744 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 100145020 # Type of FU issued +system.cpu.iq.rate 2.252601 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2379738 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023763 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 231363005 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 131215529 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 90039702 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15640975 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9648680 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7175345 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 94170320 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8354431 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1902679 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 7109479 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 10719 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 42241 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2246537 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 7140427 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11100 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 42139 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2256560 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 42761 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2468 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 42760 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1687 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1002883 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3707612 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 461807 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 123638491 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 278104 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 27105677 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8747640 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1940 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 39979 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 414885 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 42241 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 554445 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 525545 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1079990 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 98729735 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 24378234 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1372765 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1006733 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3731793 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 447885 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 123749930 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 277756 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 27136625 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8757663 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2237 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 43684 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 396903 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 42139 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 560048 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 524506 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1084554 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 98770041 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 24389817 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1374979 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10997095 # number of nop insts executed -system.cpu.iew.exec_refs 31540837 # number of memory reference insts executed -system.cpu.iew.exec_branches 12532490 # Number of branches executed -system.cpu.iew.exec_stores 7162603 # Number of stores executed -system.cpu.iew.exec_rate 2.227716 # Inst execution rate -system.cpu.iew.wb_sent 97918369 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 97175588 # cumulative count of insts written-back -system.cpu.iew.wb_producers 67088120 # num instructions producing a value -system.cpu.iew.wb_consumers 95122376 # num instructions consuming a value +system.cpu.iew.exec_nop 11003169 # number of nop insts executed +system.cpu.iew.exec_refs 31551638 # number of memory reference insts executed +system.cpu.iew.exec_branches 12536484 # Number of branches executed +system.cpu.iew.exec_stores 7161821 # Number of stores executed +system.cpu.iew.exec_rate 2.221673 # Inst execution rate +system.cpu.iew.wb_sent 97959187 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 97215047 # cumulative count of insts written-back +system.cpu.iew.wb_producers 67118954 # num instructions producing a value +system.cpu.iew.wb_consumers 95176065 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.192648 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.705282 # average fanout of values written-back +system.cpu.iew.wb_rate 2.186696 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.705208 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 31736961 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 31848480 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 962705 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 39466887 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.328612 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.908948 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 966635 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 39567002 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.322720 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.905630 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 14969500 37.93% 37.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8597582 21.78% 59.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3898491 9.88% 69.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1956472 4.96% 74.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1378246 3.49% 78.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1028775 2.61% 80.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 694003 1.76% 82.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 732346 1.86% 84.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6211472 15.74% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15032687 37.99% 37.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8622118 21.79% 59.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3917590 9.90% 69.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1951695 4.93% 74.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1384336 3.50% 78.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1033619 2.61% 80.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 694183 1.75% 82.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 726057 1.84% 84.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6204717 15.68% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 39466887 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 39567002 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -570,345 +571,345 @@ system.cpu.commit.op_class_0::MemWrite 6501103 7.07% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction -system.cpu.commit.bw_lim_events 6211472 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6204717 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 156894391 # The number of ROB reads -system.cpu.rob.rob_writes 251967276 # The number of ROB writes -system.cpu.timesIdled 4539 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 223860 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 157112780 # The number of ROB reads +system.cpu.rob.rob_writes 252206838 # The number of ROB writes +system.cpu.timesIdled 4633 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 245947 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.526479 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.526479 # CPI: Total CPI of All Threads -system.cpu.ipc 1.899412 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.899412 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 133358103 # number of integer regfile reads -system.cpu.int_regfile_writes 73122882 # number of integer regfile writes -system.cpu.fp_regfile_reads 6250590 # number of floating regfile reads -system.cpu.fp_regfile_writes 6153622 # number of floating regfile writes -system.cpu.misc_regfile_reads 718773 # number of misc regfile reads +system.cpu.cpi 0.528126 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.528126 # CPI: Total CPI of All Threads +system.cpu.ipc 1.893487 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.893487 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 133407543 # number of integer regfile reads +system.cpu.int_regfile_writes 73150911 # number of integer regfile writes +system.cpu.fp_regfile_reads 6256040 # number of floating regfile reads +system.cpu.fp_regfile_writes 6161921 # number of floating regfile writes +system.cpu.misc_regfile_reads 718993 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 160 # number of replacements -system.cpu.dcache.tags.tagsinuse 1457.564933 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28680753 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2248 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12758.342082 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 159 # number of replacements +system.cpu.dcache.tags.tagsinuse 1458.668074 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28697534 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2246 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12777.174533 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1457.564933 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.355851 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.355851 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2088 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1458.668074 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.356120 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.356120 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2087 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 542 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1388 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.509766 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 57382576 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 57382576 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22187756 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22187756 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492735 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492735 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 262 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 262 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28680491 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28680491 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28680491 # number of overall hits -system.cpu.dcache.overall_hits::total 28680491 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1042 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1042 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8368 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8368 # number of WriteReq misses +system.cpu.dcache.tags.age_task_id_blocks_1024::2 541 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1390 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.509521 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 57416312 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 57416312 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22204643 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22204643 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492628 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492628 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 263 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 263 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28697271 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28697271 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28697271 # number of overall hits +system.cpu.dcache.overall_hits::total 28697271 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1023 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1023 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8475 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8475 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9410 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9410 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9410 # number of overall misses -system.cpu.dcache.overall_misses::total 9410 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 65475750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 65475750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 523849968 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 523849968 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 589325718 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 589325718 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 589325718 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 589325718 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22188798 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22188798 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9498 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9498 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9498 # number of overall misses +system.cpu.dcache.overall_misses::total 9498 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 69711000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 69711000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 550954965 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 550954965 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 85000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 85000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 620665965 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 620665965 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 620665965 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 620665965 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22205666 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22205666 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 263 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 263 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28689901 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28689901 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28689901 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28689901 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000047 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000047 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001287 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001287 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003802 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003802 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000328 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000328 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000328 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000328 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62836.612284 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62836.612284 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62601.573614 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62601.573614 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62627.600213 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62627.600213 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62627.600213 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62627.600213 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29227 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 416 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 894 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.692394 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 208 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 264 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 264 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28706769 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28706769 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28706769 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28706769 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001304 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001304 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003788 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003788 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000331 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000331 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000331 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000331 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68143.695015 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68143.695015 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65009.435398 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65009.435398 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65347.016740 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65347.016740 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65347.016740 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65347.016740 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 33287 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 426 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 78.138498 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 110 # number of writebacks -system.cpu.dcache.writebacks::total 110 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 529 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 529 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7163 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7163 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7163 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7163 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 513 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 513 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 109 # number of writebacks +system.cpu.dcache.writebacks::total 109 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 512 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 512 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6741 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6741 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7253 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7253 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7253 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7253 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 511 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 511 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1734 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1734 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2247 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2247 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2247 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2247 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36153000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36153000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 125731745 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 125731745 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161884745 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 161884745 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161884745 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 161884745 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2245 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2245 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2245 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2245 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 38736500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 38736500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 136484495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 136484495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 83500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 83500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 175220995 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 175220995 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 175220995 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 175220995 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000267 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.003802 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.003802 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.003788 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.003788 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000078 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000078 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70473.684211 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70473.684211 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72509.656863 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72509.656863 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72044.835336 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72044.835336 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72044.835336 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72044.835336 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75805.283757 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75805.283757 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78710.781430 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78710.781430 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 83500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 83500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78049.440980 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78049.440980 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78049.440980 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78049.440980 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 9583 # number of replacements -system.cpu.icache.tags.tagsinuse 1600.631053 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 16112652 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 11519 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1398.789131 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 9845 # number of replacements +system.cpu.icache.tags.tagsinuse 1600.510636 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 16144798 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 11783 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1370.177204 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1600.631053 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.781558 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.781558 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1936 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 763 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 930 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 32265889 # Number of tag accesses -system.cpu.icache.tags.data_accesses 32265889 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 16112652 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 16112652 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 16112652 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 16112652 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 16112652 # number of overall hits -system.cpu.icache.overall_hits::total 16112652 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14533 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14533 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14533 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14533 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14533 # number of overall misses -system.cpu.icache.overall_misses::total 14533 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 419570250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 419570250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 419570250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 419570250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 419570250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 419570250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 16127185 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 16127185 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 16127185 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 16127185 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 16127185 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 16127185 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000901 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000901 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000901 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000901 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000901 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000901 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28870.174775 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28870.174775 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28870.174775 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28870.174775 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28870.174775 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28870.174775 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 196 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1600.510636 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.781499 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.781499 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1938 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 760 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 936 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.946289 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 32331281 # Number of tag accesses +system.cpu.icache.tags.data_accesses 32331281 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 16144798 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 16144798 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 16144798 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 16144798 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 16144798 # number of overall hits +system.cpu.icache.overall_hits::total 16144798 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14951 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14951 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14951 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14951 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14951 # number of overall misses +system.cpu.icache.overall_misses::total 14951 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 446766000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 446766000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 446766000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 446766000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 446766000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 446766000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 16159749 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 16159749 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 16159749 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 16159749 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 16159749 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 16159749 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000925 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000925 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000925 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000925 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000925 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000925 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29882.014581 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 29882.014581 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 29882.014581 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 29882.014581 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 29882.014581 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 29882.014581 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 502 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 39.200000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 55.777778 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3014 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3014 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3014 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3014 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3014 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3014 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11519 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 11519 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 11519 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 11519 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 11519 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 11519 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 306551250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 306551250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 306551250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 306551250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 306551250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 306551250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000714 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000714 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000714 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000714 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000714 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000714 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26612.661689 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26612.661689 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26612.661689 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 26612.661689 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26612.661689 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 26612.661689 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3168 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3168 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3168 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3168 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3168 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3168 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11783 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 11783 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 11783 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 11783 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 11783 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 11783 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 332403750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 332403750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 332403750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 332403750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 332403750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 332403750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000729 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000729 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000729 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000729 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000729 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000729 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28210.451498 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28210.451498 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28210.451498 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 28210.451498 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28210.451498 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 28210.451498 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2401.991328 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8524 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3591 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.373712 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2407.331968 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8790 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3587 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.450516 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.703660 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.347225 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 376.940444 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 17.698797 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2011.289043 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 378.344128 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000540 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061259 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.011503 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.073303 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3591 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 915 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2425 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.109589 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 116342 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 116342 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 8454 # number of ReadReq hits +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061380 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.011546 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.073466 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3587 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 911 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2430 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.109467 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 118425 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 118425 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 8720 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 55 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 8509 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 110 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 110 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::total 8775 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 109 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 109 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 8454 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 8720 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 81 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 8535 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 8454 # number of overall hits +system.cpu.l2cache.demand_hits::total 8801 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 8720 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 81 # number of overall hits -system.cpu.l2cache.overall_hits::total 8535 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3065 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 458 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 3523 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 1709 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1709 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3065 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2167 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 5232 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3065 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2167 # number of overall misses -system.cpu.l2cache.overall_misses::total 5232 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 210484500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35100000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 245584500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 123658250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 123658250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 210484500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 158758250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 369242750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 210484500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 158758250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 369242750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 11519 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 513 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 12032 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 110 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 110 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1735 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1735 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 11519 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2248 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 13767 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 11519 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2248 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 13767 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.266082 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.892788 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.292803 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985014 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.985014 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.266082 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.963968 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.380039 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.266082 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.963968 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.380039 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68673.572594 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76637.554585 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69708.912858 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72357.080164 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72357.080164 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68673.572594 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73261.767420 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70573.920107 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68673.572594 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73261.767420 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70573.920107 # average overall miss latency +system.cpu.l2cache.overall_hits::total 8801 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3063 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 457 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 3520 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1708 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1708 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3063 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2165 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 5228 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3063 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2165 # number of overall misses +system.cpu.l2cache.overall_misses::total 5228 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 229052250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 37709500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 266761750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 134332250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 134332250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 229052250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 172041750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 401094000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 229052250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 172041750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 401094000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 11783 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 512 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 12295 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 109 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 109 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1734 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1734 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 11783 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2246 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 14029 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 11783 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2246 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 14029 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.259951 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.892578 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.286295 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985006 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.985006 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.259951 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.963936 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.372657 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.259951 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.963936 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.372657 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74780.362390 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82515.317287 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75784.588068 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78648.858314 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78648.858314 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74780.362390 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79465.011547 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76720.351951 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74780.362390 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79465.011547 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76720.351951 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -917,102 +918,102 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3065 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 458 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3523 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1709 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1709 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3065 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2167 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5232 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3065 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2167 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5232 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 171659500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 29415000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 201074500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 102798250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 102798250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 171659500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 132213250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 303872750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 171659500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 132213250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 303872750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.266082 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.892788 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.292803 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985014 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985014 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.266082 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963968 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.380039 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.266082 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963968 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.380039 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56006.362153 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64224.890830 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57074.794209 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60151.111761 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60151.111761 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56006.362153 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61012.113521 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58079.654052 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56006.362153 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61012.113521 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58079.654052 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3063 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 457 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3520 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1708 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1708 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3063 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2165 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5228 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3063 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2165 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5228 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 190854250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 31997500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 222851750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 113271750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 113271750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 190854250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 145269250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 336123500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 190854250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 145269250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 336123500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.259951 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.892578 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.286295 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985006 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985006 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.259951 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963936 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.372657 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.259951 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963936 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.372657 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62309.582109 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70016.411379 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63310.156250 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66318.354801 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66318.354801 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62309.582109 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67098.960739 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64292.941852 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62309.582109 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67098.960739 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64292.941852 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 12032 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 12032 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 110 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1735 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1735 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23038 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4606 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27644 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 888128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 12295 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 12295 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 109 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1734 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1734 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23566 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4601 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 28167 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 754112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 904832 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 13877 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 14138 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 13877 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 14138 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 13877 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7048500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 14138 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7178000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 17856250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 18279750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3547750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3635750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 3523 # Transaction distribution -system.membus.trans_dist::ReadResp 3523 # Transaction distribution -system.membus.trans_dist::ReadExReq 1709 # Transaction distribution -system.membus.trans_dist::ReadExResp 1709 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10464 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10464 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334848 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 334848 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 3520 # Transaction distribution +system.membus.trans_dist::ReadResp 3520 # Transaction distribution +system.membus.trans_dist::ReadExReq 1708 # Transaction distribution +system.membus.trans_dist::ReadExResp 1708 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10456 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10456 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334592 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 334592 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5232 # Request fanout histogram +system.membus.snoop_fanout::samples 5228 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5232 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5228 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5232 # Request fanout histogram -system.membus.reqLayer0.occupancy 6529000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5228 # Request fanout histogram +system.membus.reqLayer0.occupancy 6467500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 48920250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 27502000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index 4e099442b..85445221a 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.118729 # Number of seconds simulated -sim_ticks 118729316000 # Number of ticks simulated -final_tick 118729316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 118729316500 # Number of ticks simulated +final_tick 118729316500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1660785 # Simulator instruction rate (inst/s) -host_op_rate 1660785 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2145562848 # Simulator tick rate (ticks/s) -host_mem_usage 293264 # Number of bytes of host memory used -host_seconds 55.34 # Real time elapsed on the host +host_inst_rate 1507080 # Simulator instruction rate (inst/s) +host_op_rate 1507080 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1946992285 # Simulator tick rate (ticks/s) +host_mem_usage 297820 # Number of bytes of host memory used +host_seconds 60.98 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,29 +29,6 @@ system.physmem.bw_inst_read::total 1412827 # In system.physmem.bw_total::cpu.inst 1412827 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1155704 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2568532 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 3043 # Transaction distribution -system.membus.trans_dist::ReadResp 3043 # Transaction distribution -system.membus.trans_dist::ReadExReq 1722 # Transaction distribution -system.membus.trans_dist::ReadExResp 1722 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9530 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 9530 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 304960 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 304960 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 4765 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4765 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 4765 # Request fanout histogram -system.membus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 42885000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -86,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 237458632 # number of cpu cycles simulated +system.cpu.numCycles 237458633 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 91903056 # Number of instructions committed @@ -105,7 +82,7 @@ system.cpu.num_mem_refs 26497334 # nu system.cpu.num_load_insts 19996208 # Number of load instructions system.cpu.num_store_insts 6501126 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 237458632 # Number of busy cycles +system.cpu.num_busy_cycles 237458633 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 10240685 # Number of branches fetched @@ -144,13 +121,122 @@ system.cpu.op_class::MemWrite 6501126 7.07% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91903089 # Class of executed instruction +system.cpu.dcache.tags.replacements 157 # number of replacements +system.cpu.dcache.tags.tagsinuse 1442.043377 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26495078 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11918.613585 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1442.043377 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.352061 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2066 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 173 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 487 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1372 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.504395 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 52996825 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 52996825 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6499355 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26495078 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26495078 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26495078 # number of overall hits +system.cpu.dcache.overall_hits::total 26495078 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 475 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 475 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1748 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1748 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2223 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses +system.cpu.dcache.overall_misses::total 2223 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 23899000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 23899000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 95048000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 95048000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 118947000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 118947000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 118947000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 118947000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000269 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50313.684211 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50313.684211 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54375.286041 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54375.286041 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53507.422402 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53507.422402 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 107 # number of writebacks +system.cpu.dcache.writebacks::total 107 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23186500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23186500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92426000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 92426000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 115612500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 115612500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 115612500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 115612500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48813.684211 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48813.684211 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52875.286041 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52875.286041 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52007.422402 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52007.422402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52007.422402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52007.422402 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 6681 # number of replacements -system.cpu.icache.tags.tagsinuse 1418.052773 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1418.052759 # Cycle average of tags in use system.cpu.icache.tags.total_refs 91894580 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 8510 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 10798.423032 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1418.052773 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1418.052759 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.692409 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.692409 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id @@ -174,12 +260,12 @@ system.cpu.icache.demand_misses::cpu.inst 8510 # n system.cpu.icache.demand_misses::total 8510 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 8510 # number of overall misses system.cpu.icache.overall_misses::total 8510 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 220712000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 220712000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 220712000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 220712000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 220712000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 220712000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 220712500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 220712500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 220712500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 220712500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 220712500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 220712500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 91903090 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 91903090 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 91903090 # number of demand (read+write) accesses @@ -192,12 +278,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25935.605170 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25935.605170 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25935.605170 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25935.605170 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25935.605170 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25935.605170 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25935.663925 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25935.663925 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25935.663925 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25935.663925 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25935.663925 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25935.663925 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -212,34 +298,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 8510 system.cpu.icache.demand_mshr_misses::total 8510 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 8510 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 8510 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 203692000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 203692000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 203692000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 203692000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 203692000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 203692000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 207947500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 207947500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 207947500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 207947500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 207947500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 207947500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000093 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000093 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23935.605170 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23935.605170 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24435.663925 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24435.663925 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24435.663925 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24435.663925 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24435.663925 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24435.663925 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2074.070560 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2074.070538 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 5956 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3109 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.915729 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.795178 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1705.018003 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 351.257379 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 17.795177 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1705.017985 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 351.257376 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052033 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.010720 # Average percentage of cache occupancy @@ -277,17 +363,17 @@ system.cpu.l2cache.demand_misses::total 4765 # nu system.cpu.l2cache.overall_misses::cpu.inst 2621 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4765 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 136292000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21944000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 158236000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 89544000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 89544000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 136292000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 111488000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 247780000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 136292000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 111488000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 247780000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 137603000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22155000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 159758000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 90405000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 90405000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 137603000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 112560000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 250163000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 137603000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 112560000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 250163000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 8510 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 8985 # number of ReadReq accesses(hits+misses) @@ -312,17 +398,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.443958 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.307991 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.443958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.190767 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.164312 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.190767 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.104932 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.190767 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.104932 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -342,17 +428,17 @@ system.cpu.l2cache.demand_mshr_misses::total 4765 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2621 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4765 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104840000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16880000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 121720000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 68880000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 68880000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104840000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 85760000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 190600000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104840000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 85760000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 190600000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 106150500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17091000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 123241500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69741000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69741000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106150500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86832000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 192982500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106150500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86832000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 192982500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.338676 # mshr miss rate for ReadReq accesses @@ -364,127 +450,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.443958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.443958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1442.043392 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26495078 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11918.613585 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1442.043392 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.352061 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2066 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 173 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 487 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1372 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.504395 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 52996825 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 52996825 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6499355 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26495078 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26495078 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26495078 # number of overall hits -system.cpu.dcache.overall_hits::total 26495078 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 475 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 475 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1748 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1748 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2223 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses -system.cpu.dcache.overall_misses::total 2223 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 23899000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 23899000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 95048000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 95048000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 118947000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 118947000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 118947000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 118947000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000269 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50313.684211 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50313.684211 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54375.286041 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54375.286041 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 53507.422402 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 53507.422402 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 107 # number of writebacks -system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22949000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 22949000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 91552000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 91552000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114501000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 114501000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114501000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 114501000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48313.684211 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48313.684211 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52375.286041 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52375.286041 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 8985 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 8985 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution @@ -514,5 +491,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 12765000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3334500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 3043 # Transaction distribution +system.membus.trans_dist::ReadResp 3043 # Transaction distribution +system.membus.trans_dist::ReadExReq 1722 # Transaction distribution +system.membus.trans_dist::ReadExResp 1722 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9530 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 9530 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 304960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 304960 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 4765 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 4765 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 4765 # Request fanout histogram +system.membus.reqLayer0.occupancy 4765500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 23825500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index c2d632546..f13570e98 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.131746 # Number of seconds simulated -sim_ticks 131745950000 # Number of ticks simulated -final_tick 131745950000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.131756 # Number of seconds simulated +sim_ticks 131756455500 # Number of ticks simulated +final_tick 131756455500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 165378 # Simulator instruction rate (inst/s) -host_op_rate 174335 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 126440065 # Simulator tick rate (ticks/s) -host_mem_usage 304748 # Number of bytes of host memory used -host_seconds 1041.96 # Real time elapsed on the host +host_inst_rate 249754 # Simulator instruction rate (inst/s) +host_op_rate 263281 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 190965456 # Simulator tick rate (ticks/s) +host_mem_usage 316672 # Number of bytes of host memory used +host_seconds 689.95 # Real time elapsed on the host sim_insts 172317809 # Number of instructions simulated sim_ops 181650742 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 138176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 138304 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory -system.physmem.bytes_read::total 247488 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 138176 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 138176 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2159 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 247616 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 138304 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 138304 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2161 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3867 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1048806 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 829718 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1878525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1048806 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1048806 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1048806 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 829718 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1878525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3867 # Number of read requests accepted +system.physmem.num_reads::total 3869 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1049694 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 829652 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1879346 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1049694 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1049694 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1049694 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 829652 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1879346 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3869 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 3867 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 3869 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 247488 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 247616 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 247488 # Total read bytes from the system interface side +system.physmem.bytesReadSys 247616 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -45,18 +45,18 @@ system.physmem.perBankRdBursts::0 305 # Pe system.physmem.perBankRdBursts::1 217 # Per bank write bursts system.physmem.perBankRdBursts::2 135 # Per bank write bursts system.physmem.perBankRdBursts::3 313 # Per bank write bursts -system.physmem.perBankRdBursts::4 308 # Per bank write bursts +system.physmem.perBankRdBursts::4 307 # Per bank write bursts system.physmem.perBankRdBursts::5 305 # Per bank write bursts system.physmem.perBankRdBursts::6 273 # Per bank write bursts system.physmem.perBankRdBursts::7 222 # Per bank write bursts system.physmem.perBankRdBursts::8 249 # Per bank write bursts system.physmem.perBankRdBursts::9 218 # Per bank write bursts system.physmem.perBankRdBursts::10 295 # Per bank write bursts -system.physmem.perBankRdBursts::11 199 # Per bank write bursts +system.physmem.perBankRdBursts::11 201 # Per bank write bursts system.physmem.perBankRdBursts::12 183 # Per bank write bursts system.physmem.perBankRdBursts::13 218 # Per bank write bursts system.physmem.perBankRdBursts::14 224 # Per bank write bursts -system.physmem.perBankRdBursts::15 203 # Per bank write bursts +system.physmem.perBankRdBursts::15 204 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 131745861500 # Total gap between requests +system.physmem.totGap 131756361000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 3867 # Read request sizes (log2) +system.physmem.readPktSize::6 3869 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,7 +90,7 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3616 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3618 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 238 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 912 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 269.543860 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 178.691365 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 273.658023 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 266 29.17% 29.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 353 38.71% 67.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 82 8.99% 76.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 61 6.69% 83.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 33 3.62% 87.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 27 2.96% 90.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 14 1.54% 91.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 19 2.08% 93.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 57 6.25% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 912 # Bytes accessed per row activation -system.physmem.totQLat 28130750 # Total ticks spent queuing -system.physmem.totMemAccLat 100637000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 19335000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7274.57 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 895 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 274.663687 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.028895 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 274.690311 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 245 27.37% 27.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 357 39.89% 67.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 81 9.05% 76.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 51 5.70% 82.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 43 4.80% 86.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 26 2.91% 89.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 22 2.46% 92.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 16 1.79% 93.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 54 6.03% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 895 # Bytes accessed per row activation +system.physmem.totQLat 26801000 # Total ticks spent queuing +system.physmem.totMemAccLat 99344750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 19345000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6927.11 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26024.57 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25677.11 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s @@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.01 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 2950 # Number of row buffer hits during reads +system.physmem.readRowHits 2968 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.29 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.71 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34069268.55 # Average gap between requests -system.physmem.pageHitRate 76.29 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3092040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1687125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 16177200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 34054370.90 # Average gap between requests +system.physmem.pageHitRate 76.71 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3069360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1674750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16169400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 8604835200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3575900700 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 75909402750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 88111095015 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.807422 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 126280313250 # Time in different power states -system.physmem_0.memoryStateTime::REF 4399200000 # Time in different power states +system.physmem_0.refreshEnergy 8605343760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3539588850 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 75945927000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 88111773120 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.773044 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 126343733250 # Time in different power states +system.physmem_0.memoryStateTime::REF 4399460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1064296750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1010942750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3787560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2066625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 13767000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3681720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2008875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13774800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 8604835200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3595739265 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 75892008750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 88112204400 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.815773 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 126251429250 # Time in different power states -system.physmem_1.memoryStateTime::REF 4399200000 # Time in different power states +system.physmem_1.refreshEnergy 8605343760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3587668065 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 75903760500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 88116237720 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.806861 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 126271447000 # Time in different power states +system.physmem_1.memoryStateTime::REF 4399460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1093059250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1080937500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 49935043 # Number of BP lookups -system.cpu.branchPred.condPredicted 39664695 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5744224 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24405530 # Number of BTB lookups -system.cpu.branchPred.BTBHits 23309445 # Number of BTB hits +system.cpu.branchPred.lookups 49934480 # Number of BP lookups +system.cpu.branchPred.condPredicted 39666708 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5743450 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 24374232 # Number of BTB lookups +system.cpu.branchPred.BTBHits 23299942 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.508866 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1908457 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 95.592518 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1908561 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 139 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -377,75 +377,75 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 263491900 # number of cpu cycles simulated +system.cpu.numCycles 263512911 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 172317809 # Number of instructions committed system.cpu.committedOps 181650742 # Number of ops (including micro ops) committed -system.cpu.discardedOps 11758002 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 11759003 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.529104 # CPI: cycles per instruction -system.cpu.ipc 0.653978 # IPC: instructions per cycle -system.cpu.tickCycles 257145198 # Number of cycles that the object actually ticked -system.cpu.idleCycles 6346702 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.529226 # CPI: cycles per instruction +system.cpu.ipc 0.653925 # IPC: instructions per cycle +system.cpu.tickCycles 257129924 # Number of cycles that the object actually ticked +system.cpu.idleCycles 6382987 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1377.772724 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40762987 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1377.698544 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40765677 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22520.987293 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22522.473481 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1377.772724 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.336370 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.336370 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1377.698544 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.336352 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.336352 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1358 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.431641 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 81532656 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 81532656 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 28355530 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28355530 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12362643 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12362643 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 81538036 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 81538036 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28358222 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28358222 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12362641 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12362641 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40718173 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40718173 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40718173 # number of overall hits -system.cpu.dcache.overall_hits::total 40718173 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 792 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 792 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1644 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1644 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 40720863 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40720863 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40720863 # number of overall hits +system.cpu.dcache.overall_hits::total 40720863 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 790 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 790 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1646 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1646 # number of WriteReq misses system.cpu.dcache.demand_misses::cpu.data 2436 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 2436 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2436 # number of overall misses system.cpu.dcache.overall_misses::total 2436 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 54011984 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 54011984 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 115610250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 115610250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 169622234 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 169622234 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 169622234 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 169622234 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28356322 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28356322 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57599734 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57599734 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 127302750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 127302750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 184902484 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 184902484 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 184902484 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 184902484 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28359012 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28359012 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 40720609 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 40720609 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 40720609 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 40720609 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 40723299 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 40723299 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 40723299 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 40723299 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses @@ -454,14 +454,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68196.949495 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68196.949495 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70322.536496 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70322.536496 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 69631.458949 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69631.458949 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 69631.458949 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69631.458949 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72911.055696 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72911.055696 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77340.674362 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77340.674362 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 75904.139573 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 75904.139573 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 75904.139573 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 75904.139573 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -472,10 +472,10 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 16 # number of writebacks system.cpu.dcache.writebacks::total 16 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 80 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 546 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 546 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 548 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 548 # number of WriteReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 626 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 626 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 626 # number of overall MSHR hits @@ -488,14 +488,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1810 system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1810 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47293264 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 47293264 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 76508500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 76508500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 123801764 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 123801764 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 123801764 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 123801764 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51193764 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 51193764 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85249250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85249250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136443014 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 136443014 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136443014 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 136443014 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses @@ -504,69 +504,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66423.123596 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66423.123596 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69679.872495 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69679.872495 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68398.764641 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68398.764641 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68398.764641 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68398.764641 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71901.353933 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71901.353933 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77640.482696 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77640.482696 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75382.880663 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75382.880663 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75382.880663 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75382.880663 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 2909 # number of replacements -system.cpu.icache.tags.tagsinuse 1424.880841 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 71614329 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4705 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 15220.898831 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2891 # number of replacements +system.cpu.icache.tags.tagsinuse 1424.909254 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 71597357 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4688 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 15272.473763 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1424.880841 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.695743 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.695743 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1796 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1424.909254 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.695756 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.695756 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 492 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 125 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1068 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.876953 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 143242775 # Number of tag accesses -system.cpu.icache.tags.data_accesses 143242775 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 71614329 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 71614329 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 71614329 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 71614329 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 71614329 # number of overall hits -system.cpu.icache.overall_hits::total 71614329 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4706 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4706 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4706 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4706 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4706 # number of overall misses -system.cpu.icache.overall_misses::total 4706 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 186377497 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 186377497 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 186377497 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 186377497 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 186377497 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 186377497 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 71619035 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 71619035 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 71619035 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 71619035 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 71619035 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 71619035 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39604.228007 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 39604.228007 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 39604.228007 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 39604.228007 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 39604.228007 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 39604.228007 # average overall miss latency +system.cpu.icache.tags.age_task_id_blocks_1024::2 490 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 129 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1067 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.877441 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 143208780 # Number of tag accesses +system.cpu.icache.tags.data_accesses 143208780 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 71597357 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 71597357 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 71597357 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 71597357 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 71597357 # number of overall hits +system.cpu.icache.overall_hits::total 71597357 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4689 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4689 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4689 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4689 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4689 # number of overall misses +system.cpu.icache.overall_misses::total 4689 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 200362248 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 200362248 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 200362248 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 200362248 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 200362248 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 200362248 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 71602046 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 71602046 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 71602046 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 71602046 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 71602046 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 71602046 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000065 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000065 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000065 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000065 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000065 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000065 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42730.272553 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42730.272553 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42730.272553 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42730.272553 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42730.272553 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42730.272553 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -575,123 +575,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4706 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4706 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4706 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4706 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4706 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4706 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 176047503 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 176047503 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 176047503 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 176047503 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 176047503 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 176047503 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37409.159159 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37409.159159 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37409.159159 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37409.159159 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37409.159159 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37409.159159 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4689 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4689 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4689 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4689 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4689 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4689 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192401752 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 192401752 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192401752 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 192401752 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192401752 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 192401752 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000065 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000065 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000065 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41032.576669 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41032.576669 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41032.576669 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 41032.576669 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41032.576669 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 41032.576669 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2001.520471 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2624 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2785 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.942190 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2001.520500 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2606 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2787 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.935056 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 3.029184 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.649056 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 490.842232 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 3.029170 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.676368 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 490.814962 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046010 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.014979 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046011 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.014978 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.061082 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 2785 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 522 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 153 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 2787 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 520 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 157 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2005 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084991 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 56139 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 56139 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2543 # number of ReadReq hits +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.085052 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 56005 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 56005 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 2525 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 80 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2623 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2605 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2543 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 2525 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 88 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2631 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2543 # number of overall hits +system.cpu.l2cache.demand_hits::total 2613 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2525 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 88 # number of overall hits -system.cpu.l2cache.overall_hits::total 2631 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2163 # number of ReadReq misses +system.cpu.l2cache.overall_hits::total 2613 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2164 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 632 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 2795 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 2796 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 1090 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 1090 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2163 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 2164 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 1722 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 3885 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2163 # number of overall misses +system.cpu.l2cache.demand_misses::total 3886 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2164 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1722 # number of overall misses -system.cpu.l2cache.overall_misses::total 3885 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 145907500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 45776750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 191684250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 75329000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 75329000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 145907500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 121105750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 267013250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 145907500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 121105750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 267013250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 4706 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 3886 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 161201250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 49637250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 210838500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84065750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 84065750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 161201250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 133703000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 294904250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 161201250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 133703000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 294904250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 4689 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 712 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 5418 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 5401 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1098 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1098 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 4706 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 4689 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 1810 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 6516 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 4706 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 6499 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4689 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 1810 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 6516 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.459626 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 6499 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.461506 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.887640 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.515873 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.517682 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992714 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.992714 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.459626 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.461506 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.951381 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.596225 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.459626 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.597938 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461506 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.951381 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.596225 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67456.079519 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72431.566456 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68581.127013 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69109.174312 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69109.174312 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67456.079519 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70328.542393 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68729.279279 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67456.079519 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70328.542393 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68729.279279 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.597938 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74492.259704 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78539.952532 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75407.188841 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77124.541284 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77124.541284 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74492.259704 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77644.018583 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75888.896037 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74492.259704 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77644.018583 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75888.896037 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -700,115 +700,113 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 14 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2160 # number of ReadReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2162 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 618 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2778 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2780 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1090 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1090 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2160 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2162 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 1708 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3868 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2160 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3870 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2162 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 3868 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 118562000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 37228000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 155790000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 61501500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61501500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 118562000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 98729500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 217291500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 118562000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 98729500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 217291500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.458989 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 3870 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134008500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 40696500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 174705000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70436750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70436750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134008500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 111133250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 245141750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134008500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 111133250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 245141750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867978 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.512735 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.514719 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992714 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.458989 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.593616 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.458989 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.595476 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.593616 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54889.814815 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60239.482201 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56079.913607 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56423.394495 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56423.394495 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54889.814815 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57804.156909 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56176.706308 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54889.814815 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57804.156909 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56176.706308 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.595476 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61983.580019 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65851.941748 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62843.525180 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64620.871560 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64620.871560 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61983.580019 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65066.305621 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63344.121447 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61983.580019 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65066.305621 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63344.121447 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 5418 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5417 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 5401 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5400 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9411 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9377 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3636 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 13047 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 301120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 13013 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300032 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 417984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 416896 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6532 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 6515 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 6532 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 6515 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6532 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3282000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 6515 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3273500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7517497 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7496248 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2996736 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3020486 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 2777 # Transaction distribution -system.membus.trans_dist::ReadResp 2777 # Transaction distribution +system.membus.trans_dist::ReadReq 2779 # Transaction distribution +system.membus.trans_dist::ReadResp 2779 # Transaction distribution system.membus.trans_dist::ReadExReq 1090 # Transaction distribution system.membus.trans_dist::ReadExResp 1090 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7734 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7734 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247488 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 247488 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7738 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7738 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 247616 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3867 # Request fanout histogram +system.membus.snoop_fanout::samples 3869 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3867 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3869 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3867 # Request fanout histogram -system.membus.reqLayer0.occupancy 4723500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3869 # Request fanout histogram +system.membus.reqLayer0.occupancy 4526500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 36361000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20559250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 30df36f38..bc1d643b6 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.085008 # Number of seconds simulated -sim_ticks 85008313500 # Number of ticks simulated -final_tick 85008313500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.085027 # Number of seconds simulated +sim_ticks 85027009000 # Number of ticks simulated +final_tick 85027009000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 130085 # Simulator instruction rate (inst/s) -host_op_rate 137131 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64179279 # Simulator tick rate (ticks/s) -host_mem_usage 313784 # Number of bytes of host memory used -host_seconds 1324.54 # Real time elapsed on the host +host_inst_rate 134467 # Simulator instruction rate (inst/s) +host_op_rate 141751 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66356016 # Simulator tick rate (ticks/s) +host_mem_usage 312828 # Number of bytes of host memory used +host_seconds 1281.38 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 181635953 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 127168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 48000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 71360 # Number of bytes read from this memory -system.physmem.bytes_read::total 246528 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 127168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 127168 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 1987 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 750 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 1115 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3852 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1495948 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 564651 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 839447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2900046 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1495948 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1495948 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1495948 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 564651 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 839447 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2900046 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3852 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 127040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 47680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 71040 # Number of bytes read from this memory +system.physmem.bytes_read::total 245760 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 127040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 127040 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 1985 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 745 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 1110 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3840 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1494113 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 560763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 835499 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2890376 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1494113 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1494113 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1494113 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 560763 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 835499 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2890376 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3840 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 3852 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 3840 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 246528 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 245760 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 246528 # Total read bytes from the system interface side +system.physmem.bytesReadSys 245760 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 309 # Per bank write bursts -system.physmem.perBankRdBursts::1 223 # Per bank write bursts +system.physmem.perBankRdBursts::1 220 # Per bank write bursts system.physmem.perBankRdBursts::2 142 # Per bank write bursts -system.physmem.perBankRdBursts::3 310 # Per bank write bursts +system.physmem.perBankRdBursts::3 304 # Per bank write bursts system.physmem.perBankRdBursts::4 300 # Per bank write bursts system.physmem.perBankRdBursts::5 302 # Per bank write bursts system.physmem.perBankRdBursts::6 262 # Per bank write bursts system.physmem.perBankRdBursts::7 237 # Per bank write bursts system.physmem.perBankRdBursts::8 252 # Per bank write bursts -system.physmem.perBankRdBursts::9 218 # Per bank write bursts -system.physmem.perBankRdBursts::10 293 # Per bank write bursts +system.physmem.perBankRdBursts::9 219 # Per bank write bursts +system.physmem.perBankRdBursts::10 292 # Per bank write bursts system.physmem.perBankRdBursts::11 194 # Per bank write bursts -system.physmem.perBankRdBursts::12 193 # Per bank write bursts -system.physmem.perBankRdBursts::13 212 # Per bank write bursts +system.physmem.perBankRdBursts::12 191 # Per bank write bursts +system.physmem.perBankRdBursts::13 211 # Per bank write bursts system.physmem.perBankRdBursts::14 211 # Per bank write bursts system.physmem.perBankRdBursts::15 194 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 85008170000 # Total gap between requests +system.physmem.totGap 85026865500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 3852 # Read request sizes (log2) +system.physmem.readPktSize::6 3840 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,17 +94,17 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2522 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 895 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 165 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 83 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2543 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 851 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 162 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 86 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see @@ -190,79 +190,79 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 760 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 321.936842 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 203.366462 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 304.047629 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 237 31.18% 31.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 182 23.95% 55.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 69 9.08% 64.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 96 12.63% 76.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 35 4.61% 81.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 45 5.92% 87.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 18 2.37% 89.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 14 1.84% 91.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 64 8.42% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 760 # Bytes accessed per row activation -system.physmem.totQLat 36289181 # Total ticks spent queuing -system.physmem.totMemAccLat 108514181 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 19260000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9420.87 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 767 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 319.332464 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 200.822648 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 307.559029 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 236 30.77% 30.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 188 24.51% 55.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 81 10.56% 65.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 90 11.73% 77.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 32 4.17% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 41 5.35% 87.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 12 1.56% 88.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 16 2.09% 90.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 71 9.26% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 767 # Bytes accessed per row activation +system.physmem.totQLat 42919435 # Total ticks spent queuing +system.physmem.totMemAccLat 114919435 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 19200000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11176.94 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28170.87 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29926.94 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.89 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.90 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.89 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 3.02 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 3085 # Number of row buffer hits during reads +system.physmem.readRowHits 3071 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.09 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.97 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 22068579.96 # Average gap between requests -system.physmem.pageHitRate 80.09 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2721600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1485000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 16239600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 22142412.89 # Average gap between requests +system.physmem.pageHitRate 79.97 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2691360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1468500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16192800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5551949520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2339255205 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 48949672500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 56861323425 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.935094 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 81434793722 # Time in different power states -system.physmem_0.memoryStateTime::REF 2838420000 # Time in different power states +system.physmem_0.refreshEnergy 5553475200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2327866605 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 48973677750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 56875372215 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.916551 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 81470624236 # Time in different power states +system.physmem_0.memoryStateTime::REF 2839200000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 733662278 # Time in different power states +system.physmem_0.memoryStateTime::ACT 716299514 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3001320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1637625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 13540800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3107160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1695375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13657800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5551949520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2301878880 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 48982450500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 56854458645 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.854443 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 81486384408 # Time in different power states -system.physmem_1.memoryStateTime::REF 2838420000 # Time in different power states +system.physmem_1.refreshEnergy 5553475200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2285718525 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 49010649750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 56868303810 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.833418 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 81532427147 # Time in different power states +system.physmem_1.memoryStateTime::REF 2839200000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 678791592 # Time in different power states +system.physmem_1.memoryStateTime::ACT 654496603 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 85929478 # Number of BP lookups -system.cpu.branchPred.condPredicted 68409655 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6016514 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 40103730 # Number of BTB lookups -system.cpu.branchPred.BTBHits 39019729 # Number of BTB hits +system.cpu.branchPred.lookups 85926168 # Number of BP lookups +system.cpu.branchPred.condPredicted 68405800 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6016539 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 40105937 # Number of BTB lookups +system.cpu.branchPred.BTBHits 39014203 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.297007 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3701200 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 81899 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.277874 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3700977 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 81896 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -381,96 +381,96 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 170016628 # number of cpu cycles simulated +system.cpu.numCycles 170054019 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5612512 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 349284796 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85929478 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42720929 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 158258026 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 12046973 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1522 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 5612946 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 349281739 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85926168 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42715180 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 158272644 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 12047045 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1757 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 2068 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 78953849 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 17938 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 169897637 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.150791 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.046975 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 2232 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 78951619 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 17953 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 169913124 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.150597 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.047113 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 17345965 10.21% 10.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30201314 17.78% 27.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31838054 18.74% 46.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 90512304 53.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 17360928 10.22% 10.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30199989 17.77% 27.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31841897 18.74% 46.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 90510310 53.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 169897637 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.505418 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.054416 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17565023 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 17095500 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 122663721 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6724834 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5848559 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11136257 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 190151 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 306621954 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27645544 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5848559 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37752791 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8406678 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 578098 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 108929543 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8381968 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 278665579 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13416120 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3045260 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 842372 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2187359 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 31268 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 80203 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 483123422 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1196973277 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 297590130 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3005585 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 169913124 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.505287 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.053946 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17565564 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 17109843 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 122664763 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6724358 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5848596 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11135936 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 189930 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 306620744 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27649027 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5848596 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37751386 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8466295 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 579465 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 108929053 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8338329 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 278664885 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13415182 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3050613 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 842331 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2187361 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 37352 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 26454 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 483122463 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1196977553 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 297589838 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3006277 # Number of floating rename lookups system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 190146493 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 23524 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23418 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13341047 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 34139788 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14476953 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2546690 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1793951 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 264825375 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 45850 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 214906973 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5192109 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 82644277 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 219958197 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 634 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 169897637 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.264920 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.017502 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 190145534 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 23528 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23432 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13338171 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 34140942 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14477069 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2549253 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1790153 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 264824262 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 45858 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 214907174 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5191222 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 82643318 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 219950944 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 642 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 169913124 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.264806 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.017451 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52826553 31.09% 31.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 36096362 21.25% 52.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 65782146 38.72% 91.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 13572889 7.99% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1571303 0.92% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 47864 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 520 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52840350 31.10% 31.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 36091754 21.24% 52.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 65793999 38.72% 91.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13568282 7.99% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1571301 0.92% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 47256 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 182 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 169897637 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 169913124 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35601312 66.11% 66.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 152935 0.28% 66.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35600908 66.11% 66.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 152918 0.28% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.39% # attempts to use FU when none available @@ -489,22 +489,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.39% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 1069 0.00% 66.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 1064 0.00% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 35738 0.07% 66.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 318 0.00% 66.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 35736 0.07% 66.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 241 0.00% 66.46% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 812 0.00% 66.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 34382 0.06% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 216 0.00% 66.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 1033 0.00% 66.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 34370 0.06% 66.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 14078938 26.14% 92.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3947834 7.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 14078817 26.14% 92.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3947857 7.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 167350726 77.87% 77.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 918985 0.43% 78.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 167349433 77.87% 77.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 918954 0.43% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.30% # Type of FU issued @@ -523,93 +523,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.30% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33019 0.02% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33017 0.02% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 165190 0.08% 78.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 245718 0.11% 78.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 165198 0.08% 78.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 245711 0.11% 78.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 460475 0.21% 78.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 460497 0.21% 78.75% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 206696 0.10% 78.85% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 32004909 14.89% 93.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13373295 6.22% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 32005154 14.89% 93.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13374554 6.22% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 214906973 # Type of FU issued -system.cpu.iq.rate 1.264035 # Inst issue rate -system.cpu.iq.fu_busy_cnt 53853755 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.250591 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 654805304 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 345511813 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 204602678 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3952143 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2010627 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1806422 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266627552 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2133176 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1600193 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 214907174 # Type of FU issued +system.cpu.iq.rate 1.263758 # Inst issue rate +system.cpu.iq.fu_busy_cnt 53853149 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.250588 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 654819591 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 345508564 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 204603377 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3952252 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2011834 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1806382 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266627232 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2133091 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1600790 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6243644 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7556 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7106 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1832319 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6244798 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7531 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7120 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1832435 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 25875 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 661 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 25844 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 768 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5848559 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5681569 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 36478 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 264887188 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 5848596 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5681557 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 36821 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 264886087 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 34139788 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14476953 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23442 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3814 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 29479 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7106 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3233640 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3247282 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6480922 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 207527385 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 30721175 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7379588 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 34140942 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14477069 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23450 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3913 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 29719 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 7120 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3233413 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3247375 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6480788 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 207526427 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 30720305 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7380747 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 15963 # number of nop insts executed -system.cpu.iew.exec_refs 43860513 # number of memory reference insts executed -system.cpu.iew.exec_branches 44937173 # Number of branches executed -system.cpu.iew.exec_stores 13139338 # Number of stores executed -system.cpu.iew.exec_rate 1.220630 # Inst execution rate -system.cpu.iew.wb_sent 206744227 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 206409100 # cumulative count of insts written-back -system.cpu.iew.wb_producers 129466460 # num instructions producing a value -system.cpu.iew.wb_consumers 221676348 # num instructions consuming a value +system.cpu.iew.exec_nop 15967 # number of nop insts executed +system.cpu.iew.exec_refs 43860812 # number of memory reference insts executed +system.cpu.iew.exec_branches 44937004 # Number of branches executed +system.cpu.iew.exec_stores 13140507 # Number of stores executed +system.cpu.iew.exec_rate 1.220356 # Inst execution rate +system.cpu.iew.wb_sent 206744573 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 206409759 # cumulative count of insts written-back +system.cpu.iew.wb_producers 129475490 # num instructions producing a value +system.cpu.iew.wb_consumers 221697589 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.214052 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.584034 # average fanout of values written-back +system.cpu.iew.wb_rate 1.213789 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.584018 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 69543087 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 69541306 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5841587 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158455572 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.146380 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.646562 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5841613 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158471260 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.146267 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.646384 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 73674398 46.50% 46.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 41276379 26.05% 72.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 22551197 14.23% 86.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9630660 6.08% 92.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3550983 2.24% 95.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2150131 1.36% 96.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1280461 0.81% 97.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 988669 0.62% 97.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3352694 2.12% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 73683520 46.50% 46.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 41279039 26.05% 72.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 22557642 14.23% 86.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9629639 6.08% 92.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3553008 2.24% 95.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2147976 1.36% 96.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1280790 0.81% 97.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 986719 0.62% 97.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3352927 2.12% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158455572 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 158471260 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317409 # Number of instructions committed system.cpu.commit.committedOps 181650341 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -655,186 +655,186 @@ system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 181650341 # Class of committed instruction -system.cpu.commit.bw_lim_events 3352694 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 3352927 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 406291105 # The number of ROB reads -system.cpu.rob.rob_writes 513842853 # The number of ROB writes -system.cpu.timesIdled 3394 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 118991 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 406304779 # The number of ROB reads +system.cpu.rob.rob_writes 513839131 # The number of ROB writes +system.cpu.timesIdled 3408 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 140895 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303021 # Number of Instructions Simulated system.cpu.committedOps 181635953 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.986730 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.986730 # CPI: Total CPI of All Threads -system.cpu.ipc 1.013448 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.013448 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 218960053 # number of integer regfile reads -system.cpu.int_regfile_writes 114514072 # number of integer regfile writes -system.cpu.fp_regfile_reads 2904445 # number of floating regfile reads -system.cpu.fp_regfile_writes 2441481 # number of floating regfile writes -system.cpu.cc_regfile_reads 709585079 # number of cc regfile reads -system.cpu.cc_regfile_writes 229544416 # number of cc regfile writes -system.cpu.misc_regfile_reads 59313443 # number of misc regfile reads +system.cpu.cpi 0.986947 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.986947 # CPI: Total CPI of All Threads +system.cpu.ipc 1.013225 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.013225 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 218958782 # number of integer regfile reads +system.cpu.int_regfile_writes 114515411 # number of integer regfile writes +system.cpu.fp_regfile_reads 2904346 # number of floating regfile reads +system.cpu.fp_regfile_writes 2441525 # number of floating regfile writes +system.cpu.cc_regfile_reads 709584302 # number of cc regfile reads +system.cpu.cc_regfile_writes 229541480 # number of cc regfile writes +system.cpu.misc_regfile_reads 59315386 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.dcache.tags.replacements 72897 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.439547 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 41117509 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 73409 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 560.115367 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 497141250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.439547 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998905 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998905 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 72889 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.417696 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 41115745 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 73401 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 560.152382 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 506067250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.417696 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998863 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998863 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 222 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 165 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 226 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 42 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 82532283 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 82532283 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 28730746 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28730746 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12341850 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12341850 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 82529901 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 82529901 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28729389 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28729389 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12341441 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12341441 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 361 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 361 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22145 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22145 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22147 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22147 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41072596 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41072596 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41072957 # number of overall hits -system.cpu.dcache.overall_hits::total 41072957 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89111 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89111 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 22437 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 22437 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 118 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 118 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 262 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 262 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 111548 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 111548 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 111666 # number of overall misses -system.cpu.dcache.overall_misses::total 111666 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 835319240 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 835319240 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 222952999 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 222952999 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2325000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 2325000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1058272239 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1058272239 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1058272239 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1058272239 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28819857 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28819857 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 41070830 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41070830 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41071191 # number of overall hits +system.cpu.dcache.overall_hits::total 41071191 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89283 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89283 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 22846 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22846 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 116 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 116 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 260 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 260 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 112129 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 112129 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 112245 # number of overall misses +system.cpu.dcache.overall_misses::total 112245 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 853218237 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 853218237 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 244809935 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 244809935 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2319500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 2319500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1098028172 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1098028172 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1098028172 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1098028172 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28818672 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28818672 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 479 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 479 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 477 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 477 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41184144 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41184144 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41184623 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41184623 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003092 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003092 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001815 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001815 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.246347 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.246347 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011693 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011693 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002709 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002709 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002711 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002711 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9373.918371 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9373.918371 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9936.845345 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9936.845345 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8874.045802 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8874.045802 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9487.146690 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9487.146690 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9477.121407 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9477.121407 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 122 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7730 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 41182959 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41182959 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41183436 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41183436 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003098 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003098 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001848 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001848 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.243187 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.243187 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011604 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011604 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002723 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002723 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002725 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002725 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9556.334767 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9556.334767 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10715.658540 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10715.658540 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8921.153846 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8921.153846 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9792.544052 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9792.544052 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9782.423912 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9782.423912 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 167 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 10490 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 532 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 61 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 14.530075 # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_targets 844 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 12.428910 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 64874 # number of writebacks -system.cpu.dcache.writebacks::total 64874 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24383 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 24383 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 13871 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 13871 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 262 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 262 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 38254 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 38254 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 38254 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 38254 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64728 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64728 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8566 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 8566 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 115 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 115 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 73294 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 73294 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 73409 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 73409 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 491417758 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 491417758 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 74043249 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 74043249 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 982500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 982500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 565461007 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 565461007 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 566443507 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 566443507 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 64871 # number of writebacks +system.cpu.dcache.writebacks::total 64871 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24560 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 24560 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14281 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 14281 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 260 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 260 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 38841 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 38841 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 38841 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 38841 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64723 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 64723 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8565 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 8565 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 113 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 113 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 73288 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 73288 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 73401 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 73401 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 526941010 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 526941010 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 81775757 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 81775757 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 905500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 905500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 608716767 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 608716767 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 609622267 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 609622267 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002246 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002246 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000693 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000693 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.240084 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.240084 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.236897 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.236897 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001780 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.001780 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001782 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001782 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7592.042980 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7592.042980 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8643.853491 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8643.853491 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8543.478261 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8543.478261 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7714.969943 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 7714.969943 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7716.267855 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 7716.267855 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8141.479999 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8141.479999 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9547.665733 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9547.665733 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8013.274336 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8013.274336 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8305.817692 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8305.817692 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8305.367325 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8305.367325 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 54440 # number of replacements -system.cpu.icache.tags.tagsinuse 510.617911 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 78896507 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 54952 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1435.734951 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 84258685250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.617911 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997301 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997301 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 54441 # number of replacements +system.cpu.icache.tags.tagsinuse 510.602621 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78893897 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 54953 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1435.661329 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 84271974250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.602621 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997271 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997271 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id @@ -842,188 +842,188 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 272 system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 48 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 157962600 # Number of tag accesses -system.cpu.icache.tags.data_accesses 157962600 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 78896507 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78896507 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78896507 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78896507 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78896507 # number of overall hits -system.cpu.icache.overall_hits::total 78896507 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 57317 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 57317 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 57317 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 57317 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 57317 # number of overall misses -system.cpu.icache.overall_misses::total 57317 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 586515679 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 586515679 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 586515679 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 586515679 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 586515679 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 586515679 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78953824 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78953824 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78953824 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78953824 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78953824 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78953824 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000726 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000726 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000726 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000726 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000726 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000726 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10232.839803 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 10232.839803 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 10232.839803 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 10232.839803 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 10232.839803 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 10232.839803 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 47827 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 10 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2525 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 18.941386 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 10 # average number of cycles each access was blocked +system.cpu.icache.tags.tag_accesses 157958145 # Number of tag accesses +system.cpu.icache.tags.data_accesses 157958145 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 78893897 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 78893897 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 78893897 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 78893897 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 78893897 # number of overall hits +system.cpu.icache.overall_hits::total 78893897 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 57699 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 57699 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 57699 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 57699 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 57699 # number of overall misses +system.cpu.icache.overall_misses::total 57699 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 607673936 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 607673936 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 607673936 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 607673936 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 607673936 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 607673936 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 78951596 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 78951596 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 78951596 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 78951596 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 78951596 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 78951596 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000731 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000731 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000731 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000731 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000731 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000731 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10531.793203 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 10531.793203 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 10531.793203 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 10531.793203 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 10531.793203 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10531.793203 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 55459 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 532 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2752 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 20.152253 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 177.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2365 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2365 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2365 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2365 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2365 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2365 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54952 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 54952 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 54952 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 54952 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 54952 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 54952 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 466993997 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 466993997 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 466993997 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 466993997 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 466993997 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 466993997 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2746 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2746 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2746 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2746 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2746 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2746 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54953 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 54953 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 54953 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 54953 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 54953 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 54953 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 509320483 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 509320483 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 509320483 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 509320483 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 509320483 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 509320483 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000696 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000696 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000696 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000696 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000696 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000696 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8498.216571 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8498.216571 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8498.216571 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 8498.216571 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8498.216571 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 8498.216571 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9268.292595 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 9268.292595 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9268.292595 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 9268.292595 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9268.292595 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 9268.292595 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 9345 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 9345 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 9289 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 9289 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 1367 # number of prefetches not generated due to page crossing +system.cpu.l2cache.prefetcher.pfSpanPage 1375 # number of prefetches not generated due to page crossing system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2661.020186 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 178437 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3588 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 49.731605 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2667.127708 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 178431 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3576 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 49.896812 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 702.071269 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1377.111854 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 421.096641 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 160.740422 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.042851 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084052 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.025702 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.009811 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.162416 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 262 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3326 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 701.951887 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1376.042782 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 417.094048 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 172.038991 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.042844 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.083987 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.025457 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.010500 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.162789 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 260 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3316 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 19 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 86 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 157 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 749 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 83 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 158 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 751 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 37 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2295 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.015991 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.203003 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3103985 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3103985 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 52960 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 64249 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 117209 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 64874 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 64874 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 8402 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 8402 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 52960 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 72651 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 125611 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 52960 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 72651 # number of overall hits -system.cpu.l2cache.overall_hits::total 125611 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1992 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 523 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 2515 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 235 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 235 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1992 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 758 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2750 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1992 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 758 # number of overall misses -system.cpu.l2cache.overall_misses::total 2750 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 121584000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 34631250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 156215250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15317000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 15317000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 121584000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 49948250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 171532250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 121584000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 49948250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 171532250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 54952 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 64772 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 119724 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 64874 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 64874 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 8637 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 8637 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 54952 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 73409 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 128361 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 54952 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 73409 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 128361 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.036250 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.008074 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.021007 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.027209 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.027209 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.036250 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.010326 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.021424 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.036250 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.010326 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.021424 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 61036.144578 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 66216.539197 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 62113.419483 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65178.723404 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65178.723404 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 61036.144578 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65894.788918 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 62375.363636 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 61036.144578 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65894.788918 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 62375.363636 # average overall miss latency +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2290 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.015869 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.202393 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3103812 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3103812 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 52962 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 64250 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 117212 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 64871 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 64871 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 8396 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 8396 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 52962 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 72646 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 125608 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 52962 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 72646 # number of overall hits +system.cpu.l2cache.overall_hits::total 125608 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1991 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 515 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 2506 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 240 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 240 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1991 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 755 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2746 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1991 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 755 # number of overall misses +system.cpu.l2cache.overall_misses::total 2746 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 137421241 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 37855250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 175276491 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 18932508 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 18932508 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 137421241 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 56787758 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 194208999 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 137421241 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 56787758 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 194208999 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 54953 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 64765 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 119718 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 64871 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 64871 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 8636 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 8636 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 54953 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 73401 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 128354 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 54953 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 73401 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 128354 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.036231 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.007952 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.020933 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.027791 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.027791 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.036231 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.010286 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.021394 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.036231 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.010286 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.021394 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69021.215972 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73505.339806 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69942.733839 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78885.450000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78885.450000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69021.215972 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75215.573510 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70724.325929 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69021.215972 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75215.573510 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70724.325929 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1032,128 +1032,128 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 13 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 13 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 13 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1987 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 515 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2502 # number of ReadReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1816 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 1816 # number of HardPFReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 235 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 235 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1987 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 750 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2737 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1987 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 750 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1816 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 4553 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104199500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 29901250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 134100750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 63393390 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 63393390 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13328500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13328500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104199500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 43229750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 147429250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104199500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 43229750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 63393390 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 210822640 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.036159 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.007951 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.020898 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 2 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 2 # number of ReadExReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 6 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 6 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1985 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 507 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2492 # number of ReadReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1808 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 1808 # number of HardPFReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 238 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 238 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1985 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 745 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2730 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1985 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 745 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1808 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4538 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 120193759 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33127750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 153321509 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 68601184 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 68601184 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16505250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16505250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 120193759 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 49633000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 169826759 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 120193759 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 49633000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 68601184 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 238427943 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.036122 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.007828 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.020816 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027209 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027209 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.036159 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.010217 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.021323 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.036159 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.010217 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027559 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027559 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.036122 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.010150 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.021269 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.036122 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.010150 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.035470 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52440.613991 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58060.679612 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53597.422062 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34908.254405 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 34908.254405 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56717.021277 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56717.021277 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52440.613991 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57639.666667 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53865.272196 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52440.613991 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57639.666667 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34908.254405 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 46304.115967 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.035355 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60551.012091 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65340.729783 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61525.485152 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37943.132743 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 37943.132743 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69349.789916 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69349.789916 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60551.012091 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66621.476510 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62207.604029 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60551.012091 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66621.476510 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37943.132743 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52540.313574 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 119724 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 119724 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 64874 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 2213 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 8637 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 8637 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 109904 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 211692 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 321596 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3516928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8850112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 12367040 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2213 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 195448 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.011323 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.105804 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 119718 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 119718 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 64871 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 2155 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 8636 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 8636 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 109906 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 211673 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 321579 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3516992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8849408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 12366400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2155 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 195380 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.011030 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.104442 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 193235 98.87% 98.87% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 2213 1.13% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 193225 98.90% 98.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 2155 1.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 195448 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 161491500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 195380 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 161483500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 82814471 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 82836732 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 110208992 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 110205232 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadReq 3617 # Transaction distribution -system.membus.trans_dist::ReadResp 3617 # Transaction distribution -system.membus.trans_dist::ReadExReq 235 # Transaction distribution -system.membus.trans_dist::ReadExResp 235 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7704 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7704 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 246528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 246528 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 3602 # Transaction distribution +system.membus.trans_dist::ReadResp 3602 # Transaction distribution +system.membus.trans_dist::ReadExReq 238 # Transaction distribution +system.membus.trans_dist::ReadExResp 238 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7680 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7680 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 245760 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 245760 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3852 # Request fanout histogram +system.membus.snoop_fanout::samples 3840 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3852 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3840 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3852 # Request fanout histogram -system.membus.reqLayer0.occupancy 5007645 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3840 # Request fanout histogram +system.membus.reqLayer0.occupancy 4975502 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 36124927 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20238053 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index 7ececc2b6..e6a9622eb 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.099596 # Nu sim_ticks 99596491000 # Number of ticks simulated final_tick 99596491000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1699536 # Simulator instruction rate (inst/s) -host_op_rate 1791584 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 982302061 # Simulator tick rate (ticks/s) -host_mem_usage 304728 # Number of bytes of host memory used -host_seconds 101.39 # Real time elapsed on the host +host_inst_rate 1940320 # Simulator instruction rate (inst/s) +host_op_rate 2045410 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1121471108 # Simulator tick rate (ticks/s) +host_mem_usage 304628 # Number of bytes of host memory used +host_seconds 88.81 # Real time elapsed on the host sim_insts 172317409 # Number of instructions simulated sim_ops 181650341 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,18 +230,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 155786601 system.membus.pkt_size::total 915226805 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 230024466 # Request fanout histogram -system.membus.snoop_fanout::mean 4.825391 # Request fanout histogram +system.membus.snoop_fanout::mean 2.825391 # Request fanout histogram system.membus.snoop_fanout::stdev 0.379633 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 40164415 17.46% 17.46% # Request fanout histogram -system.membus.snoop_fanout::5 189860051 82.54% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 40164415 17.46% 17.46% # Request fanout histogram +system.membus.snoop_fanout::3 189860051 82.54% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::total 230024466 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index 62a10ca2c..6ce1a7f0e 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.230173 # Number of seconds simulated -sim_ticks 230173357000 # Number of ticks simulated -final_tick 230173357000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 230173357500 # Number of ticks simulated +final_tick 230173357500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1229194 # Simulator instruction rate (inst/s) -host_op_rate 1295881 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1646435898 # Simulator tick rate (ticks/s) -host_mem_usage 312932 # Number of bytes of host memory used -host_seconds 139.80 # Real time elapsed on the host +host_inst_rate 1098511 # Simulator instruction rate (inst/s) +host_op_rate 1158108 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1471393960 # Simulator tick rate (ticks/s) +host_mem_usage 313104 # Number of bytes of host memory used +host_seconds 156.43 # Real time elapsed on the host sim_insts 171842483 # Number of instructions simulated sim_ops 181165370 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 460346714 # number of cpu cycles simulated +system.cpu.numCycles 460346715 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 171842483 # Number of instructions committed @@ -168,7 +168,7 @@ system.cpu.num_mem_refs 40540779 # nu system.cpu.num_load_insts 27896144 # Number of load instructions system.cpu.num_store_insts 12644635 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 460346713.998000 # Number of busy cycles +system.cpu.num_busy_cycles 460346714.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 40300311 # Number of branches fetched @@ -208,12 +208,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 181650742 # Class of executed instruction system.cpu.dcache.tags.replacements 40 # number of replacements -system.cpu.dcache.tags.tagsinuse 1363.619284 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1363.619277 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619284 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619277 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.332915 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.332915 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id @@ -309,16 +309,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1788 system.cpu.dcache.demand_mshr_misses::total 1788 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34093000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 34093000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57994500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 57994500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92087500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 92087500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92140500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 92140500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34437000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 34437000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58544500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 58544500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92981500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 92981500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 93035000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 93035000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses @@ -329,24 +329,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000045 system.cpu.dcache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49553.779070 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49553.779070 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52722.272727 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52722.272727 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51503.076063 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51503.076063 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51503.912800 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51503.912800 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50053.779070 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50053.779070 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53222.272727 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53222.272727 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52003.076063 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52003.076063 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52003.912800 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52003.912800 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1506 # number of replacements -system.cpu.icache.tags.tagsinuse 1147.992604 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1147.992598 # Cycle average of tags in use system.cpu.icache.tags.total_refs 189857001 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 62227.794494 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1147.992604 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1147.992598 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.560543 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.560543 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1545 # Occupied blocks per task id @@ -370,12 +370,12 @@ system.cpu.icache.demand_misses::cpu.inst 3051 # n system.cpu.icache.demand_misses::total 3051 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 3051 # number of overall misses system.cpu.icache.overall_misses::total 3051 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 112370500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 112370500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 112370500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 112370500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 112370500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 112370500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 112371000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 112371000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 112371000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 112371000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 112371000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 112371000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 189860052 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 189860052 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 189860052 # number of demand (read+write) accesses @@ -388,12 +388,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36830.711242 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36830.711242 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36830.711242 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36830.711242 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36830.711242 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36830.711242 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36830.875123 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36830.875123 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36830.875123 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36830.875123 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36830.875123 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36830.875123 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -408,34 +408,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 3051 system.cpu.icache.demand_mshr_misses::total 3051 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3051 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3051 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 106268500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 106268500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 106268500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 106268500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 106268500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 106268500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 107794500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 107794500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 107794500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 107794500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 107794500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 107794500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34830.711242 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34830.711242 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34830.711242 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 34830.711242 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34830.711242 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 34830.711242 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35330.875123 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35330.875123 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35330.875123 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35330.875123 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35330.875123 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35330.875123 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 1675.663358 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 1675.663349 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1380 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.582524 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 3.037779 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.036759 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 503.588821 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.036753 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 503.588818 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy @@ -473,17 +473,17 @@ system.cpu.l2cache.demand_misses::total 3453 # nu system.cpu.l2cache.overall_misses::cpu.inst 1729 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1724 # number of overall misses system.cpu.l2cache.overall_misses::total 3453 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 89997500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32887000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 122884500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56814500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 56814500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 89997500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 89701500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 179699000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 89997500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 89701500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 179699000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 90862500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 33203000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 124065500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 57360500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 57360500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 90862500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 90563500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 181426000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 90862500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 90563500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 181426000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 3051 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 689 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 3740 # number of ReadReq accesses(hits+misses) @@ -508,17 +508,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.713430 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.566699 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.963667 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.713430 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52051.764025 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52036.392405 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52047.649301 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52027.930403 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52027.930403 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52051.764025 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52031.032483 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52041.413264 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52051.764025 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52031.032483 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52041.413264 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52552.053210 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52536.392405 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52547.861076 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52527.930403 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52527.930403 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52552.053210 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52531.032483 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52541.558065 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52552.053210 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52531.032483 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52541.558065 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -538,17 +538,17 @@ system.cpu.l2cache.demand_mshr_misses::total 3453 system.cpu.l2cache.overall_mshr_misses::cpu.inst 1729 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1724 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3453 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 69160000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 94440000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 43680000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 43680000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 69160000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 68960000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 138120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 69160000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 68960000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 138120000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70024500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25596000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 95620500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 44226000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 44226000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70024500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 69822000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 139846500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70024500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 69822000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 139846500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.917271 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.631283 # mshr miss rate for ReadReq accesses @@ -560,17 +560,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.713430 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.713430 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 3740 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution @@ -585,19 +585,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 310784 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 4856 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 4856 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 4856 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 4856 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 2444000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) @@ -624,9 +622,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 3453 # Request fanout histogram -system.membus.reqLayer0.occupancy 3596000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 3596500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 31220000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 17408500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index 66a194e38..e9f2af2a4 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.270563 # Number of seconds simulated -sim_ticks 270563082000 # Number of ticks simulated -final_tick 270563082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 270563082500 # Number of ticks simulated +final_tick 270563082500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1449498 # Simulator instruction rate (inst/s) -host_op_rate 1449499 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2027353723 # Simulator tick rate (ticks/s) -host_mem_usage 294428 # Number of bytes of host memory used -host_seconds 133.46 # Real time elapsed on the host +host_inst_rate 1283602 # Simulator instruction rate (inst/s) +host_op_rate 1283603 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1795321724 # Simulator tick rate (ticks/s) +host_mem_usage 297332 # Number of bytes of host memory used +host_seconds 150.70 # Real time elapsed on the host sim_insts 193444518 # Number of instructions simulated sim_ops 193444756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,32 +29,9 @@ system.physmem.bw_inst_read::total 850848 # In system.physmem.bw_total::cpu.inst 850848 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 372793 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1223641 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 4095 # Transaction distribution -system.membus.trans_dist::ReadResp 4095 # Transaction distribution -system.membus.trans_dist::ReadExReq 1078 # Transaction distribution -system.membus.trans_dist::ReadExResp 1078 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5173 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5173 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5173 # Request fanout histogram -system.membus.reqLayer0.occupancy 5173000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 46557000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 401 # Number of system calls -system.cpu.numCycles 541126164 # number of cpu cycles simulated +system.cpu.numCycles 541126165 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 193444518 # Number of instructions committed @@ -73,7 +50,7 @@ system.cpu.num_mem_refs 76733958 # nu system.cpu.num_load_insts 57735091 # Number of load instructions system.cpu.num_store_insts 18998867 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 541126163.998000 # Number of busy cycles +system.cpu.num_busy_cycles 541126164.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 15132745 # Number of branches fetched @@ -112,13 +89,142 @@ system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 193445773 # Class of executed instruction +system.cpu.dcache.tags.replacements 2 # number of replacements +system.cpu.dcache.tags.tagsinuse 1237.203936 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1237.203936 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.302052 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1237 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.384277 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 153469402 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 153469402 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 76709932 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 76709932 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 76709932 # number of overall hits +system.cpu.dcache.overall_hits::total 76709932 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 498 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 498 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1077 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1077 # number of WriteReq misses +system.cpu.dcache.SwapReq_misses::cpu.data 1 # number of SwapReq misses +system.cpu.dcache.SwapReq_misses::total 1 # number of SwapReq misses +system.cpu.dcache.demand_misses::cpu.data 1575 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses +system.cpu.dcache.overall_misses::total 1575 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 27390000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 27390000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 59235000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 59235000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 55000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 55000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 86625000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 86625000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 86625000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 86625000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 18976439 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 22406 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 22406 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 76711507 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 76711507 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 76711507 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 76711507 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000009 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000057 # miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000045 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_miss_rate::total 0.000045 # miss rate for SwapReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 55000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 55000 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 2 # number of writebacks +system.cpu.dcache.writebacks::total 2 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::cpu.data 1 # number of SwapReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::total 1 # number of SwapReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1575 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1575 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1575 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1575 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26643000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26643000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57619500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 57619500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 53500 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 53500 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 84262500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 84262500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 84262500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 84262500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000057 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000045 # mshr miss rate for SwapReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 53500 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 53500 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 10362 # number of replacements -system.cpu.icache.tags.tagsinuse 1591.579171 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1591.579164 # Cycle average of tags in use system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1591.579171 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1591.579164 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.777138 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.777138 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1926 # Occupied blocks per task id @@ -142,12 +248,12 @@ system.cpu.icache.demand_misses::cpu.inst 12288 # n system.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses system.cpu.icache.overall_misses::total 12288 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 310818000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 310818000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 310818000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 310818000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 310818000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 310818000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 310818500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 310818500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 310818500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 310818500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 310818500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 310818500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses @@ -160,12 +266,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 system.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25294.433594 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25294.433594 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25294.433594 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25294.433594 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25294.433594 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25294.433594 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25294.474284 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25294.474284 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25294.474284 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25294.474284 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25294.474284 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25294.474284 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -180,34 +286,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 12288 system.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 286242000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 286242000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 286242000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 286242000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 286242000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 286242000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 292386500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 292386500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 292386500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 292386500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 292386500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 292386500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000064 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23294.433594 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23294.433594 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23294.433594 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23294.433594 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23794.474284 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23794.474284 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23794.474284 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 23794.474284 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23794.474284 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 23794.474284 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2678.340865 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2678.340853 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 8691 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 2.121308 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 0.000453 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.282924 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 403.057488 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.282913 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 403.057487 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069436 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy @@ -240,17 +346,17 @@ system.cpu.l2cache.demand_misses::total 5173 # nu system.cpu.l2cache.overall_misses::cpu.inst 3597 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1576 # number of overall misses system.cpu.l2cache.overall_misses::total 5173 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 187044000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 25896000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 212940000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56056000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 56056000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 187044000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 81952000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 268996000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 187044000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 81952000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 268996000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 188843000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 26145000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 214988000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56595000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 56595000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 188843000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 82740000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 271583000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 188843000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 82740000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 271583000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 12288 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 498 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 12786 # number of ReadReq accesses(hits+misses) @@ -275,17 +381,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.373125 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.292725 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.373125 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.139005 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.122100 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.139005 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.096656 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.139005 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.096656 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -305,17 +411,17 @@ system.cpu.l2cache.demand_mshr_misses::total 5173 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3597 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1576 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5173 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 143880000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19920000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 163800000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 43120000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 43120000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 143880000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 63040000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 206920000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 143880000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 63040000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 206920000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 145678500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20169000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 165847500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 43659000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 43659000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 145678500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 63828000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 209506500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 145678500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 63828000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 209506500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.320272 # mshr miss rate for ReadReq accesses @@ -327,147 +433,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.373125 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2 # number of replacements -system.cpu.dcache.tags.tagsinuse 1237.203941 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1237.203941 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.302052 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1237 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.384277 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 153469402 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 153469402 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 76709932 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 76709932 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 76709932 # number of overall hits -system.cpu.dcache.overall_hits::total 76709932 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 498 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 498 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1077 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1077 # number of WriteReq misses -system.cpu.dcache.SwapReq_misses::cpu.data 1 # number of SwapReq misses -system.cpu.dcache.SwapReq_misses::total 1 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 1575 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses -system.cpu.dcache.overall_misses::total 1575 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 27390000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 27390000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 59235000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 59235000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 55000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 55000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 86625000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 86625000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 86625000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 86625000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 18976439 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 22406 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 22406 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 76711507 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 76711507 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 76711507 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 76711507 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000009 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000057 # miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000045 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_miss_rate::total 0.000045 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 55000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 55000 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2 # number of writebacks -system.cpu.dcache.writebacks::total 2 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::cpu.data 1 # number of SwapReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::total 1 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1575 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1575 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1575 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1575 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26394000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26394000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57081000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 57081000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 53000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 53000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 83475000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 83475000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 83475000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 83475000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000057 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000045 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 53000 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 53000 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 12786 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 2 # Transaction distribution @@ -497,5 +474,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 18432000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 4095 # Transaction distribution +system.membus.trans_dist::ReadResp 4095 # Transaction distribution +system.membus.trans_dist::ReadExReq 1078 # Transaction distribution +system.membus.trans_dist::ReadExResp 1078 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 5173 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 5173 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 5173 # Request fanout histogram +system.membus.reqLayer0.occupancy 5173500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 25865500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 85460c89a..e5c937252 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.148652 # Number of seconds simulated -sim_ticks 148652306000 # Number of ticks simulated -final_tick 148652306000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.148669 # Number of seconds simulated +sim_ticks 148668850500 # Number of ticks simulated +final_tick 148668850500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 83185 # Simulator instruction rate (inst/s) -host_op_rate 139426 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 93628996 # Simulator tick rate (ticks/s) -host_mem_usage 346568 # Number of bytes of host memory used -host_seconds 1587.67 # Real time elapsed on the host +host_inst_rate 82634 # Simulator instruction rate (inst/s) +host_op_rate 138502 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 93018548 # Simulator tick rate (ticks/s) +host_mem_usage 346916 # Number of bytes of host memory used +host_seconds 1598.27 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 224768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125696 # Number of bytes read from this memory -system.physmem.bytes_read::total 350464 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 224768 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 224768 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3512 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1964 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5476 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1512038 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 845570 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2357609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1512038 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1512038 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1512038 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 845570 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2357609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5476 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 225344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125504 # Number of bytes read from this memory +system.physmem.bytes_read::total 350848 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 225344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 225344 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3521 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1961 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5482 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1515745 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 844185 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2359929 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1515745 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1515745 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1515745 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 844185 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2359929 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5482 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5476 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5482 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 350464 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 350848 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 350464 # Total read bytes from the system interface side +system.physmem.bytesReadSys 350848 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 324 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 295 # Per bank write bursts -system.physmem.perBankRdBursts::1 363 # Per bank write bursts -system.physmem.perBankRdBursts::2 461 # Per bank write bursts -system.physmem.perBankRdBursts::3 370 # Per bank write bursts -system.physmem.perBankRdBursts::4 335 # Per bank write bursts -system.physmem.perBankRdBursts::5 334 # Per bank write bursts -system.physmem.perBankRdBursts::6 400 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 345 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 294 # Per bank write bursts +system.physmem.perBankRdBursts::1 364 # Per bank write bursts +system.physmem.perBankRdBursts::2 457 # Per bank write bursts +system.physmem.perBankRdBursts::3 371 # Per bank write bursts +system.physmem.perBankRdBursts::4 339 # Per bank write bursts +system.physmem.perBankRdBursts::5 333 # Per bank write bursts +system.physmem.perBankRdBursts::6 398 # Per bank write bursts system.physmem.perBankRdBursts::7 383 # Per bank write bursts -system.physmem.perBankRdBursts::8 340 # Per bank write bursts -system.physmem.perBankRdBursts::9 286 # Per bank write bursts -system.physmem.perBankRdBursts::10 236 # Per bank write bursts -system.physmem.perBankRdBursts::11 261 # Per bank write bursts -system.physmem.perBankRdBursts::12 219 # Per bank write bursts -system.physmem.perBankRdBursts::13 509 # Per bank write bursts -system.physmem.perBankRdBursts::14 392 # Per bank write bursts -system.physmem.perBankRdBursts::15 292 # Per bank write bursts +system.physmem.perBankRdBursts::8 344 # Per bank write bursts +system.physmem.perBankRdBursts::9 280 # Per bank write bursts +system.physmem.perBankRdBursts::10 239 # Per bank write bursts +system.physmem.perBankRdBursts::11 268 # Per bank write bursts +system.physmem.perBankRdBursts::12 225 # Per bank write bursts +system.physmem.perBankRdBursts::13 502 # Per bank write bursts +system.physmem.perBankRdBursts::14 395 # Per bank write bursts +system.physmem.perBankRdBursts::15 290 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 148652208500 # Total gap between requests +system.physmem.totGap 148668756000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5476 # Read request sizes (log2) +system.physmem.readPktSize::6 5482 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4366 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 909 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 176 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1147 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 304.265039 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 175.960981 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.625541 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 464 40.45% 40.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 245 21.36% 61.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 104 9.07% 70.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 57 4.97% 75.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 54 4.71% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 57 4.97% 85.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 24 2.09% 87.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 15 1.31% 88.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 127 11.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1147 # Bytes accessed per row activation -system.physmem.totQLat 37377750 # Total ticks spent queuing -system.physmem.totMemAccLat 140052750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 27380000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6825.74 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1140 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 306.470175 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.641766 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.557853 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 448 39.30% 39.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 255 22.37% 61.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 105 9.21% 70.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 70 6.14% 77.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 38 3.33% 80.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 59 5.18% 85.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 19 1.67% 87.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 18 1.58% 88.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 128 11.23% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1140 # Bytes accessed per row activation +system.physmem.totQLat 40930250 # Total ticks spent queuing +system.physmem.totMemAccLat 143717750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 27410000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7466.30 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25575.74 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26216.30 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.36 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.36 # Average system read bandwidth in MiByte/s @@ -214,286 +214,285 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4321 # Number of row buffer hits during reads +system.physmem.readRowHits 4334 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.91 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.06 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 27146130.11 # Average gap between requests -system.physmem.pageHitRate 78.91 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5072760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2767875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 22791600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 27119437.43 # Average gap between requests +system.physmem.pageHitRate 79.06 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5027400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2743125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 22776000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 9708918960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4015280925 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 85666359000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 99421191120 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.838371 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 142511183750 # Time in different power states -system.physmem_0.memoryStateTime::REF 4963660000 # Time in different power states +system.physmem_0.refreshEnergy 9709936080 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4021675470 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 85670093250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 99432251325 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.842708 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 142518159000 # Time in different power states +system.physmem_0.memoryStateTime::REF 4964180000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1172773250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1181750000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3575880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1951125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 19585800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3568320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1947000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 19648200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 9708918960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3861811845 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 85800972750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 99396816360 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.674456 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 142739163750 # Time in different power states -system.physmem_1.memoryStateTime::REF 4963660000 # Time in different power states +system.physmem_1.refreshEnergy 9709936080 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3821631120 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 85845562500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 99402293220 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.641253 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 142814554750 # Time in different power states +system.physmem_1.memoryStateTime::REF 4964180000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 947728750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 888260750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 22375930 # Number of BP lookups -system.cpu.branchPred.condPredicted 22375930 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1550820 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 14142904 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13245564 # Number of BTB hits +system.cpu.branchPred.lookups 22385702 # Number of BP lookups +system.cpu.branchPred.condPredicted 22385702 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1554139 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 14132286 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13246709 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.655193 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1524021 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 21798 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.733661 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1526841 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 22095 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 297304620 # number of cpu cycles simulated +system.cpu.numCycles 297337717 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27866919 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 248846814 # Number of instructions fetch has processed -system.cpu.fetch.Branches 22375930 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 14769585 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 267364531 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3698749 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 56 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 4550 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 42690 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 27888104 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 249064218 # Number of instructions fetch has processed +system.cpu.fetch.Branches 22385702 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 14773550 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 267343346 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3703385 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 34 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 5713 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 48972 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 111 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 26638460 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 257102 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 297128244 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.381645 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.790124 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 83 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 26656558 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 259176 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 297137957 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.382061 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.790607 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 229068376 77.09% 77.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5099613 1.72% 78.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 4127262 1.39% 80.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4784384 1.61% 81.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4893969 1.65% 83.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5110538 1.72% 85.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5334476 1.80% 86.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3994023 1.34% 88.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 34715603 11.68% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 229077480 77.09% 77.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5080600 1.71% 78.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4128062 1.39% 80.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4791015 1.61% 81.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4884919 1.64% 83.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5103681 1.72% 85.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5337561 1.80% 86.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4007445 1.35% 88.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 34727194 11.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 297128244 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.075263 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.837010 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16329336 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 230975824 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 26113582 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 21860128 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1849374 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 359242894 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1849374 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 24118008 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 162656356 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 38273 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 38263619 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 70202614 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 350538626 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 41453 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 61947521 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7945702 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 153558 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 405817730 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 972424276 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 641996744 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4657501 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 297137957 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.075287 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.837648 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16350382 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 230944995 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 26142980 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 21847908 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1851692 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 359376016 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1851692 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 24144395 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 162574126 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 34810 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 38280834 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 70252100 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 350628030 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 42505 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 62013521 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7956456 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 170486 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 405834886 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 972854229 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 642281329 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4678301 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 146388280 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2397 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2322 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 128546417 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 89512895 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 32023027 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 63891013 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 21581901 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 341300793 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5145 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 266928835 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 76764 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 119543073 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 250225997 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3900 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 297128244 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.898362 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.364631 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 146405436 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2386 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2313 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 128573116 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89639956 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 32032649 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 63973866 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 21576036 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 341334735 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4899 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 266857181 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 74594 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 119571219 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 250511173 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3654 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 297137957 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.898092 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.364162 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 171384973 57.68% 57.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 54250707 18.26% 75.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 33605057 11.31% 87.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 19187938 6.46% 93.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10808168 3.64% 97.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4369052 1.47% 98.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2227260 0.75% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 898004 0.30% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 397085 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 171399069 57.68% 57.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 54278133 18.27% 75.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 33575860 11.30% 87.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19165859 6.45% 93.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10861721 3.66% 97.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4344660 1.46% 98.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2227090 0.75% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 887493 0.30% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 398072 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 297128244 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 297137957 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 240256 7.42% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2591676 80.04% 87.46% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 406020 12.54% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 235011 7.30% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2578157 80.11% 87.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 405217 12.59% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1211341 0.45% 0.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 167360520 62.70% 63.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 793230 0.30% 63.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7036198 2.64% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1213739 0.45% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 66512723 24.92% 91.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 22801084 8.54% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1211344 0.45% 0.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 167292419 62.69% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 790150 0.30% 63.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7035672 2.64% 66.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1215098 0.46% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 66512451 24.92% 91.46% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 22800047 8.54% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 266928835 # Type of FU issued -system.cpu.iq.rate 0.897829 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3237952 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012130 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 829304993 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 456859927 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 261005005 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4995637 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4315017 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2397122 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266441955 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2513491 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18899538 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 266857181 # Type of FU issued +system.cpu.iq.rate 0.897488 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3218385 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012060 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 829150425 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 456900250 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 260922611 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4994873 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4333463 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2397328 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266351243 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2512979 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18909810 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 32863308 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14004 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 331776 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11507310 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 32990369 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14136 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 328607 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11516932 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 52520 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 17 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 52167 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 10 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1849374 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 126083228 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5521965 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 341305938 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 113234 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 89512895 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 32023027 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2291 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2224383 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 364956 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 331776 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 682604 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 926974 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1609578 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 264820941 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 65644877 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2107894 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1851692 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 126137646 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5532810 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 341339634 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 112602 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 89639956 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 32032649 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2212 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2223479 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 382778 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 328607 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 684628 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 928175 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1612803 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 264737771 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 65643847 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2119410 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 88243318 # number of memory reference insts executed -system.cpu.iew.exec_branches 14594562 # Number of branches executed -system.cpu.iew.exec_stores 22598441 # Number of stores executed -system.cpu.iew.exec_rate 0.890739 # Inst execution rate -system.cpu.iew.wb_sent 264116022 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 263402127 # cumulative count of insts written-back -system.cpu.iew.wb_producers 208929627 # num instructions producing a value -system.cpu.iew.wb_consumers 376950815 # num instructions consuming a value +system.cpu.iew.exec_refs 88241442 # number of memory reference insts executed +system.cpu.iew.exec_branches 14589088 # Number of branches executed +system.cpu.iew.exec_stores 22597595 # Number of stores executed +system.cpu.iew.exec_rate 0.890361 # Inst execution rate +system.cpu.iew.wb_sent 264036391 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 263319939 # cumulative count of insts written-back +system.cpu.iew.wb_producers 208896510 # num instructions producing a value +system.cpu.iew.wb_consumers 376872402 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.885967 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.554262 # average fanout of values written-back +system.cpu.iew.wb_rate 0.885592 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.554290 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 119991036 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 120026923 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1555160 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 280815934 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.788286 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.594389 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1559493 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 280830334 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.788246 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.594394 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 180962849 64.44% 64.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57749972 20.57% 85.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14199777 5.06% 90.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11927311 4.25% 94.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4203723 1.50% 95.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2893126 1.03% 96.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 916943 0.33% 97.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1048119 0.37% 97.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6914114 2.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 180946233 64.43% 64.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57795535 20.58% 85.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14201408 5.06% 90.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11929876 4.25% 94.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4188274 1.49% 95.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2885386 1.03% 96.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 910038 0.32% 97.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1053521 0.38% 97.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6920063 2.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 280815934 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 280830334 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -539,336 +538,336 @@ system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction -system.cpu.commit.bw_lim_events 6914114 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6920063 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 615256240 # The number of ROB reads -system.cpu.rob.rob_writes 699066092 # The number of ROB writes -system.cpu.timesIdled 3079 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 176376 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 615300578 # The number of ROB reads +system.cpu.rob.rob_writes 699132843 # The number of ROB writes +system.cpu.timesIdled 3156 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 199760 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.251094 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.251094 # CPI: Total CPI of All Threads -system.cpu.ipc 0.444229 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.444229 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 456513966 # number of integer regfile reads -system.cpu.int_regfile_writes 239334814 # number of integer regfile writes -system.cpu.fp_regfile_reads 3274089 # number of floating regfile reads -system.cpu.fp_regfile_writes 2057271 # number of floating regfile writes -system.cpu.cc_regfile_reads 102998380 # number of cc regfile reads -system.cpu.cc_regfile_writes 60202762 # number of cc regfile writes -system.cpu.misc_regfile_reads 136901121 # number of misc regfile reads +system.cpu.cpi 2.251344 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.251344 # CPI: Total CPI of All Threads +system.cpu.ipc 0.444179 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.444179 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 456486870 # number of integer regfile reads +system.cpu.int_regfile_writes 239256029 # number of integer regfile writes +system.cpu.fp_regfile_reads 3277423 # number of floating regfile reads +system.cpu.fp_regfile_writes 2057707 # number of floating regfile writes +system.cpu.cc_regfile_reads 102994410 # number of cc regfile reads +system.cpu.cc_regfile_writes 60201710 # number of cc regfile writes +system.cpu.misc_regfile_reads 136869897 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.dcache.tags.replacements 52 # number of replacements -system.cpu.dcache.tags.tagsinuse 1443.647680 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 67095165 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2013 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33330.931446 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 51 # number of replacements +system.cpu.dcache.tags.tagsinuse 1444.566400 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 67084714 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2000 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33542.357000 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1443.647680 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.352453 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.352453 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1961 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 441 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1444.566400 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.352677 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.352677 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1949 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 432 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1405 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.478760 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 134197329 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 134197329 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 46580786 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 46580786 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513865 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513865 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 67094651 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 67094651 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 67094651 # number of overall hits -system.cpu.dcache.overall_hits::total 67094651 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1141 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1141 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1866 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1866 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3007 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3007 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3007 # number of overall misses -system.cpu.dcache.overall_misses::total 3007 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 64283437 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 64283437 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 116004574 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 116004574 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 180288011 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 180288011 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 180288011 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 180288011 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 46581927 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 46581927 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_task_id_percent::1024 0.475830 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 134176300 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 134176300 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 46570369 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 46570369 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513845 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513845 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 67084214 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 67084214 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 67084214 # number of overall hits +system.cpu.dcache.overall_hits::total 67084214 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1050 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1050 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1886 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1886 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2936 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2936 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2936 # number of overall misses +system.cpu.dcache.overall_misses::total 2936 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 66068903 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 66068903 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 130813345 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 130813345 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 196882248 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 196882248 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 196882248 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 196882248 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 46571419 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 46571419 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 67097658 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 67097658 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 67097658 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 67097658 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000091 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000091 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000045 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000045 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000045 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56339.559159 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56339.559159 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62167.510182 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62167.510182 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59956.106086 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59956.106086 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59956.106086 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59956.106086 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 248 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 50 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 67087150 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 67087150 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 67087150 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 67087150 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000092 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000092 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000044 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000044 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000044 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000044 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62922.764762 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62922.764762 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69360.204136 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69360.204136 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67057.986376 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67057.986376 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67057.986376 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67057.986376 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 241 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 39 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.600000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 50 # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.200000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 19.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 10 # number of writebacks system.cpu.dcache.writebacks::total 10 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 666 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 666 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 588 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 588 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 667 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 667 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 667 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 667 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1865 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1865 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2340 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2340 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2340 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2340 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33671000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33671000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 111589176 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 111589176 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 145260176 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 145260176 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 145260176 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 145260176 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 589 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 589 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 589 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 589 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 462 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 462 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1885 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1885 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2347 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2347 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2347 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2347 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36319250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36319250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 127241905 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 127241905 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 163561155 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 163561155 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 163561155 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 163561155 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000091 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000091 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000092 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000092 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000035 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000035 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70886.315789 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70886.315789 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59833.338338 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59833.338338 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62076.998291 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 62076.998291 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62076.998291 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 62076.998291 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78613.095238 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78613.095238 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67502.336870 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67502.336870 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69689.456753 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 69689.456753 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69689.456753 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 69689.456753 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 5851 # number of replacements -system.cpu.icache.tags.tagsinuse 1641.461746 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 26627917 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 7830 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3400.755683 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 5861 # number of replacements +system.cpu.icache.tags.tagsinuse 1662.434995 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 26645946 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 7838 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3399.584843 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1641.461746 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.801495 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.801495 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1979 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 813 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 142 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 767 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.966309 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 53285074 # Number of tag accesses -system.cpu.icache.tags.data_accesses 53285074 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 26627919 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 26627919 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 26627919 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 26627919 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 26627919 # number of overall hits -system.cpu.icache.overall_hits::total 26627919 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 10540 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 10540 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 10540 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 10540 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 10540 # number of overall misses -system.cpu.icache.overall_misses::total 10540 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 391405749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 391405749 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 391405749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 391405749 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 391405749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 391405749 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 26638459 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 26638459 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 26638459 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 26638459 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 26638459 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 26638459 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000396 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000396 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000396 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000396 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000396 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000396 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37135.270304 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 37135.270304 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 37135.270304 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 37135.270304 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 37135.270304 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 37135.270304 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1286 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1662.434995 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.811736 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.811736 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1977 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 756 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 135 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 777 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.965332 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 53321296 # Number of tag accesses +system.cpu.icache.tags.data_accesses 53321296 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 26645946 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 26645946 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 26645946 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 26645946 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 26645946 # number of overall hits +system.cpu.icache.overall_hits::total 26645946 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 10610 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 10610 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 10610 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 10610 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 10610 # number of overall misses +system.cpu.icache.overall_misses::total 10610 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 431026999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 431026999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 431026999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 431026999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 431026999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 431026999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 26656556 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 26656556 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 26656556 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 26656556 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 26656556 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 26656556 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000398 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000398 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000398 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000398 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000398 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000398 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40624.599340 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 40624.599340 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 40624.599340 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 40624.599340 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 40624.599340 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 40624.599340 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1664 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 27 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 49.461538 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 61.629630 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2383 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2383 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2383 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2383 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2383 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2383 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8157 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 8157 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 8157 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 8157 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 8157 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 8157 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 292444251 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 292444251 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 292444251 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 292444251 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 292444251 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 292444251 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000306 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000306 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000306 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000306 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000306 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000306 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35851.937109 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35851.937109 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35851.937109 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35851.937109 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35851.937109 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35851.937109 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2425 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2425 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2425 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2425 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2425 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2425 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8185 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 8185 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 8185 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 8185 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 8185 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 8185 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 323320999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 323320999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 323320999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 323320999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 323320999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 323320999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000307 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000307 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000307 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39501.649236 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39501.649236 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39501.649236 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 39501.649236 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39501.649236 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 39501.649236 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2637.518864 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4367 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3944 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.107252 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2641.798011 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4354 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3951 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.101999 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1.637738 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2323.101405 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 312.779722 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000050 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.070895 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.009545 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.080491 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3944 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 920 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2666 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.120361 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 86925 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 86925 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 4317 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 44 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 4361 # number of ReadReq hits +system.cpu.l2cache.tags.occ_blocks::writebacks 1.181969 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2328.091219 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 312.524822 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000036 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.071048 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.009538 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.080621 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3951 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 894 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 157 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2664 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.120575 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 87043 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 87043 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 4315 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 34 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 4349 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 10 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 10 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 2 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 2 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 5 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 5 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 4317 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 49 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 4366 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 4317 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 49 # number of overall hits -system.cpu.l2cache.overall_hits::total 4366 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3513 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 431 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 3944 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 324 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 324 # number of UpgradeReq misses +system.cpu.l2cache.demand_hits::cpu.inst 4315 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 39 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 4354 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 4315 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 39 # number of overall hits +system.cpu.l2cache.overall_hits::total 4354 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3522 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 428 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 3950 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 345 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 345 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 1533 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 1533 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3513 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1964 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 5477 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3513 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1964 # number of overall misses -system.cpu.l2cache.overall_misses::total 5477 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 240782500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32741000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 273523500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 102420500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 102420500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 240782500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 135161500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 375944000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 240782500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 135161500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 375944000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 7830 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 8305 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 3522 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1961 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 5483 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3522 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1961 # number of overall misses +system.cpu.l2cache.overall_misses::total 5483 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 269302250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35486250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 304788500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 114514250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 114514250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 269302250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 150000500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 419302750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 269302250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 150000500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 419302750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 7837 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 462 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 8299 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 10 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 10 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 327 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 327 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 347 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 347 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1538 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1538 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 7830 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2013 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9843 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 7830 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2013 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9843 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.448659 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.907368 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.474895 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990826 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990826 # miss rate for UpgradeReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 7837 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2000 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9837 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 7837 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2000 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9837 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.449407 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.926407 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.475961 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.994236 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.994236 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.996749 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.996749 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.448659 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.975658 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.556436 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.448659 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.975658 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.556436 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68540.421292 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75965.197216 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69351.800203 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66810.502283 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66810.502283 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68540.421292 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68819.501018 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68640.496622 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68540.421292 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68819.501018 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68640.496622 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.449407 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.980500 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.557385 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.449407 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.980500 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.557385 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76462.876207 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82911.799065 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 77161.645570 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74699.445532 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74699.445532 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76462.876207 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76491.840898 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76473.235455 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76462.876207 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76491.840898 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76473.235455 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -877,118 +876,118 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3513 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 431 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3944 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 324 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 324 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3522 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 428 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3950 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 345 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 345 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1533 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1533 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3513 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1964 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5477 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3513 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1964 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5477 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 196758000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27393000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 224151000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3240823 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3240823 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 83086000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 83086000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 196758000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 110479000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 307237000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 196758000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 110479000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 307237000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.448659 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.907368 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.474895 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990826 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990826 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3522 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1961 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5483 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3522 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1961 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5483 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 225343750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 30127250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 255471000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6111844 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6111844 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 95336750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 95336750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 225343750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 125464000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 350807750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 225343750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 125464000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 350807750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.449407 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.926407 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.475961 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.994236 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.994236 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996749 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996749 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.448659 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.975658 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.556436 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.448659 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.975658 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.556436 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56008.539710 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63556.844548 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56833.417850 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.540123 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.540123 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54198.303979 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54198.303979 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56008.539710 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56252.036660 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56095.855395 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56008.539710 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56252.036660 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56095.855395 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.449407 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980500 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.557385 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.449407 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980500 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.557385 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63981.757524 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70390.771028 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64676.202532 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17715.489855 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17715.489855 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62189.660796 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62189.660796 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63981.757524 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63979.602244 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63980.986686 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63981.757524 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63979.602244 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63980.986686 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 8632 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 8631 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 8647 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 8646 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 327 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 327 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 347 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 347 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1538 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1538 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15986 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4690 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 20676 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 501056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129472 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 630528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 327 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 10507 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16021 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4704 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 20725 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 501504 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 630144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 348 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 10542 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 10507 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 10542 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 10507 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5263999 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 10542 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5281499 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 12826749 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 12941000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3560824 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3566845 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 3943 # Transaction distribution -system.membus.trans_dist::ReadResp 3943 # Transaction distribution -system.membus.trans_dist::UpgradeReq 324 # Transaction distribution -system.membus.trans_dist::UpgradeResp 324 # Transaction distribution +system.membus.trans_dist::ReadReq 3949 # Transaction distribution +system.membus.trans_dist::ReadResp 3949 # Transaction distribution +system.membus.trans_dist::UpgradeReq 345 # Transaction distribution +system.membus.trans_dist::UpgradeResp 345 # Transaction distribution system.membus.trans_dist::ReadExReq 1533 # Transaction distribution system.membus.trans_dist::ReadExResp 1533 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11600 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11600 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11600 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 350464 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 350464 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 350464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11654 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11654 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11654 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 350848 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 350848 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 350848 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5800 # Request fanout histogram +system.membus.snoop_fanout::samples 5827 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5800 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5827 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5800 # Request fanout histogram -system.membus.reqLayer0.occupancy 7074000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5827 # Request fanout histogram +system.membus.reqLayer0.occupancy 7212001 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 51890176 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 29752405 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index d20d50993..0e62e6e73 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.250954 # Number of seconds simulated -sim_ticks 250953957000 # Number of ticks simulated -final_tick 250953957000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 250953957500 # Number of ticks simulated +final_tick 250953957500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 881800 # Simulator instruction rate (inst/s) -host_op_rate 1477977 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1675544377 # Simulator tick rate (ticks/s) -host_mem_usage 333860 # Number of bytes of host memory used -host_seconds 149.77 # Real time elapsed on the host +host_inst_rate 722726 # Simulator instruction rate (inst/s) +host_op_rate 1211354 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1373280924 # Simulator tick rate (ticks/s) +host_mem_usage 338728 # Number of bytes of host memory used +host_seconds 182.74 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221363385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,35 +29,10 @@ system.physmem.bw_inst_read::total 724276 # In system.physmem.bw_total::cpu.inst 724276 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 483276 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1207552 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 3160 # Transaction distribution -system.membus.trans_dist::ReadResp 3160 # Transaction distribution -system.membus.trans_dist::ReadExReq 1575 # Transaction distribution -system.membus.trans_dist::ReadExResp 1575 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 4735 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4735 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 4735 # Request fanout histogram -system.membus.reqLayer0.occupancy 4753500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 42633500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 501907914 # number of cpu cycles simulated +system.cpu.numCycles 501907915 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 132071193 # Number of instructions committed @@ -78,7 +53,7 @@ system.cpu.num_mem_refs 77165304 # nu system.cpu.num_load_insts 56649587 # Number of load instructions system.cpu.num_store_insts 20515717 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 501907913.998000 # Number of busy cycles +system.cpu.num_busy_cycles 501907914.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 12326938 # Number of branches fetched @@ -117,13 +92,122 @@ system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 221363385 # Class of executed instruction +system.cpu.dcache.tags.replacements 41 # number of replacements +system.cpu.dcache.tags.tagsinuse 1363.457564 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457564 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.332875 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 471 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.455078 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 154397377 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 154397377 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20514153 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 77195831 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 77195831 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 77195831 # number of overall hits +system.cpu.dcache.overall_hits::total 77195831 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1578 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1905 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses +system.cpu.dcache.overall_misses::total 1905 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 17692500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 17692500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 86664000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 86664000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 104356500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 104356500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 104356500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 104356500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 56682005 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 56682005 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 77197736 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 77197736 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 77197736 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 77197736 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000077 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54105.504587 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54105.504587 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54920.152091 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54920.152091 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54780.314961 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54780.314961 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 7 # number of writebacks +system.cpu.dcache.writebacks::total 7 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 327 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 327 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1578 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1578 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1905 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17202000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17202000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84297000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 84297000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 101499000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 101499000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 101499000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 101499000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000077 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52605.504587 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52605.504587 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53420.152091 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53420.152091 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53280.314961 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53280.314961 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53280.314961 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53280.314961 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2836 # number of replacements -system.cpu.icache.tags.tagsinuse 1455.296642 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1455.296636 # Cycle average of tags in use system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 36959.879207 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296642 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296636 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.710594 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id @@ -147,12 +231,12 @@ system.cpu.icache.demand_misses::cpu.inst 4694 # n system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses system.cpu.icache.overall_misses::total 4694 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 180319000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 180319000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 180319000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 180319000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 180319000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 180319000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 180319500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 180319500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 180319500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 180319500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 180319500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 180319500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 173494367 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 173494367 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 173494367 # number of demand (read+write) accesses @@ -165,12 +249,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 system.cpu.icache.demand_miss_rate::total 0.000027 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000027 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38414.784832 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 38414.784832 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 38414.784832 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 38414.784832 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 38414.784832 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 38414.784832 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38414.891351 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 38414.891351 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 38414.891351 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 38414.891351 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 38414.891351 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 38414.891351 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -185,34 +269,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4694 system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170931000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 170931000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170931000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 170931000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170931000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 170931000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 173278500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 173278500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 173278500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 173278500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 173278500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 173278500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36414.784832 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36414.784832 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36414.784832 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36414.784832 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.784832 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.784832 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36914.891351 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36914.891351 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36914.891351 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36914.891351 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36914.891351 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36914.891351 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2058.178686 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2058.178675 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1862 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.588496 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.978580 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 228.178362 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.978570 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 228.178361 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy @@ -250,17 +334,17 @@ system.cpu.l2cache.demand_misses::total 4735 # nu system.cpu.l2cache.overall_misses::cpu.inst 2840 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1895 # number of overall misses system.cpu.l2cache.overall_misses::total 4735 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 147697000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16641500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 164338500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 81900000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 81900000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 147697000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 98541500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 246238500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 147697000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 98541500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 246238500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 149117500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16801500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 165919000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 82687500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 82687500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 149117500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 99489000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 248606500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 149117500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 99489000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 248606500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 4694 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 327 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 5021 # number of ReadReq accesses(hits+misses) @@ -285,17 +369,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.717533 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.717533 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52005.985915 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52004.687500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52005.854430 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52005.985915 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.791557 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52003.907075 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52005.985915 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.791557 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52003.907075 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52506.161972 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52504.687500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52506.012658 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52506.161972 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.791557 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52504.012672 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52506.161972 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.791557 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52504.012672 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -315,17 +399,17 @@ system.cpu.l2cache.demand_mshr_misses::total 4735 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2840 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1895 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4735 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 113600000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12800000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 126400000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 113600000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 75800000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 189400000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 113600000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 75800000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 189400000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115020000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12960000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 127980000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63787500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63787500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115020000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 76747500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 191767500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115020000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 76747500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 191767500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.978593 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.629357 # mshr miss rate for ReadReq accesses @@ -337,127 +421,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.717533 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.717533 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 41 # number of replacements -system.cpu.dcache.tags.tagsinuse 1363.457571 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457571 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.332875 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 471 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.455078 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 154397377 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 154397377 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20514153 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 77195831 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 77195831 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 77195831 # number of overall hits -system.cpu.dcache.overall_hits::total 77195831 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1578 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1905 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses -system.cpu.dcache.overall_misses::total 1905 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 17692500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 17692500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 86664000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 86664000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 104356500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 104356500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 104356500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 104356500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 56682005 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 56682005 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 77197736 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 77197736 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 77197736 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 77197736 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000077 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54105.504587 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54105.504587 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54920.152091 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54920.152091 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54780.314961 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54780.314961 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 7 # number of writebacks -system.cpu.dcache.writebacks::total 7 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 327 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 327 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1578 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1578 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1905 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17038500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17038500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83508000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 83508000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 100546500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 100546500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 100546500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 100546500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000077 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52105.504587 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52105.504587 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52920.152091 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52920.152091 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 5021 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 7 # Transaction distribution @@ -489,5 +464,30 @@ system.cpu.toL2Bus.respLayer0.occupancy 7041000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 3160 # Transaction distribution +system.membus.trans_dist::ReadResp 3160 # Transaction distribution +system.membus.trans_dist::ReadExReq 1575 # Transaction distribution +system.membus.trans_dist::ReadExResp 1575 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 4735 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 4735 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 4735 # Request fanout histogram +system.membus.reqLayer0.occupancy 4754000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 23694000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |