diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-13 12:30:30 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-13 12:30:30 -0600 |
| commit | 0d46708dc20c438d29bd724fb7d4b54d4d2f318a (patch) | |
| tree | 337e1a7404c57817cd08106a0369542ea5c4ac30 /tests/long/se/70.twolf/ref | |
| parent | 9b05e96b9efdb9cdcc4e40ef9c96b1228df7a175 (diff) | |
| download | gem5-0d46708dc20c438d29bd724fb7d4b54d4d2f318a.tar.xz | |
bp: fix up stats for changes to branch predictor
Diffstat (limited to 'tests/long/se/70.twolf/ref')
8 files changed, 1786 insertions, 1767 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout index ddac6bec8..6032e061b 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:36:18 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:58:42 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing +Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sav +Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -21,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 41833966000 because target called exit() +122 123 124 Exiting @ tick 42005374000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 7525585e3..2e73aee88 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.041834 # Number of seconds simulated -sim_ticks 41833966000 # Number of ticks simulated -final_tick 41833966000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.042005 # Number of seconds simulated +sim_ticks 42005374000 # Number of ticks simulated +final_tick 42005374000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 151560 # Simulator instruction rate (inst/s) -host_op_rate 151560 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 68989742 # Simulator tick rate (ticks/s) +host_inst_rate 147839 # Simulator instruction rate (inst/s) +host_op_rate 147839 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67571644 # Simulator tick rate (ticks/s) host_mem_usage 213560 # Number of bytes of host memory used -host_seconds 606.38 # Real time elapsed on the host +host_seconds 621.64 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read 316032 # Number of bytes read from this memory @@ -17,9 +17,9 @@ system.physmem.bytes_written 0 # Nu system.physmem.num_reads 4938 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 7554436 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 4274421 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 7554436 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 7523609 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 4256979 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 7523609 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -36,10 +36,10 @@ system.cpu.dtb.data_hits 26498119 # DT system.cpu.dtb.data_misses 33 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 26498152 # DTB accesses -system.cpu.itb.fetch_hits 9991202 # ITB hits +system.cpu.itb.fetch_hits 10037351 # ITB hits system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 9991251 # ITB accesses +system.cpu.itb.fetch_accesses 10037400 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -53,16 +53,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 83667933 # number of cpu cycles simulated +system.cpu.numCycles 84010749 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 83292959 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 83632403 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 10907 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7700653 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 75967280 # Number of cycles cpu stages are processed. -system.cpu.activity 90.796172 # Percentage of cycles cpu is active +system.cpu.timesIdled 11097 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7735993 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 76274756 # Number of cycles cpu stages are processed. +system.cpu.activity 90.791663 # Percentage of cycles cpu is active system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed @@ -74,158 +74,158 @@ system.cpu.committedInsts 91903056 # Nu system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) -system.cpu.cpi 0.910393 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.914124 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 0.910393 # CPI: Total CPI of All Threads -system.cpu.ipc 1.098426 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.914124 # CPI: Total CPI of All Threads +system.cpu.ipc 1.093944 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 1.098426 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 13542330 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 9941405 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 4410938 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 8655858 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 4135478 # Number of BTB hits +system.cpu.ipc_total 1.093944 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 13563923 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 9779691 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 4496836 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 7950423 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 3848158 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target. -system.cpu.branch_predictor.RASInCorrect 132 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 47.776639 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 6269254 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 7273076 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 73609025 # Number of Reads from Int. Register File +system.cpu.branch_predictor.RASInCorrect 123 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 48.401928 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 5997418 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 7566505 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 73742077 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 136184497 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 2206079 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 136317549 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 2206798 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 8057967 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 38654467 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 26652325 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 3861647 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 548433 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4410080 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 5830622 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 43.064235 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 57347630 # Number of Instructions Executed. -system.cpu.mult_div_unit.multiplies 458254 # Number of Multipy Operations Executed +system.cpu.regfile_manager.floatRegFileAccesses 8058686 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 38530251 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 26765541 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 3521133 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 974845 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4495978 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 5744724 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 43.903025 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 57471384 # Number of Instructions Executed. +system.cpu.mult_div_unit.multiplies 458266 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 27446781 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 56221152 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 67.195579 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 34307675 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 49360258 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 58.995431 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33744588 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 49923345 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 59.668434 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65638077 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 18029856 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.549303 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 29755825 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 53912108 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.435807 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 7551 # number of replacements -system.cpu.icache.tagsinuse 1491.782957 # Cycle average of tags in use -system.cpu.icache.total_refs 9979713 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 9436 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1057.621132 # Average number of references to valid blocks. +system.cpu.stage0.idleCycles 27790213 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 56220536 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 66.920646 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 34560671 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 49450078 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 58.861608 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 34032650 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 49978099 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 59.490124 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65981194 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 18029555 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.461010 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 30068425 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 53942324 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.208836 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 8111 # number of replacements +system.cpu.icache.tagsinuse 1492.322334 # Cycle average of tags in use +system.cpu.icache.total_refs 10025618 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 9996 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1002.962985 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1491.782957 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.728410 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.728410 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 9979713 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 9979713 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 9979713 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 9979713 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 9979713 # number of overall hits -system.cpu.icache.overall_hits::total 9979713 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11486 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11486 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11486 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11486 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11486 # number of overall misses -system.cpu.icache.overall_misses::total 11486 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 291407500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 291407500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 291407500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 291407500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 291407500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 291407500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9991199 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9991199 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9991199 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9991199 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9991199 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9991199 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001150 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001150 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001150 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25370.668640 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25370.668640 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25370.668640 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1492.322334 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.728673 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.728673 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 10025618 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10025618 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10025618 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10025618 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10025618 # number of overall hits +system.cpu.icache.overall_hits::total 10025618 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11728 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11728 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11728 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11728 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11728 # number of overall misses +system.cpu.icache.overall_misses::total 11728 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 295393500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 295393500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 295393500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 295393500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 295393500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 295393500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 10037346 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 10037346 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 10037346 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 10037346 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 10037346 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 10037346 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001168 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001168 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001168 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25187.031037 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25187.031037 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25187.031037 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 69500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 97000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 17375 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 16166.666667 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2050 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2050 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2050 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2050 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2050 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2050 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9436 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 9436 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 9436 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 9436 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 9436 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 9436 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 222700000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 222700000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 222700000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 222700000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 222700000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 222700000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000944 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000944 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000944 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23601.102162 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23601.102162 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23601.102162 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1732 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1732 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1732 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1732 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1732 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1732 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9996 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 9996 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 9996 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 9996 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 9996 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 9996 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 228898000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 228898000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 228898000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 228898000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 228898000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 228898000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000996 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000996 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000996 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22898.959584 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22898.959584 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22898.959584 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1441.532122 # Cycle average of tags in use -system.cpu.dcache.total_refs 26491206 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1441.511431 # Cycle average of tags in use +system.cpu.dcache.total_refs 26491208 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11916.871795 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11916.872695 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1441.532122 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.351937 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.351937 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 19995645 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 19995645 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6495561 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6495561 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26491206 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26491206 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26491206 # number of overall hits -system.cpu.dcache.overall_hits::total 26491206 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 553 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 553 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5542 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5542 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 6095 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 6095 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 6095 # number of overall misses -system.cpu.dcache.overall_misses::total 6095 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 28393500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 28393500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 303801000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 303801000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 332194500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 332194500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 332194500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 332194500 # number of overall miss cycles +system.cpu.dcache.occ_blocks::cpu.data 1441.511431 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.351932 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.351932 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 19995646 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 19995646 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6495562 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6495562 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26491208 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26491208 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26491208 # number of overall hits +system.cpu.dcache.overall_hits::total 26491208 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 552 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 552 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5541 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5541 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 6093 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 6093 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 6093 # number of overall misses +system.cpu.dcache.overall_misses::total 6093 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 28391500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 28391500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 303790500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 303790500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 332182000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 332182000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 332182000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 332182000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -238,28 +238,28 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000852 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000230 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000230 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51344.484629 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54817.935763 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54502.789171 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54502.789171 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51433.876812 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54825.933947 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54518.627934 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54518.627934 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 41047000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 41043500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 824 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 823 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 49814.320388 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 49870.595383 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 107 # number of writebacks system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3794 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3794 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3872 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3872 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3872 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3872 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 77 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3793 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3793 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3870 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3870 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3870 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3870 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses @@ -268,49 +268,49 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23213000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23213000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92997500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 92997500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 116210500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 116210500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 116210500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 116210500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23216000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23216000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92995500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 92995500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 116211500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 116211500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 116211500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 116211500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48869.473684 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53202.231121 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52276.428250 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52276.428250 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48875.789474 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53201.086957 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52276.878093 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52276.878093 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2189.253602 # Cycle average of tags in use -system.cpu.l2cache.total_refs 6704 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2189.730470 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7264 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.042657 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.213285 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.838059 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1820.375269 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 351.040274 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000544 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.055553 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.010713 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.066811 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 6642 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::writebacks 17.847253 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1820.879596 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 351.003621 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.055569 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.010712 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.066825 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 7202 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6695 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 7255 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 6642 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 7202 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 6721 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 6642 # number of overall hits +system.cpu.l2cache.demand_hits::total 7281 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 7202 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits -system.cpu.l2cache.overall_hits::total 6721 # number of overall hits +system.cpu.l2cache.overall_hits::total 7281 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 2794 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 3216 # number of ReadReq misses @@ -322,44 +322,44 @@ system.cpu.l2cache.demand_misses::total 4938 # nu system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4938 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 146193000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22134500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 168327500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 90565000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 90565000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 146193000 # 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number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 146177000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 112705000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 258882000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 146177000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 112705000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 258882000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 9996 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 9911 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 10471 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 9436 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 9996 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 11659 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 9436 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 12219 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 9996 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 11659 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.296100 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 12219 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.279512 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.296100 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.279512 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.296100 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.279512 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52323.908375 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52451.421801 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52592.915215 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52323.908375 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52565.065299 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52323.908375 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52565.065299 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52318.181818 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52462.085308 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52593.495935 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52318.181818 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52567.630597 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52318.181818 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52567.630597 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -379,31 +379,31 @@ system.cpu.l2cache.demand_mshr_misses::total 4938 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 112072000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16981500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 129053500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69344000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69344000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 112072000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86325500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 198397500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 112072000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86325500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 198397500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.296100 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 112070000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16981000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 129051000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69345500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69345500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 112070000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86326500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 198396500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 112070000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86326500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 198396500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.279512 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.296100 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.279512 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.296100 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.279512 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40111.667860 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40240.521327 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40269.454123 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40111.667860 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40263.759328 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40111.667860 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40263.759328 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40110.952040 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40239.336493 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40270.325203 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40110.952040 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40264.225746 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40110.952040 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40264.225746 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout index f5b2c31fd..58e98acc5 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:45:24 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 18:07:15 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing +Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav +Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -21,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 29167093500 because target called exit() +122 123 124 Exiting @ tick 23638033500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 221154573..8502942e2 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.029167 # Number of seconds simulated -sim_ticks 29167093500 # Number of ticks simulated -final_tick 29167093500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023638 # Number of seconds simulated +sim_ticks 23638033500 # Number of ticks simulated +final_tick 23638033500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 198361 # Simulator instruction rate (inst/s) -host_op_rate 198361 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 68729352 # Simulator tick rate (ticks/s) +host_inst_rate 231314 # Simulator instruction rate (inst/s) +host_op_rate 231314 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64954124 # Simulator tick rate (ticks/s) host_mem_usage 214912 # Number of bytes of host memory used -host_seconds 424.38 # Real time elapsed on the host +host_seconds 363.92 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 332416 # Number of bytes read from this memory -system.physmem.bytes_inst_read 193856 # Number of instructions bytes read from this memory +system.physmem.bytes_read 336064 # Number of bytes read from this memory +system.physmem.bytes_inst_read 197952 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 5194 # Number of read requests responded to by this memory +system.physmem.num_reads 5251 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 11396953 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 6646394 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 11396953 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 14217088 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 8374301 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 14217088 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 25236325 # DTB read hits -system.cpu.dtb.read_misses 540509 # DTB read misses +system.cpu.dtb.read_hits 23223377 # DTB read hits +system.cpu.dtb.read_misses 198479 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 25776834 # DTB read accesses -system.cpu.dtb.write_hits 7362909 # DTB write hits -system.cpu.dtb.write_misses 1032 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 7363941 # DTB write accesses -system.cpu.dtb.data_hits 32599234 # DTB hits -system.cpu.dtb.data_misses 541541 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 33140775 # DTB accesses -system.cpu.itb.fetch_hits 18604047 # ITB hits -system.cpu.itb.fetch_misses 85 # ITB misses +system.cpu.dtb.read_accesses 23421856 # DTB read accesses +system.cpu.dtb.write_hits 7079825 # DTB write hits +system.cpu.dtb.write_misses 1403 # DTB write misses +system.cpu.dtb.write_acv 5 # DTB write access violations +system.cpu.dtb.write_accesses 7081228 # DTB write accesses +system.cpu.dtb.data_hits 30303202 # DTB hits +system.cpu.dtb.data_misses 199882 # DTB misses +system.cpu.dtb.data_acv 5 # DTB access violations +system.cpu.dtb.data_accesses 30503084 # DTB accesses +system.cpu.itb.fetch_hits 14943347 # ITB hits +system.cpu.itb.fetch_misses 91 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 18604132 # ITB accesses +system.cpu.itb.fetch_accesses 14943438 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -53,247 +53,247 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 58334188 # number of cpu cycles simulated +system.cpu.numCycles 47276068 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 18443606 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 13550904 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1909309 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 15151906 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 11744171 # Number of BTB hits +system.cpu.BPredUnit.lookups 15033034 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10893927 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 965097 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 8612659 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7067377 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1797123 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2508 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 19753130 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 155901269 # Number of instructions fetch has processed -system.cpu.fetch.Branches 18443606 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13541294 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 28873870 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8029527 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 3519156 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1819 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 18604047 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 633220 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 58241050 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.676828 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.252315 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1490279 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 6040 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15621230 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 128217007 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15033034 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 8557656 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22378884 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4633381 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5548401 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1854 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14943347 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 336798 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 47185446 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.717300 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.373013 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 29367180 50.42% 50.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2937608 5.04% 55.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2015194 3.46% 58.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3338566 5.73% 64.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4094138 7.03% 71.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1423310 2.44% 74.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1755062 3.01% 77.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1585835 2.72% 79.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11724157 20.13% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24806562 52.57% 52.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2389979 5.07% 57.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1207538 2.56% 60.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1775063 3.76% 63.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2802024 5.94% 69.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1169800 2.48% 72.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1228019 2.60% 74.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 790135 1.67% 76.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11016326 23.35% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 58241050 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.316171 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.672554 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 21649179 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2708949 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 27144653 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 658698 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6079571 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2969190 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13806 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 150046107 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 43597 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6079571 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 23241789 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 566661 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6095 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 26202396 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2144538 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 144061667 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 244284 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1605069 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 105522995 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 186327738 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 175726328 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10601410 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 47185446 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.317984 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.712091 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17463925 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4249040 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20759249 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1090184 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3623048 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2545357 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12255 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 125130253 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 31826 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3623048 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18629909 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 965094 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8920 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20661182 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3297293 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 122152175 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 11 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 401388 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2422623 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 89685518 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 158620062 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 148881837 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9738225 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 37095634 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 535 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 531 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 6071657 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29750182 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 9383371 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2457988 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 836885 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 120824169 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 510 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 104934850 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 288533 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 35688110 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 27652526 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 121 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 58241050 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.801733 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.850509 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 21258157 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1427 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1434 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8739521 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 25557847 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8301356 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2609711 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 904973 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 106143007 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2358 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 96975947 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 189226 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21491456 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16142477 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1969 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 47185446 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.055209 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.876136 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 19806248 34.01% 34.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11039636 18.96% 52.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 9348946 16.05% 69.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6752104 11.59% 80.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5521673 9.48% 90.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2974014 5.11% 95.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1775531 3.05% 98.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 852122 1.46% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 170776 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12454883 26.40% 26.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9420722 19.97% 46.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8458741 17.93% 64.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6315379 13.38% 77.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4948925 10.49% 88.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2846998 6.03% 94.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1728154 3.66% 97.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 801160 1.70% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 210484 0.45% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 58241050 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 47185446 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 161609 9.97% 9.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 218 0.01% 9.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 6469 0.40% 10.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 2295 0.14% 10.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 845619 52.17% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 62.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 527151 32.52% 95.21% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 77634 4.79% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 186828 11.91% 11.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 238 0.02% 11.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 7150 0.46% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 5464 0.35% 12.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 842994 53.75% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 446294 28.45% 94.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 79499 5.07% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 63561145 60.57% 60.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 485535 0.46% 61.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2794061 2.66% 63.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115045 0.11% 63.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2411045 2.30% 66.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 308682 0.29% 66.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 763571 0.73% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 318 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 27006510 25.74% 92.86% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7488931 7.14% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58979048 60.82% 60.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 480591 0.50% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2800978 2.89% 64.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115548 0.12% 64.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2385848 2.46% 66.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 311419 0.32% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 759609 0.78% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23970757 24.72% 92.60% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7171823 7.40% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 104934850 # Type of FU issued -system.cpu.iq.rate 1.798857 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1620995 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.015448 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 254843963 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 146750024 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 92740043 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15176315 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9791044 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7062550 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 98540004 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8015834 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1319105 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 96975947 # Type of FU issued +system.cpu.iq.rate 2.051269 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1568467 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016174 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 227768377 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 118855856 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87353688 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15126656 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 8815414 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7066282 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90552040 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7992367 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1520027 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 9753984 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 15279 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 28494 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2882268 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5561649 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 19937 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34563 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1800253 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10177 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10514 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6079571 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 81043 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 15363 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 132624218 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 876009 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29750182 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 9383371 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 510 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 184 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 33 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 28494 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1787084 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 342134 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2129218 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 102333218 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25777384 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2601632 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3623048 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 133924 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17201 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 116441723 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 394323 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 25557847 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8301356 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2358 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2853 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 36 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 34563 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 569788 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 508452 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1078240 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 95678343 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23422851 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1297604 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 11799539 # number of nop insts executed -system.cpu.iew.exec_refs 33141424 # number of memory reference insts executed -system.cpu.iew.exec_branches 12916232 # Number of branches executed -system.cpu.iew.exec_stores 7364040 # Number of stores executed -system.cpu.iew.exec_rate 1.754258 # Inst execution rate -system.cpu.iew.wb_sent 101006568 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 99802593 # cumulative count of insts written-back -system.cpu.iew.wb_producers 67789343 # num instructions producing a value -system.cpu.iew.wb_consumers 93484829 # num instructions consuming a value +system.cpu.iew.exec_nop 10296358 # number of nop insts executed +system.cpu.iew.exec_refs 30504278 # number of memory reference insts executed +system.cpu.iew.exec_branches 12076445 # Number of branches executed +system.cpu.iew.exec_stores 7081427 # Number of stores executed +system.cpu.iew.exec_rate 2.023822 # Inst execution rate +system.cpu.iew.wb_sent 94963988 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 94419970 # cumulative count of insts written-back +system.cpu.iew.wb_producers 64608180 # num instructions producing a value +system.cpu.iew.wb_consumers 89987821 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.710877 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.725137 # average fanout of values written-back +system.cpu.iew.wb_rate 1.997204 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717966 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions system.cpu.commit.commitCommittedOps 91903055 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 40723267 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 24539814 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1895854 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 52161479 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.761895 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.510937 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 953116 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43562398 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.109688 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.736301 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 23655247 45.35% 45.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11195713 21.46% 66.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 5070133 9.72% 76.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2810925 5.39% 81.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1675607 3.21% 85.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1392452 2.67% 87.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 795157 1.52% 89.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 831289 1.59% 90.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4734956 9.08% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 17041146 39.12% 39.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9957627 22.86% 61.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4507142 10.35% 72.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2283698 5.24% 77.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1617573 3.71% 81.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1122316 2.58% 83.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 722162 1.66% 85.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 820666 1.88% 87.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5490068 12.60% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 52161479 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43562398 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -304,64 +304,64 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4734956 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5490068 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 180051805 # The number of ROB reads -system.cpu.rob.rob_writes 271380444 # The number of ROB writes -system.cpu.timesIdled 2277 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 93138 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 154514159 # The number of ROB reads +system.cpu.rob.rob_writes 236533126 # The number of ROB writes +system.cpu.timesIdled 2183 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 90622 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.692972 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.692972 # CPI: Total CPI of All Threads -system.cpu.ipc 1.443060 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.443060 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 138495671 # number of integer regfile reads -system.cpu.int_regfile_writes 75435014 # number of integer regfile writes -system.cpu.fp_regfile_reads 6177236 # number of floating regfile reads -system.cpu.fp_regfile_writes 6044349 # number of floating regfile writes -system.cpu.misc_regfile_reads 715554 # number of misc regfile reads +system.cpu.cpi 0.561609 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.561609 # CPI: Total CPI of All Threads +system.cpu.ipc 1.780599 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.780599 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 129442497 # number of integer regfile reads +system.cpu.int_regfile_writes 70765525 # number of integer regfile writes +system.cpu.fp_regfile_reads 6190739 # number of floating regfile reads +system.cpu.fp_regfile_writes 6047859 # number of floating regfile writes +system.cpu.misc_regfile_reads 714278 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 8695 # number of replacements -system.cpu.icache.tagsinuse 1593.002324 # Cycle average of tags in use -system.cpu.icache.total_refs 18592194 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 10628 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1749.359616 # Average number of references to valid blocks. +system.cpu.icache.replacements 10359 # number of replacements +system.cpu.icache.tagsinuse 1607.190165 # Cycle average of tags in use +system.cpu.icache.total_refs 14929668 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 12297 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1214.090266 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1593.002324 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.777833 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.777833 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 18592194 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 18592194 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 18592194 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 18592194 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 18592194 # number of overall hits -system.cpu.icache.overall_hits::total 18592194 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11853 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11853 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11853 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11853 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11853 # number of overall misses -system.cpu.icache.overall_misses::total 11853 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 188036500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 188036500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 188036500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 188036500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 188036500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 188036500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 18604047 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 18604047 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 18604047 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 18604047 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 18604047 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 18604047 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000637 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000637 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000637 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15864.042858 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15864.042858 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15864.042858 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1607.190165 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.784761 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.784761 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14929668 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14929668 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14929668 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14929668 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14929668 # number of overall hits +system.cpu.icache.overall_hits::total 14929668 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 13679 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 13679 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 13679 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 13679 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 13679 # number of overall misses +system.cpu.icache.overall_misses::total 13679 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 203969000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 203969000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 203969000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 203969000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 203969000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 203969000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14943347 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14943347 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14943347 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14943347 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14943347 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14943347 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000915 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000915 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000915 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14911.104613 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14911.104613 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14911.104613 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -370,258 +370,258 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1225 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1225 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1225 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1225 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1225 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1225 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10628 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 10628 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 10628 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 10628 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 10628 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 10628 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 124769000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 124769000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 124769000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 124769000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 124769000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 124769000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000571 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000571 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000571 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11739.649981 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11739.649981 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11739.649981 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1382 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1382 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1382 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1382 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1382 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1382 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12297 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 12297 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 12297 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 12297 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 12297 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 12297 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 130905500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 130905500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 130905500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 130905500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 130905500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 130905500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000823 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000823 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000823 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10645.319997 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10645.319997 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10645.319997 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 159 # number of replacements -system.cpu.dcache.tagsinuse 1462.507461 # Cycle average of tags in use -system.cpu.dcache.total_refs 30399158 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2246 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 13534.798753 # Average number of references to valid blocks. +system.cpu.dcache.replacements 158 # number of replacements +system.cpu.dcache.tagsinuse 1455.343539 # Cycle average of tags in use +system.cpu.dcache.total_refs 28184934 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2238 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12593.804290 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1462.507461 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.357057 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.357057 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 23906051 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23906051 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6493055 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6493055 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 52 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 52 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 30399106 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 30399106 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 30399106 # number of overall hits -system.cpu.dcache.overall_hits::total 30399106 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 938 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 938 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8048 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8048 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 1455.343539 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.355308 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.355308 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 21691339 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21691339 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6493048 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6493048 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 547 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 547 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28184387 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28184387 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28184387 # number of overall hits +system.cpu.dcache.overall_hits::total 28184387 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 946 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 946 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8055 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8055 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 8986 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 8986 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 8986 # number of overall misses -system.cpu.dcache.overall_misses::total 8986 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 28163500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 28163500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 289889000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 289889000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9001 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9001 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9001 # number of overall misses +system.cpu.dcache.overall_misses::total 9001 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 28453500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 28453500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 289283500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 289283500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 38000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 38000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 318052500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 318052500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 318052500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 318052500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23906989 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23906989 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 317737000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 317737000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 317737000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 317737000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21692285 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21692285 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 53 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 53 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 30408092 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 30408092 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 30408092 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 30408092 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000039 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001238 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018868 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000296 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000296 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30025.053305 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36020.004970 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 548 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 548 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28193388 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28193388 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28193388 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28193388 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000044 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001239 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001825 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000319 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000319 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30077.695560 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35913.531968 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35394.224349 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35394.224349 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2500 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35300.188868 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35300.188868 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6500 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 108 # number of writebacks system.cpu.dcache.writebacks::total 108 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 424 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 424 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6317 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6317 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6741 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6741 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6741 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6741 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 514 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 514 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1731 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1731 # number of WriteReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 435 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 435 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6329 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6329 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6764 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6764 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6764 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6764 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 511 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 511 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1726 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1726 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2245 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2245 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2245 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2245 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16469500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 16469500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61655000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 61655000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2237 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2237 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2237 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2237 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16444500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 16444500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61474000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 61474000 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 35000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 35000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78124500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 78124500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78124500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 78124500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018868 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000074 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000074 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32041.828794 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35618.139804 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 77918500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 77918500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 77918500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 77918500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000265 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.001825 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000079 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000079 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32181.017613 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35616.454229 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 35000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34799.331849 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34799.331849 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34831.694233 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34831.694233 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2400.275766 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7666 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3556 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.155793 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2429.489974 # Cycle average of tags in use +system.cpu.l2cache.total_refs 9270 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3617 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.562897 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.633584 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2000.487710 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 382.154472 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000538 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.061050 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.011662 # 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miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.963936 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34334.103665 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34410.675381 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34726.846424 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34334.103665 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34659.815242 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34334.103665 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34659.815242 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1726 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1726 # 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miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.251525 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.964254 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34320.562561 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34414.847162 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34718.823529 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34320.562561 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34654.309546 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34320.562561 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34654.309546 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 2000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2000 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3029 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 459 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3488 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1706 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1706 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3029 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2165 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5194 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3029 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2165 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5194 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 94144500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14345500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 108490000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53828000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53828000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 94144500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 68173500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 162318000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 94144500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 68173500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 162318000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.285002 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.891262 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985557 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.285002 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963936 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.285002 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963936 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31081.049851 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31253.812636 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31552.168816 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31081.049851 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31488.914550 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31081.049851 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31488.914550 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3093 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 458 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3551 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1700 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1700 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3093 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2158 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5251 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3093 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2158 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5251 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 96110500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14313000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 110423500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53634000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53634000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 96110500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 67947000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 164057500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 96110500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67947000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 164057500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.251525 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.894531 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984936 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.251525 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964254 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.251525 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964254 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31073.553185 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31251.091703 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31549.411765 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31073.553185 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31486.098239 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31073.553185 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31486.098239 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout index d10088405..8c858c201 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 16:37:09 +gem5 compiled Feb 12 2012 17:19:56 +gem5 started Feb 12 2012 20:58:01 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing +Couldn't unlink build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing/smred.sav +Couldn't unlink build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -21,4 +23,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 105850842000 because target called exit() +122 123 124 Exiting @ tick 88632152500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 98dddaff0..64cc4b80a 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,25 +1,25 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.105851 # Number of seconds simulated -sim_ticks 105850842000 # Number of ticks simulated -final_tick 105850842000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.088632 # Number of seconds simulated +sim_ticks 88632152500 # Number of ticks simulated +final_tick 88632152500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 122767 # Simulator instruction rate (inst/s) -host_op_rate 134419 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 75414821 # Simulator tick rate (ticks/s) -host_mem_usage 227032 # Number of bytes of host memory used -host_seconds 1403.58 # Real time elapsed on the host -sim_insts 172314144 # Number of instructions simulated -sim_ops 188667627 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 239936 # Number of bytes read from this memory -system.physmem.bytes_inst_read 128320 # Number of instructions bytes read from this memory +host_inst_rate 134694 # Simulator instruction rate (inst/s) +host_op_rate 147478 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69281557 # Simulator tick rate (ticks/s) +host_mem_usage 227272 # Number of bytes of host memory used +host_seconds 1279.30 # Real time elapsed on the host +sim_insts 172315139 # Number of instructions simulated +sim_ops 188668622 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 244352 # Number of bytes read from this memory +system.physmem.bytes_inst_read 132032 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 3749 # Number of read requests responded to by this memory +system.physmem.num_reads 3818 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2266737 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1212272 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2266737 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 2756923 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1489663 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 2756923 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -63,315 +63,315 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 211701685 # number of cpu cycles simulated +system.cpu.numCycles 177264306 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 102100879 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 80677195 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 9930193 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 84233443 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 79245701 # Number of BTB hits +system.cpu.BPredUnit.lookups 96525090 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 74749964 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 6668938 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 46796658 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 44215963 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 4698090 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 111402 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 44542965 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 416708415 # Number of instructions fetch has processed -system.cpu.fetch.Branches 102100879 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 83943791 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 108793327 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 33207424 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 35058719 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 11 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 259 # Number of stall cycles due to pending traps +system.cpu.BPredUnit.usedRAS 4389679 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 114813 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 39966229 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 381133369 # Number of instructions fetch has processed +system.cpu.fetch.Branches 96525090 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48605642 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80754991 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 27412697 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 35762422 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9389 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.CacheLines 40619675 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2204435 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 211643202 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.135620 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.646860 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 36758976 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1679336 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 177207232 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.350259 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.058598 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 103052143 48.69% 48.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4614041 2.18% 50.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 32953123 15.57% 66.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 18235328 8.62% 75.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 9171108 4.33% 79.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 12530200 5.92% 85.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 8476968 4.01% 89.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4316297 2.04% 91.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 18293994 8.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 96615622 54.52% 54.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5430463 3.06% 57.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10300720 5.81% 63.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10325695 5.83% 69.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8756862 4.94% 74.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6889395 3.89% 78.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6237128 3.52% 81.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8634116 4.87% 86.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 24017231 13.55% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 211643202 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.482287 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.968376 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 53231519 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 33609414 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 100494512 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1217161 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 23090596 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14181130 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 166488 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 422617374 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 695976 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 23090596 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 62189594 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 455687 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 28663702 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 92677243 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4566380 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 388527700 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 20997 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2241803 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 666137382 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1656361753 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1638646831 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 17714922 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 298061936 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 368075446 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2723266 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2675408 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 23504222 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 46900559 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16903337 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3858030 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2525525 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 332647611 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2225423 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 261830951 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 960204 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 143464205 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 342029155 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 589405 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 211643202 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.237134 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.489338 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 177207232 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.544526 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.150085 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 46183847 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 34297054 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74780894 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1386206 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 20559231 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14846637 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 165269 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 392589126 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 748420 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 20559231 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 52356007 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 443712 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 29007637 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 69958724 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4881921 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 367191514 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 92621 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2515930 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 627979317 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1558602975 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1541578337 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 17024638 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 298063528 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 329915789 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2303042 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2294526 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 21773052 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 41898813 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 15562062 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3360389 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2124393 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 324040554 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2103109 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 248819756 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 576048 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 136002156 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 346792965 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 466892 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 177207232 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.404117 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.633607 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 97826086 46.22% 46.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 37864076 17.89% 64.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34104807 16.11% 80.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 22781361 10.76% 90.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 11447248 5.41% 96.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4765675 2.25% 98.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2321089 1.10% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 393603 0.19% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 139257 0.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 78492090 44.29% 44.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 28577659 16.13% 60.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 26660356 15.04% 75.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 21359445 12.05% 87.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12490578 7.05% 94.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 5763951 3.25% 97.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3149996 1.78% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 544249 0.31% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 168908 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 211643202 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 177207232 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 397917 18.24% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5522 0.25% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 50 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 46 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1324685 60.73% 79.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 453082 20.77% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 627952 27.03% 27.03% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5535 0.24% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 48 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 1 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 27.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1223626 52.68% 79.95% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 465789 20.05% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 204918446 78.26% 78.26% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 928788 0.35% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33078 0.01% 78.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 166576 0.06% 78.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 257183 0.10% 78.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76398 0.03% 78.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 467924 0.18% 79.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 207596 0.08% 79.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71825 0.03% 79.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 325 0.00% 79.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 40744644 15.56% 94.67% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13958168 5.33% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 194916381 78.34% 78.34% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 997256 0.40% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33202 0.01% 78.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 163976 0.07% 78.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 252533 0.10% 78.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76462 0.03% 78.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 463893 0.19% 79.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206151 0.08% 79.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71843 0.03% 79.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.25% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 37907135 15.23% 94.48% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13730603 5.52% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 261830951 # Type of FU issued -system.cpu.iq.rate 1.236792 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2181302 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008331 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 734699293 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 476117347 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 242859396 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3747317 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2232204 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1844998 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 262127165 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1885088 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1590290 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 248819756 # Type of FU issued +system.cpu.iq.rate 1.403665 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2322951 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009336 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 674003670 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 460004017 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 236904190 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3742073 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2153997 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1836768 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 249257876 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1884831 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1793335 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 17048851 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 31549 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12762 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4256480 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 12046906 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 20817 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12587 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2915006 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 20 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 150 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 23090596 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 13781 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 840 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 334926486 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 3752435 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 46900559 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16903337 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2201532 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 340 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 255 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12762 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 9994816 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1695108 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 11689924 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 249206258 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 38606621 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 12624693 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 20559231 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 11749 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 500 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 326199297 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1048998 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 41898813 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 15562062 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2080622 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 86 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 254 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12587 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4245338 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3938864 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8184202 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 241936044 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 36336721 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6883712 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 53452 # number of nop insts executed -system.cpu.iew.exec_refs 52203623 # number of memory reference insts executed -system.cpu.iew.exec_branches 52584405 # Number of branches executed -system.cpu.iew.exec_stores 13597002 # Number of stores executed -system.cpu.iew.exec_rate 1.177158 # Inst execution rate -system.cpu.iew.wb_sent 246234772 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 244704394 # cumulative count of insts written-back -system.cpu.iew.wb_producers 148512928 # num instructions producing a value -system.cpu.iew.wb_consumers 247801271 # num instructions consuming a value +system.cpu.iew.exec_nop 55634 # number of nop insts executed +system.cpu.iew.exec_refs 49775211 # number of memory reference insts executed +system.cpu.iew.exec_branches 53836233 # Number of branches executed +system.cpu.iew.exec_stores 13438490 # Number of stores executed +system.cpu.iew.exec_rate 1.364832 # Inst execution rate +system.cpu.iew.wb_sent 239697329 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 238740958 # cumulative count of insts written-back +system.cpu.iew.wb_producers 143497606 # num instructions producing a value +system.cpu.iew.wb_consumers 250089451 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.155893 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.599323 # average fanout of values written-back +system.cpu.iew.wb_rate 1.346808 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.573785 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 172328532 # The number of committed instructions -system.cpu.commit.commitCommittedOps 188682015 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 146244510 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1636018 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9791900 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 188552607 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.000686 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.681539 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 172329527 # The number of committed instructions +system.cpu.commit.commitCommittedOps 188683010 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 137516300 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1636217 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 6533063 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 156648002 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.204503 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.917568 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 105375521 55.89% 55.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 40844225 21.66% 77.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 19484606 10.33% 87.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8759294 4.65% 92.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4914501 2.61% 95.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2011973 1.07% 96.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1708688 0.91% 97.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1009693 0.54% 97.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4444106 2.36% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 79778069 50.93% 50.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 37231664 23.77% 74.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15824405 10.10% 84.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8489087 5.42% 90.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4756905 3.04% 93.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1480671 0.95% 94.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1767391 1.13% 95.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1258526 0.80% 96.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6061284 3.87% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 188552607 # Number of insts commited each cycle -system.cpu.commit.committedInsts 172328532 # Number of instructions committed -system.cpu.commit.committedOps 188682015 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 156648002 # Number of insts commited each cycle +system.cpu.commit.committedInsts 172329527 # Number of instructions committed +system.cpu.commit.committedOps 188683010 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 42498565 # Number of memory references committed -system.cpu.commit.loads 29851708 # Number of loads committed +system.cpu.commit.refs 42498963 # Number of memory references committed +system.cpu.commit.loads 29851907 # Number of loads committed system.cpu.commit.membars 22408 # Number of memory barriers committed -system.cpu.commit.branches 40283906 # Number of branches committed +system.cpu.commit.branches 40284105 # Number of branches committed system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. -system.cpu.commit.int_insts 150115117 # Number of committed integer instructions. +system.cpu.commit.int_insts 150115913 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4444106 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6061284 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 519029825 # The number of ROB reads -system.cpu.rob.rob_writes 693007050 # The number of ROB writes -system.cpu.timesIdled 1719 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 58483 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 172314144 # Number of Instructions Simulated -system.cpu.committedOps 188667627 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 172314144 # Number of Instructions Simulated -system.cpu.cpi 1.228580 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.228580 # CPI: Total CPI of All Threads -system.cpu.ipc 0.813948 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.813948 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1111988877 # number of integer regfile reads -system.cpu.int_regfile_writes 407368356 # number of integer regfile writes -system.cpu.fp_regfile_reads 2928539 # number of floating regfile reads -system.cpu.fp_regfile_writes 2498508 # number of floating regfile writes -system.cpu.misc_regfile_reads 502946356 # number of misc regfile reads -system.cpu.misc_regfile_writes 824482 # number of misc regfile writes -system.cpu.icache.replacements 1934 # number of replacements -system.cpu.icache.tagsinuse 1329.301324 # Cycle average of tags in use -system.cpu.icache.total_refs 40615441 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 3640 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11158.088187 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 476780827 # The number of ROB reads +system.cpu.rob.rob_writes 673054212 # The number of ROB writes +system.cpu.timesIdled 1680 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 57074 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 172315139 # Number of Instructions Simulated +system.cpu.committedOps 188668622 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 172315139 # Number of Instructions Simulated +system.cpu.cpi 1.028722 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.028722 # CPI: Total CPI of All Threads +system.cpu.ipc 0.972080 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.972080 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1073592031 # number of integer regfile reads +system.cpu.int_regfile_writes 384645437 # number of integer regfile writes +system.cpu.fp_regfile_reads 2906196 # number of floating regfile reads +system.cpu.fp_regfile_writes 2487132 # number of floating regfile writes +system.cpu.misc_regfile_reads 464057527 # number of misc regfile reads +system.cpu.misc_regfile_writes 824880 # number of misc regfile writes +system.cpu.icache.replacements 2566 # number of replacements +system.cpu.icache.tagsinuse 1366.287383 # Cycle average of tags in use +system.cpu.icache.total_refs 36753975 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4308 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 8531.563370 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1329.301324 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.649073 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.649073 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 40615441 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 40615441 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 40615441 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 40615441 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 40615441 # number of overall hits -system.cpu.icache.overall_hits::total 40615441 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4234 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4234 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4234 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4234 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4234 # number of overall misses -system.cpu.icache.overall_misses::total 4234 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 101275500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 101275500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 101275500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 101275500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 101275500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 101275500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 40619675 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 40619675 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 40619675 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 40619675 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 40619675 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 40619675 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000104 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000104 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000104 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23919.579594 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23919.579594 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23919.579594 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1366.287383 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.667133 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.667133 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 36753975 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 36753975 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 36753975 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 36753975 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 36753975 # number of overall hits +system.cpu.icache.overall_hits::total 36753975 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5001 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5001 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5001 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5001 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5001 # number of overall misses +system.cpu.icache.overall_misses::total 5001 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 108825000 # 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number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000136 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000136 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000136 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21760.647870 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21760.647870 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21760.647870 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -380,214 +380,219 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 594 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 594 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 594 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 594 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 594 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 594 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3640 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 3640 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 3640 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 3640 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 3640 # 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average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20486.950549 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20486.950549 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 692 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 692 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 692 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 692 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 692 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 692 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4309 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4309 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4309 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4309 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4309 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4309 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 78064500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 78064500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 78064500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 78064500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 78064500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 78064500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18116.616384 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18116.616384 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18116.616384 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 53 # number of replacements -system.cpu.dcache.tagsinuse 1403.723956 # Cycle average of tags in use -system.cpu.dcache.total_refs 48643693 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1846 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 26350.862947 # Average number of references to valid blocks. +system.cpu.dcache.replacements 55 # number of replacements +system.cpu.dcache.tagsinuse 1415.234721 # Cycle average of tags in use +system.cpu.dcache.total_refs 46401176 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1864 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 24893.334764 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1403.723956 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.342706 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.342706 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 36234545 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 36234545 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12356727 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12356727 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 27791 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 27791 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 24630 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 24630 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 48591272 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 48591272 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 48591272 # number of overall hits -system.cpu.dcache.overall_hits::total 48591272 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1808 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1808 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 7560 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 7560 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 1415.234721 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.345516 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.345516 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 33991693 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 33991693 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12356758 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12356758 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 27891 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 27891 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 24829 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 24829 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 46348451 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 46348451 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 46348451 # number of overall hits +system.cpu.dcache.overall_hits::total 46348451 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1783 # 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number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 63500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 63500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 296685500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 296685500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 296685500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 296685500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 36236353 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 36236353 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9312 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9312 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9312 # number of overall misses +system.cpu.dcache.overall_misses::total 9312 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 58909500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 58909500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 235574500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 235574500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 64000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 64000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 294484000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 294484000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 294484000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 294484000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 33993476 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 33993476 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 27793 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 27793 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 24630 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 24630 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 48600640 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 48600640 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 48600640 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 48600640 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000050 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000611 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 27893 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 27893 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 24829 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 24829 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46357763 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46357763 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46357763 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46357763 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000052 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000609 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000072 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000193 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000193 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32925.331858 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31369.907407 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31670.100342 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31670.100342 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.000201 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000201 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33039.540101 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31288.949396 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 32000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31624.140893 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31624.140893 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 20000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # 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number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2005 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1744 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3749 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2005 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1744 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 3749 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 62251500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20643500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 82895000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33590000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33590000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 62251500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 54233500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 116485000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 62251500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 54233500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 116485000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.550824 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.876821 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991751 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.550824 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.944745 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.550824 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.944745 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31048.129676 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31183.534743 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31044.362292 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31048.129676 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31097.190367 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31048.129676 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31097.190367 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 17 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 20 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 17 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 20 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 17 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 20 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2063 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 675 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2738 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1080 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1080 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2063 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1755 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3818 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2063 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1755 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 3818 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 64062500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 21038500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 85101000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 31000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 31000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33524500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33524500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64062500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 54563000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 118625500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64062500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 54563000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 118625500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.478877 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.872093 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.990826 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.478877 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.941524 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.478877 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.941524 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31053.078042 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31168.148148 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31041.203704 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31053.078042 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31090.028490 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31053.078042 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31090.028490 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout index 99b3e7f21..138f6116a 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:53 -gem5 started Feb 11 2012 15:02:46 +gem5 compiled Feb 12 2012 17:18:12 +gem5 started Feb 12 2012 19:27:36 gem5 executing on zizzer command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing +Couldn't unlink build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing/smred.sav +Couldn't unlink build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -22,4 +24,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 96266258000 because target called exit() +122 123 124 Exiting @ tick 87727531000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 0aeabdea4..7c2d38b1f 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,264 +1,264 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.096266 # Number of seconds simulated -sim_ticks 96266258000 # Number of ticks simulated -final_tick 96266258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.087728 # Number of seconds simulated +sim_ticks 87727531000 # Number of ticks simulated +final_tick 87727531000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 89516 # Simulator instruction rate (inst/s) -host_op_rate 150037 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 65247901 # Simulator tick rate (ticks/s) -host_mem_usage 229524 # Number of bytes of host memory used -host_seconds 1475.39 # Real time elapsed on the host +host_inst_rate 101058 # Simulator instruction rate (inst/s) +host_op_rate 169383 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67127344 # Simulator tick rate (ticks/s) +host_mem_usage 229892 # Number of bytes of host memory used +host_seconds 1306.88 # Real time elapsed on the host sim_insts 132071227 # Number of instructions simulated sim_ops 221363017 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 339712 # Number of bytes read from this memory -system.physmem.bytes_inst_read 214912 # Number of instructions bytes read from this memory +system.physmem.bytes_read 345792 # Number of bytes read from this memory +system.physmem.bytes_inst_read 220224 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 5308 # Number of read requests responded to by this memory +system.physmem.num_reads 5403 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 3528879 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 2232475 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 3528879 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 3941659 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 2510318 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 3941659 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 192532517 # number of cpu cycles simulated +system.cpu.numCycles 175455063 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 25728486 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 25728486 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2892788 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 23533152 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 20839978 # Number of BTB hits +system.cpu.BPredUnit.lookups 20916443 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 20916443 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2209285 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 15543482 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 13847483 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 30657479 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 260466955 # Number of instructions fetch has processed -system.cpu.fetch.Branches 25728486 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 20839978 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 70644215 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 26785814 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 67566342 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 136 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1120 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 28758661 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 555177 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 192452166 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.262310 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.335029 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27331578 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 227091825 # Number of instructions fetch has processed +system.cpu.fetch.Branches 20916443 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13847483 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 59872682 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 19479342 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 71171142 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1142 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9711 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 25826236 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 465691 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 175377754 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.138493 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.301400 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 123644733 64.25% 64.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4091160 2.13% 66.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3200074 1.66% 68.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4567374 2.37% 70.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4265123 2.22% 72.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4442159 2.31% 74.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5459285 2.84% 77.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3091960 1.61% 79.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 39690298 20.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 117181647 66.82% 66.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3214918 1.83% 68.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2487615 1.42% 70.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3152390 1.80% 71.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3541045 2.02% 73.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3761465 2.14% 76.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4534795 2.59% 78.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2814480 1.60% 80.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 34689399 19.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 192452166 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.133632 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.352847 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 44411978 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 57625858 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 56973408 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9858048 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 23582874 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 423042956 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 23582874 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 52998252 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14705836 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 23082 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 57546904 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 43595218 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 410638323 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 18885984 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22330558 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 437009036 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1063910767 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1053088723 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10822044 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 175377754 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.119213 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.294302 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 40655078 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 60979767 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 46580847 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10170563 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 16991499 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 366154541 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 16991499 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 48551575 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 16255360 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 22908 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 48159937 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 45396475 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 356930622 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 31 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 20611614 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22556100 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 370578330 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 915376002 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 905357204 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10018798 # Number of floating rename lookups system.cpu.rename.CommittedMaps 234363409 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 202645627 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1783 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1777 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 94569707 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 103994638 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 37171273 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 66711674 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 21456392 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 395555693 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2683 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 287296212 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 238230 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 173600960 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 348497721 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1437 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 192452166 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.492819 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.482262 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 136214921 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1884 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1879 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 95075204 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89798900 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 33126150 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 59105892 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 19470251 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 344622515 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 7679 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 271009025 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 252543 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 122771831 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 234148079 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 6433 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 175377754 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.545287 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.468253 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 60170871 31.27% 31.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 53695201 27.90% 59.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 36000837 18.71% 77.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20815986 10.82% 88.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 13514067 7.02% 95.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 5325466 2.77% 98.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2181156 1.13% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 607811 0.32% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 140771 0.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 49123743 28.01% 28.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 52511910 29.94% 57.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 34319849 19.57% 77.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19020528 10.85% 88.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12714994 7.25% 95.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4949443 2.82% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2083502 1.19% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 542650 0.31% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 111135 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 192452166 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 175377754 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 103783 3.80% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2313613 84.82% 88.62% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 310319 11.38% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 91290 3.51% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2230006 85.80% 89.31% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 277845 10.69% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1202882 0.42% 0.42% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 186701896 64.99% 65.40% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.40% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1648118 0.57% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 73212241 25.48% 91.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 24531075 8.54% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1212979 0.45% 0.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 176351426 65.07% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1596977 0.59% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 68342169 25.22% 91.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 23505474 8.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 287296212 # Type of FU issued -system.cpu.iq.rate 1.492196 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2727715 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009494 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 764505561 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 564134434 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 277997574 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5504974 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 5363501 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2644368 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 286052729 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2768316 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18967849 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 271009025 # Type of FU issued +system.cpu.iq.rate 1.544606 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2599141 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009591 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 714934206 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 462829464 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 263397424 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 5313282 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4873666 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2553131 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 269732632 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2662555 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18949841 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 47345048 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 33748 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 344727 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16655557 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 33149310 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 29835 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 306343 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12610434 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 48770 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 47714 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 23582874 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 506702 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 199063 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 395558376 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 136305 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 103994638 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 37171273 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1768 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 106766 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 14420 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 344727 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2499729 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 593078 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3092807 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 283409034 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 71642320 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3887178 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 16991499 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 515293 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 247384 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 344630194 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 299081 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 89798900 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 33126150 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1841 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 161274 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 32917 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 306343 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1299828 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1028827 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2328655 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 267903545 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 67266011 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3105480 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 95673519 # number of memory reference insts executed -system.cpu.iew.exec_branches 15642768 # Number of branches executed -system.cpu.iew.exec_stores 24031199 # Number of stores executed -system.cpu.iew.exec_rate 1.472006 # Inst execution rate -system.cpu.iew.wb_sent 281921944 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 280641942 # cumulative count of insts written-back -system.cpu.iew.wb_producers 227553614 # num instructions producing a value -system.cpu.iew.wb_consumers 378165457 # num instructions consuming a value +system.cpu.iew.exec_refs 90381113 # number of memory reference insts executed +system.cpu.iew.exec_branches 14784987 # Number of branches executed +system.cpu.iew.exec_stores 23115102 # Number of stores executed +system.cpu.iew.exec_rate 1.526907 # Inst execution rate +system.cpu.iew.wb_sent 266831657 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 265950555 # cumulative count of insts written-back +system.cpu.iew.wb_producers 214539100 # num instructions producing a value +system.cpu.iew.wb_consumers 362277288 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.457634 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.601730 # average fanout of values written-back +system.cpu.iew.wb_rate 1.515776 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.592196 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 132071227 # The number of committed instructions system.cpu.commit.commitCommittedOps 221363017 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 174222633 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 123379420 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2892920 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 168869292 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.310854 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.745147 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2210265 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158386255 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.397615 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.796088 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 63124360 37.38% 37.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 62150025 36.80% 74.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15630374 9.26% 83.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11975959 7.09% 90.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 5416595 3.21% 93.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2994905 1.77% 95.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2021663 1.20% 96.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1189804 0.70% 97.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4365607 2.59% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 54200924 34.22% 34.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 60421756 38.15% 72.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15533803 9.81% 82.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12711410 8.03% 90.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4532649 2.86% 93.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2958963 1.87% 94.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2077692 1.31% 96.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1244602 0.79% 97.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4704456 2.97% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 168869292 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 158386255 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071227 # Number of instructions committed system.cpu.commit.committedOps 221363017 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -269,64 +269,64 @@ system.cpu.commit.branches 12326943 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339606 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4365607 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4704456 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 560089335 # The number of ROB reads -system.cpu.rob.rob_writes 814800236 # The number of ROB writes -system.cpu.timesIdled 1747 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 80351 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 498424236 # The number of ROB reads +system.cpu.rob.rob_writes 706514017 # The number of ROB writes +system.cpu.timesIdled 1681 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 77309 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071227 # Number of Instructions Simulated system.cpu.committedOps 221363017 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071227 # Number of Instructions Simulated -system.cpu.cpi 1.457793 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.457793 # CPI: Total CPI of All Threads -system.cpu.ipc 0.685968 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.685968 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 530367480 # number of integer regfile reads -system.cpu.int_regfile_writes 288604591 # number of integer regfile writes -system.cpu.fp_regfile_reads 3608788 # number of floating regfile reads -system.cpu.fp_regfile_writes 2298113 # number of floating regfile writes -system.cpu.misc_regfile_reads 149639402 # number of misc regfile reads +system.cpu.cpi 1.328488 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.328488 # CPI: Total CPI of All Threads +system.cpu.ipc 0.752735 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.752735 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 511675262 # number of integer regfile reads +system.cpu.int_regfile_writes 274174484 # number of integer regfile writes +system.cpu.fp_regfile_reads 3515494 # number of floating regfile reads +system.cpu.fp_regfile_writes 2227241 # number of floating regfile writes +system.cpu.misc_regfile_reads 139504609 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.icache.replacements 4205 # number of replacements -system.cpu.icache.tagsinuse 1597.649860 # Cycle average of tags in use -system.cpu.icache.total_refs 28751182 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 6167 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4662.101832 # Average number of references to valid blocks. +system.cpu.icache.replacements 5602 # number of replacements +system.cpu.icache.tagsinuse 1631.479553 # Cycle average of tags in use +system.cpu.icache.total_refs 25817139 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7573 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 3409.103262 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1597.649860 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.780102 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.780102 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 28751182 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 28751182 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 28751182 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 28751182 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 28751182 # number of overall hits -system.cpu.icache.overall_hits::total 28751182 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 7479 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 7479 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 7479 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 7479 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 7479 # number of overall misses -system.cpu.icache.overall_misses::total 7479 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 173725000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 173725000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 173725000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 173725000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 173725000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 173725000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 28758661 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 28758661 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 28758661 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 28758661 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 28758661 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 28758661 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000260 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000260 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000260 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23228.372777 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23228.372777 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23228.372777 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1631.479553 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.796621 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.796621 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25817139 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25817139 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25817139 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25817139 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25817139 # number of overall hits +system.cpu.icache.overall_hits::total 25817139 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 9097 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 9097 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 9097 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 9097 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 9097 # number of overall misses +system.cpu.icache.overall_misses::total 9097 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 188035000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 188035000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 188035000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 188035000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 188035000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 188035000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25826236 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25826236 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25826236 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25826236 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25826236 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25826236 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000352 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000352 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000352 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20670.001099 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20670.001099 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20670.001099 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -335,80 +335,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1119 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1119 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1119 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1119 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1119 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1119 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6360 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 6360 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 6360 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6360 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6360 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6360 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 125233500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 125233500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 125233500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 125233500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 125233500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 125233500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000221 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000221 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000221 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19690.801887 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19690.801887 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19690.801887 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1378 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1378 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1378 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1378 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1378 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1378 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7719 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 7719 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 7719 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 7719 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 7719 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 7719 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 130954500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 130954500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 130954500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 130954500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 130954500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 130954500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16965.215702 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16965.215702 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16965.215702 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 56 # number of replacements -system.cpu.dcache.tagsinuse 1415.486536 # Cycle average of tags in use -system.cpu.dcache.total_refs 72938173 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1987 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 36707.686462 # Average number of references to valid blocks. +system.cpu.dcache.replacements 54 # number of replacements +system.cpu.dcache.tagsinuse 1429.840369 # Cycle average of tags in use +system.cpu.dcache.total_refs 68659767 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1998 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34364.247748 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1415.486536 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.345578 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.345578 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 52423955 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 52423955 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513973 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513973 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 72937928 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 72937928 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 72937928 # number of overall hits -system.cpu.dcache.overall_hits::total 72937928 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 771 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 771 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1757 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1757 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2528 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2528 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2528 # number of overall misses -system.cpu.dcache.overall_misses::total 2528 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24605500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24605500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 66582500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 66582500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 91188000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 91188000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 91188000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 91188000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 52424726 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 52424726 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 1429.840369 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.349082 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.349082 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 48145557 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 48145557 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20514023 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20514023 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 68659580 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 68659580 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 68659580 # number of overall hits +system.cpu.dcache.overall_hits::total 68659580 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 765 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 765 # 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number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 89367500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 89367500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 48146322 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 48146322 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 72940456 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 72940456 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 72940456 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 72940456 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000015 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000086 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000035 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000035 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31913.748379 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37895.560615 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36071.202532 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36071.202532 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 68662052 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 68662052 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 68662052 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 68662052 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000016 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000083 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000036 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000036 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32168.627451 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37937.024019 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36151.901294 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36151.901294 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -419,119 +419,119 @@ system.cpu.dcache.fast_writes 0 # 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miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.980392 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34257.742704 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34167.088608 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34126.366559 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34257.742704 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34134.615385 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34257.742704 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34134.615385 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994869 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.454377 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.981000 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.454377 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.981000 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34254.577158 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34183.698297 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34158.607350 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34254.577158 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34163.863405 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34254.577158 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34163.863405 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -540,48 +540,48 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3358 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 395 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3753 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 193 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 193 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1555 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1555 # 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number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48232500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48232500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104175500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 60470500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 164646000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104175500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 60470500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 164646000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.544511 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.927230 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3441 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 411 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3852 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 146 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 146 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1551 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1551 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3441 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1962 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5403 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3441 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1962 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5403 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 106751500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12743500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 119495000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 4526000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 4526000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48112000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48112000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106751500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 60855500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 167607000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106751500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 60855500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 167607000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.454377 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.931973 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994882 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.544511 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980392 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.544511 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980392 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31023.079214 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30982.278481 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994869 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.454377 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.981000 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.454377 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.981000 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31023.394362 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31006.082725 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31017.684887 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31023.079214 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31010.512821 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31023.079214 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31010.512821 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31019.987105 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31023.394362 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31017.074414 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31023.394362 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31017.074414 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |