diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-06-27 05:49:51 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-06-27 05:49:51 -0400 |
| commit | 5a15909bac241dc795c691d49c4e2c68cab745f4 (patch) | |
| tree | d0ae694e320c725ed8116943c7179516567279f3 /tests/long/se/70.twolf/ref | |
| parent | ac515d7a9b131ffc9e128bd209fcddb2f383808b (diff) | |
| download | gem5-5a15909bac241dc795c691d49c4e2c68cab745f4.tar.xz | |
stats: Update stats for monitor, cache and bus changes
This patch removes the sparse histogram total from the CommMonitor
stats. It also bumps the stats after the unit fixes in the atomic
cache access. Lastly, it updates the stats to match the new port
ordering. All numbers are the same, and the only thing that changes is
which master corresponds to what port index.
Diffstat (limited to 'tests/long/se/70.twolf/ref')
8 files changed, 2441 insertions, 2446 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 4f9464f49..9ab9303b1 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.041671 # Number of seconds simulated -sim_ticks 41671058000 # Number of ticks simulated -final_tick 41671058000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.041672 # Number of seconds simulated +sim_ticks 41671895000 # Number of ticks simulated +final_tick 41671895000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79080 # Simulator instruction rate (inst/s) -host_op_rate 79080 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35856814 # Simulator tick rate (ticks/s) -host_mem_usage 228800 # Number of bytes of host memory used -host_seconds 1162.15 # Real time elapsed on the host +host_inst_rate 84546 # Simulator instruction rate (inst/s) +host_op_rate 84546 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38336000 # Simulator tick rate (ticks/s) +host_mem_usage 228812 # Number of bytes of host memory used +host_seconds 1087.02 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 178816 # Nu system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 4291132 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3292837 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7583969 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4291132 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4291132 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4291132 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3292837 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7583969 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 4291046 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3292771 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7583816 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4291046 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4291046 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4291046 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3292771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7583816 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 4938 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 4938 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 41670985500 # Total gap between requests +system.physmem.totGap 41671821000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,10 +85,10 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 3344 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1140 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3328 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1155 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 428 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -213,14 +213,14 @@ system.physmem.bytesPerActivate::6144-6145 1 0.28% 98.33% # system.physmem.bytesPerActivate::8128-8129 2 0.56% 98.89% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 4 1.11% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 360 # Bytes accessed per row activation -system.physmem.totQLat 21938250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 110827000 # Sum of mem lat for all requests +system.physmem.totQLat 20561250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 109587500 # Sum of mem lat for all requests system.physmem.totBusLat 24690000 # Total cycles spent in databus access -system.physmem.totBankLat 64198750 # Total cycles spent in bank access -system.physmem.avgQLat 4442.74 # Average queueing delay per request -system.physmem.avgBankLat 13000.96 # Average bank access latency per request +system.physmem.totBankLat 64336250 # Total cycles spent in bank access +system.physmem.avgQLat 4163.88 # Average queueing delay per request +system.physmem.avgBankLat 13028.81 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22443.70 # Average memory access latency +system.physmem.avgMemAccLat 22192.69 # Average memory access latency system.physmem.avgRdBW 7.58 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 7.58 # Average consumed read bandwidth in MB/s @@ -233,8 +233,8 @@ system.physmem.readRowHits 4578 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 92.71 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 8438838.70 # Average gap between requests -system.membus.throughput 7583969 # Throughput (bytes/s) +system.physmem.avgGap 8439007.90 # Average gap between requests +system.membus.throughput 7583816 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 3216 # Transaction distribution system.membus.trans_dist::ReadResp 3216 # Transaction distribution system.membus.trans_dist::ReadExReq 1722 # Transaction distribution @@ -245,39 +245,39 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 316032 system.membus.tot_pkt_size 316032 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 316032 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 5804000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 5784500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 46092250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 46068500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.branchPred.lookups 13412467 # Number of BP lookups -system.cpu.branchPred.condPredicted 9649930 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 4269365 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 7424694 # Number of BTB lookups -system.cpu.branchPred.BTBHits 3768519 # Number of BTB hits +system.cpu.branchPred.lookups 13412627 # Number of BP lookups +system.cpu.branchPred.condPredicted 9650146 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4269214 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 7424479 # Number of BTB lookups +system.cpu.branchPred.BTBHits 3768497 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 50.756556 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 50.757730 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1029619 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 126 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 19996249 # DTB read hits +system.cpu.dtb.read_hits 19996270 # DTB read hits system.cpu.dtb.read_misses 10 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 19996259 # DTB read accesses -system.cpu.dtb.write_hits 6501862 # DTB write hits +system.cpu.dtb.read_accesses 19996280 # DTB read accesses +system.cpu.dtb.write_hits 6501863 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6501885 # DTB write accesses -system.cpu.dtb.data_hits 26498111 # DTB hits +system.cpu.dtb.write_accesses 6501886 # DTB write accesses +system.cpu.dtb.data_hits 26498133 # DTB hits system.cpu.dtb.data_misses 33 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 26498144 # DTB accesses -system.cpu.itb.fetch_hits 9957259 # ITB hits +system.cpu.dtb.data_accesses 26498166 # DTB accesses +system.cpu.itb.fetch_hits 9956949 # ITB hits system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 9957308 # ITB accesses +system.cpu.itb.fetch_accesses 9956998 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -291,34 +291,34 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 83342117 # number of cpu cycles simulated +system.cpu.numCycles 83343791 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 5905707 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 7506760 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 73570716 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 5905662 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 7506965 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 73570550 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 136146188 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 2206130 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 136146022 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 2206131 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 8058018 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 38521724 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 26722400 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 3469281 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 799226 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4268507 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 5972195 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 41.681781 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 57404114 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 8058019 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 38521866 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 26722393 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 3469296 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 799060 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4268356 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 5972346 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 41.680307 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 57404028 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 458253 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 82971475 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 82970405 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 10802 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7733735 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 75608382 # Number of cycles cpu stages are processed. -system.cpu.activity 90.720496 # Percentage of cycles cpu is active +system.cpu.timesIdled 10389 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7736037 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 75607754 # Number of cycles cpu stages are processed. +system.cpu.activity 90.717920 # Percentage of cycles cpu is active system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed @@ -330,72 +330,72 @@ system.cpu.committedInsts 91903056 # Nu system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) -system.cpu.cpi 0.906848 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.906866 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.906848 # CPI: Total CPI of All Threads -system.cpu.ipc 1.102720 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.906866 # CPI: Total CPI of All Threads +system.cpu.ipc 1.102698 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.102720 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 27661043 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 55681074 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 66.810247 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 34090230 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 49251887 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 59.096035 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33490685 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 49851432 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 59.815414 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65315589 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 18026528 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.629554 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 29482268 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 53859849 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.625007 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 7633 # number of replacements -system.cpu.icache.tagsinuse 1492.272065 # Cycle average of tags in use -system.cpu.icache.total_refs 9945862 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 9518 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1044.952931 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1492.272065 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.728648 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.728648 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 9945862 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 9945862 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 9945862 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 9945862 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 9945862 # number of overall hits -system.cpu.icache.overall_hits::total 9945862 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11397 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11397 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11397 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11397 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11397 # number of overall misses -system.cpu.icache.overall_misses::total 11397 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 317452000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 317452000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 317452000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 317452000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 317452000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 317452000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9957259 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9957259 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9957259 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9957259 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9957259 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9957259 # number of overall (read+write) accesses +system.cpu.ipc_total 1.102698 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 27663446 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 55680345 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 66.808030 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 34092107 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 49251684 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 59.094605 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 33492443 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 49851348 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 59.814111 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65317278 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 18026513 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.629101 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 29484037 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 53859754 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.623595 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.tags.replacements 7635 # number of replacements +system.cpu.icache.tags.tagsinuse 1492.268238 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 9945551 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 9520 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1044.700735 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1492.268238 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.728647 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.728647 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 9945551 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 9945551 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 9945551 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 9945551 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 9945551 # number of overall hits +system.cpu.icache.overall_hits::total 9945551 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11398 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11398 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11398 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11398 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11398 # number of overall misses +system.cpu.icache.overall_misses::total 11398 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 318279500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 318279500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 318279500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 318279500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 318279500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 318279500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9956949 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9956949 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9956949 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9956949 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9956949 # 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average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27853.996666 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27853.996666 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27924.153360 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27924.153360 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27924.153360 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27924.153360 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27924.153360 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27924.153360 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -404,83 +404,83 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 7 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1879 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1879 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1879 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1879 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1879 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1879 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9518 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 9518 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 9518 # 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number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 259449500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 259449500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 259449500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 259449500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000956 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000956 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27326.223997 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27326.223997 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27326.223997 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 27326.223997 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27326.223997 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 27326.223997 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27253.098739 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27253.098739 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27253.098739 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 27253.098739 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27253.098739 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 27253.098739 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 18196610 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 9993 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 9993 # Transaction distribution +system.cpu.toL2Bus.throughput 18199316 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 9995 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 9995 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1748 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 19036 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 19040 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4553 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 23589 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 609152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 23593 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 609280 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 149120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 758272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 758272 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size 758400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 758400 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 6031000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 6032000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 14277000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 14868500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3334500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3600000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2189.717368 # Cycle average of tags in use -system.cpu.l2cache.total_refs 6791 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.069165 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.843612 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1820.867359 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 351.006398 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.055568 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.010712 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.066825 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 6724 # number of ReadReq hits +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2189.714615 # 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number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 6726 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits -system.cpu.l2cache.overall_hits::total 6803 # number of overall hits +system.cpu.l2cache.overall_hits::total 6805 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 2794 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 3216 # number of ReadReq misses @@ -492,52 +492,52 @@ system.cpu.l2cache.demand_misses::total 4938 # nu system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4938 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 183057000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30189500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 213246500 # 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number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 9993 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 9995 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 9518 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 9520 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 11741 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 9518 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 11743 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 9520 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 11741 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.293549 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 11743 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.293487 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.321825 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.321761 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.985126 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.293549 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.293487 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.420577 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293549 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.420506 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293487 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.420577 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65517.895490 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71539.099526 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 66307.991294 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66602.206736 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66602.206736 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65517.895490 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67573.927239 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66410.591333 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65517.895490 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67573.927239 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66410.591333 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.420506 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65279.885469 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70949.052133 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 66023.787313 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66901.858304 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66901.858304 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65279.885469 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67698.460821 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 66329.991900 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65279.885469 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67698.460821 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66329.991900 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -557,73 +557,73 @@ system.cpu.l2cache.demand_mshr_misses::total 4938 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 148372000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24939500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 173311500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 93717750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 93717750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 148372000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 118657250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 267029250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 148372000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 118657250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 267029250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293549 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 147140500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24615500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 171756000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 94045000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 94045000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 147140500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 118660500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 265801000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 147140500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 118660500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 265801000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321825 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321761 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.293549 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.420577 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293549 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.420506 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.420577 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53103.793844 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59098.341232 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53890.391791 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54423.780488 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54423.780488 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53103.793844 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55343.866604 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54076.397327 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53103.793844 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55343.866604 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54076.397327 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.420506 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52663.027917 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58330.568720 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53406.716418 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54613.821138 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54613.821138 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52663.027917 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55345.382463 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53827.663021 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52663.027917 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55345.382463 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53827.663021 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1441.455577 # Cycle average of tags in use -system.cpu.dcache.total_refs 26488507 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11915.657670 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1441.455577 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.351918 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.351918 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 157 # number of replacements +system.cpu.dcache.tags.tagsinuse 1441.455272 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26488508 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11915.658120 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1441.455272 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.351918 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.351918 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 19995622 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 19995622 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492885 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492885 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26488507 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26488507 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26488507 # number of overall hits -system.cpu.dcache.overall_hits::total 26488507 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492886 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492886 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26488508 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26488508 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26488508 # number of overall hits +system.cpu.dcache.overall_hits::total 26488508 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 576 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 576 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8218 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8218 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 8794 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 8794 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 8794 # number of overall misses -system.cpu.dcache.overall_misses::total 8794 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 38984000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 38984000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 463524000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 463524000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 502508000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 502508000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 502508000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 502508000 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 8217 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8217 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 8793 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8793 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 8793 # number of overall misses +system.cpu.dcache.overall_misses::total 8793 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 38176750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 38176750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 468176250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 468176250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 506353000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 506353000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 506353000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 506353000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -640,19 +640,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000332 system.cpu.dcache.demand_miss_rate::total 0.000332 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000332 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000332 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67680.555556 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 67680.555556 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56403.504502 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56403.504502 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 57142.142370 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 57142.142370 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 57142.142370 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 57142.142370 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21765 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66279.079861 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66279.079861 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56976.542534 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56976.542534 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 57585.920619 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 57585.920619 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 57585.920619 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 57585.920619 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 22475 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 825 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 847 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.381818 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.534829 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -660,12 +660,12 @@ system.cpu.dcache.writebacks::writebacks 107 # nu system.cpu.dcache.writebacks::total 107 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 101 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6470 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6470 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6571 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6571 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6571 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6571 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6469 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6469 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6570 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6570 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6570 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6570 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses @@ -674,14 +674,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31213000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 31213000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116706500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 116706500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 147919500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 147919500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 147919500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 147919500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30964000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30964000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 117222500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 117222500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 148186500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 148186500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 148186500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 148186500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -690,14 +690,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65711.578947 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65711.578947 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66765.732265 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66765.732265 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66540.485830 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66540.485830 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66540.485830 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66540.485830 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65187.368421 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65187.368421 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67060.926773 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67060.926773 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66660.593792 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66660.593792 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66660.593792 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66660.593792 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 183d79059..b5b638e61 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,51 +1,51 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023497 # Number of seconds simulated -sim_ticks 23497413000 # Number of ticks simulated -final_tick 23497413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023492 # Number of seconds simulated +sim_ticks 23492267500 # Number of ticks simulated +final_tick 23492267500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 127551 # Simulator instruction rate (inst/s) -host_op_rate 127551 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35603882 # Simulator tick rate (ticks/s) -host_mem_usage 231880 # Number of bytes of host memory used -host_seconds 659.97 # Real time elapsed on the host +host_inst_rate 122951 # Simulator instruction rate (inst/s) +host_op_rate 122951 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34312389 # Simulator tick rate (ticks/s) +host_mem_usage 231868 # Number of bytes of host memory used +host_seconds 684.66 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 195392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138624 # Number of bytes read from this memory -system.physmem.bytes_read::total 334016 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 195392 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 195392 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3053 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2166 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5219 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8315469 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5899543 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14215012 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8315469 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8315469 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8315469 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5899543 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 14215012 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5219 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 195904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138560 # Number of bytes read from this memory +system.physmem.bytes_read::total 334464 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 195904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 195904 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3061 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2165 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5226 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8339084 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5898111 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14237195 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8339084 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8339084 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8339084 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5898111 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 14237195 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5226 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 5219 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 334016 # Total number of bytes read from memory +system.physmem.cpureqs 5226 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 334464 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 334016 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 334464 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 469 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 291 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 302 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 519 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 221 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 224 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 218 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 288 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 301 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 520 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 220 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 227 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 220 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 289 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 237 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 278 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 280 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 248 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 252 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 398 # Track reads on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 23497287000 # Total gap between requests +system.physmem.totGap 23492140500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 5219 # Categorize read packet sizes +system.physmem.readPktSize::6 5226 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,12 +85,12 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 3287 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 507 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 77 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1366 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 506 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 78 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -149,139 +149,135 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 418 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 779.330144 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 283.808293 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1370.086091 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 124 29.67% 29.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 51 12.20% 41.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 42 10.05% 51.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 20 4.78% 56.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 15 3.59% 60.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 19 4.55% 64.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 7 1.67% 66.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 9 2.15% 68.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 7 1.67% 70.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 3 0.72% 71.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 8 1.91% 72.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 7 1.67% 74.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 6 1.44% 76.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 5 1.20% 77.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 4 0.96% 78.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 1 0.24% 78.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 6 1.44% 79.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 3 0.72% 80.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 4 0.96% 81.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 3 0.72% 82.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 5 1.20% 83.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 3 0.72% 84.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 5 1.20% 85.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 3 0.72% 86.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 3 0.72% 86.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 3 0.72% 87.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 1 0.24% 87.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 3 0.72% 88.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 1 0.24% 88.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 3 0.72% 89.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 2 0.48% 89.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 2 0.48% 90.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 1 0.24% 90.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 2 0.48% 91.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.24% 91.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 2 0.48% 91.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 1 0.24% 92.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 1 0.24% 92.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 1 0.24% 92.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.24% 92.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 1 0.24% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.24% 93.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 1 0.24% 93.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 1 0.24% 93.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 1 0.24% 94.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 2 0.48% 94.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 1 0.24% 94.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 2 0.48% 95.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.24% 95.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 1 0.24% 95.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 1 0.24% 95.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 1 0.24% 96.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 2 0.48% 96.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 1 0.24% 96.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 1 0.24% 97.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 1 0.24% 97.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 1 0.24% 97.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.24% 97.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 1 0.24% 98.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 1 0.24% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 1 0.24% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 416 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 780.923077 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 283.989164 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1375.157964 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 120 28.85% 28.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 59 14.18% 43.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 37 8.89% 51.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 19 4.57% 56.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 16 3.85% 60.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 20 4.81% 65.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 8 1.92% 67.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 8 1.92% 68.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 5 1.20% 70.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 5 1.20% 71.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 6 1.44% 72.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 8 1.92% 74.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 6 1.44% 76.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 4 0.96% 77.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 4 0.96% 78.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 2 0.48% 78.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 5 1.20% 79.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 3 0.72% 80.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 4 0.96% 81.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 3 0.72% 82.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 4 0.96% 83.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 3 0.72% 83.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 5 1.20% 85.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 3 0.72% 85.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 4 0.96% 86.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 3 0.72% 87.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 1 0.24% 87.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 3 0.72% 88.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 1 0.24% 88.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 4 0.96% 89.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 2 0.48% 90.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 2 0.48% 90.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 1 0.24% 90.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 1 0.24% 91.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 2 0.48% 91.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 1 0.24% 91.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 1 0.24% 92.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 2 0.48% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 1 0.24% 92.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 1 0.24% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.24% 93.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 1 0.24% 93.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 1 0.24% 93.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 1 0.24% 93.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 2 0.48% 94.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 1 0.24% 94.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 2 0.48% 95.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 1 0.24% 95.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 1 0.24% 95.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 5 1.20% 96.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 1 0.24% 97.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 1 0.24% 97.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 1 0.24% 97.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 1 0.24% 97.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 1 0.24% 98.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 1 0.24% 98.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 1 0.24% 98.56% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8129 2 0.48% 99.04% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 4 0.96% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 418 # Bytes accessed per row activation -system.physmem.totQLat 22102000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 116465750 # Sum of mem lat for all requests -system.physmem.totBusLat 26095000 # Total cycles spent in databus access -system.physmem.totBankLat 68268750 # Total cycles spent in bank access -system.physmem.avgQLat 4234.91 # Average queueing delay per request -system.physmem.avgBankLat 13080.81 # Average bank access latency per request +system.physmem.bytesPerActivate::total 416 # Bytes accessed per row activation +system.physmem.totQLat 21308250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 115583250 # Sum of mem lat for all requests +system.physmem.totBusLat 26130000 # Total cycles spent in databus access +system.physmem.totBankLat 68145000 # Total cycles spent in bank access +system.physmem.avgQLat 4077.35 # Average queueing delay per request +system.physmem.avgBankLat 13039.61 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22315.72 # Average memory access latency -system.physmem.avgRdBW 14.22 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 22116.96 # Average memory access latency +system.physmem.avgRdBW 14.24 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 14.22 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 14.24 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.11 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4801 # Number of row buffer hits during reads +system.physmem.readRowHits 4810 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.99 # Row buffer hit rate for reads +system.physmem.readRowHitRate 92.04 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4502258.48 # Average gap between requests -system.membus.throughput 14215012 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 3511 # Transaction distribution -system.membus.trans_dist::ReadResp 3511 # Transaction distribution -system.membus.trans_dist::ReadExReq 1708 # Transaction distribution -system.membus.trans_dist::ReadExResp 1708 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 10438 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 10438 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 334016 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 334016 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 334016 # Total data (bytes) +system.physmem.avgGap 4495243.11 # Average gap between requests +system.membus.throughput 14237195 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3520 # Transaction distribution +system.membus.trans_dist::ReadResp 3520 # Transaction distribution +system.membus.trans_dist::ReadExReq 1706 # Transaction distribution +system.membus.trans_dist::ReadExResp 1706 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 10452 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 10452 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 334464 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 334464 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 334464 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6341000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6824500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 48807250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 49069500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.cpu.branchPred.lookups 14862551 # Number of BP lookups -system.cpu.branchPred.condPredicted 10783549 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 926034 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8413875 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6968843 # Number of BTB hits +system.cpu.branchPred.lookups 14868892 # Number of BP lookups +system.cpu.branchPred.condPredicted 10787177 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 926932 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8430316 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6969924 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 82.825607 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1469354 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3121 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 82.676901 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1469870 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3126 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 23132924 # DTB read hits -system.cpu.dtb.read_misses 192093 # DTB read misses +system.cpu.dtb.read_hits 23134581 # DTB read hits +system.cpu.dtb.read_misses 192685 # DTB read misses system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 23325017 # DTB read accesses -system.cpu.dtb.write_hits 7072345 # DTB write hits -system.cpu.dtb.write_misses 1094 # DTB write misses +system.cpu.dtb.read_accesses 23327266 # DTB read accesses +system.cpu.dtb.write_hits 7072669 # DTB write hits +system.cpu.dtb.write_misses 1128 # DTB write misses system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 7073439 # DTB write accesses -system.cpu.dtb.data_hits 30205269 # DTB hits -system.cpu.dtb.data_misses 193187 # DTB misses +system.cpu.dtb.write_accesses 7073797 # DTB write accesses +system.cpu.dtb.data_hits 30207250 # DTB hits +system.cpu.dtb.data_misses 193813 # DTB misses system.cpu.dtb.data_acv 4 # DTB access violations -system.cpu.dtb.data_accesses 30398456 # DTB accesses -system.cpu.itb.fetch_hits 14755058 # ITB hits +system.cpu.dtb.data_accesses 30401063 # DTB accesses +system.cpu.itb.fetch_hits 14756036 # ITB hits system.cpu.itb.fetch_misses 101 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14755159 # ITB accesses +system.cpu.itb.fetch_accesses 14756137 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -295,238 +291,237 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 46994827 # number of cpu cycles simulated +system.cpu.numCycles 46984536 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15489149 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 127098752 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14862551 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 8438197 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22157137 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4490975 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5583322 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 113 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2356 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 14755058 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 326188 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46762472 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.717965 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.375306 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15488073 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 127117981 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14868892 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 8439794 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22159630 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4494895 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5563054 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2312 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14756036 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 325999 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46746670 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.719295 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.375691 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24605335 52.62% 52.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2364392 5.06% 57.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1192796 2.55% 60.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1746753 3.74% 63.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2761574 5.91% 69.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1153115 2.47% 72.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1218931 2.61% 74.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 773556 1.65% 76.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10946020 23.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24587040 52.60% 52.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2365337 5.06% 57.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1191741 2.55% 60.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1747442 3.74% 63.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2760154 5.90% 69.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1154764 2.47% 72.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1218466 2.61% 74.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 772204 1.65% 76.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10949522 23.42% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46762472 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.316259 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.704526 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17321703 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4276623 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20543509 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1101986 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3518651 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2516350 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12158 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 124100512 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 31524 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3518651 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18468008 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 966877 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7668 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20476490 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3324778 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 121264521 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 82 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 403236 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2443262 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 89058236 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 157582364 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 147884300 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9698064 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 46746670 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.316464 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.705528 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17316199 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4260248 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20549941 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1098483 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3521799 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2517933 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12169 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 124122749 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 32253 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3521799 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18461305 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 962240 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7648 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20480612 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3313066 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 121283530 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 59 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 398899 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2436739 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 89066471 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 157595093 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 147895466 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9699627 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 20630875 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 727 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 718 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8817740 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 25385211 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8251770 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2611914 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 924495 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 105530247 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1715 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 96635335 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 178536 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 20879466 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15657073 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1326 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46762472 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.066515 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.875135 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 20639110 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 733 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 729 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8785388 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 25392018 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8252125 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2596537 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 925406 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 105547434 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2098 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 96644788 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 177437 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 20878127 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15672265 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1709 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46746670 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.067415 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.876261 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12166038 26.02% 26.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 9374565 20.05% 46.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8425963 18.02% 64.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6292522 13.46% 77.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4920709 10.52% 88.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2854864 6.11% 94.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1726414 3.69% 97.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 795538 1.70% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 205859 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12170136 26.03% 26.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9358863 20.02% 46.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8416132 18.00% 64.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6289434 13.45% 77.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4916374 10.52% 88.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2864607 6.13% 94.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1727461 3.70% 97.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 797242 1.71% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 206421 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46762472 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46746670 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 190796 12.16% 12.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 12.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 12.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 179 0.01% 12.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 7128 0.45% 12.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 5650 0.36% 12.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 843178 53.72% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 444699 28.33% 95.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 77939 4.97% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 188535 12.02% 12.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 12.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 12.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 207 0.01% 12.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 7191 0.46% 12.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 5653 0.36% 12.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 842893 53.74% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 446132 28.45% 95.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 77750 4.96% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58779410 60.83% 60.83% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 479944 0.50% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58781922 60.82% 60.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 479844 0.50% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2800605 2.90% 64.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115340 0.12% 64.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2387840 2.47% 66.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 311019 0.32% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 760059 0.79% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23845244 24.68% 92.60% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7155548 7.40% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2799901 2.90% 64.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115380 0.12% 64.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2387749 2.47% 66.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 311051 0.32% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 760106 0.79% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23852037 24.68% 92.60% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7156472 7.40% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 96635335 # Type of FU issued -system.cpu.iq.rate 2.056297 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1569569 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016242 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 226659120 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 117679968 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87126809 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15122127 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 8766253 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7066480 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90213613 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7991284 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1520773 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 96644788 # Type of FU issued +system.cpu.iq.rate 2.056949 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1568361 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016228 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 226659796 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 117693658 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87130802 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15122248 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 8768674 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7065649 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90221948 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7991194 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1517986 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5389013 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 18483 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34901 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1750667 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5395820 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 18680 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34810 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1751022 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10533 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1986 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10535 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1932 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3518651 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 134178 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18459 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 115772618 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 373350 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 25385211 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8251770 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1715 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3175 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 37 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34901 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 538953 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 495548 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1034501 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 95401130 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23325510 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1234205 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3521799 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 133427 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 18321 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 115791419 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 375079 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 25392018 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8252125 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2098 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2892 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 38 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 34810 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 537595 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 497018 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1034613 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 95405393 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23327731 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1239395 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10240656 # number of nop insts executed -system.cpu.iew.exec_refs 30399148 # number of memory reference insts executed -system.cpu.iew.exec_branches 12029434 # Number of branches executed -system.cpu.iew.exec_stores 7073638 # Number of stores executed -system.cpu.iew.exec_rate 2.030035 # Inst execution rate -system.cpu.iew.wb_sent 94712572 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 94193289 # cumulative count of insts written-back -system.cpu.iew.wb_producers 64506867 # num instructions producing a value -system.cpu.iew.wb_consumers 89893282 # num instructions consuming a value +system.cpu.iew.exec_nop 10241887 # number of nop insts executed +system.cpu.iew.exec_refs 30401730 # number of memory reference insts executed +system.cpu.iew.exec_branches 12031007 # Number of branches executed +system.cpu.iew.exec_stores 7073999 # Number of stores executed +system.cpu.iew.exec_rate 2.030570 # Inst execution rate +system.cpu.iew.wb_sent 94717591 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 94196451 # cumulative count of insts written-back +system.cpu.iew.wb_producers 64508240 # num instructions producing a value +system.cpu.iew.wb_consumers 89892394 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.004333 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717594 # average fanout of values written-back +system.cpu.iew.wb_rate 2.004839 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717616 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23870674 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 23889448 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 914298 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43243821 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.125230 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.743207 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 915179 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43224871 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.126161 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.744271 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16770420 38.78% 38.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9933071 22.97% 61.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4488153 10.38% 72.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2264318 5.24% 77.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1614513 3.73% 81.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1126501 2.60% 83.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 722210 1.67% 85.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 820173 1.90% 87.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5504462 12.73% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16760873 38.78% 38.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9929358 22.97% 61.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4485318 10.38% 72.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2262602 5.23% 77.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1610546 3.73% 81.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1125217 2.60% 83.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 721883 1.67% 85.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 816904 1.89% 87.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5512170 12.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43243821 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43224871 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -537,212 +532,212 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5504462 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5512170 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 153512048 # The number of ROB reads -system.cpu.rob.rob_writes 235089898 # The number of ROB writes -system.cpu.timesIdled 5458 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 232355 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 153504164 # The number of ROB reads +system.cpu.rob.rob_writes 235130535 # The number of ROB writes +system.cpu.timesIdled 5262 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 237866 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.558268 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.558268 # CPI: Total CPI of All Threads -system.cpu.ipc 1.791255 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.791255 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 129137938 # number of integer regfile reads -system.cpu.int_regfile_writes 70566847 # number of integer regfile writes -system.cpu.fp_regfile_reads 6190616 # number of floating regfile reads -system.cpu.fp_regfile_writes 6048237 # number of floating regfile writes -system.cpu.misc_regfile_reads 714522 # number of misc regfile reads +system.cpu.cpi 0.558146 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.558146 # CPI: Total CPI of All Threads +system.cpu.ipc 1.791647 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.791647 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 129142322 # number of integer regfile reads +system.cpu.int_regfile_writes 70569523 # number of integer regfile writes +system.cpu.fp_regfile_reads 6189856 # number of floating regfile reads +system.cpu.fp_regfile_writes 6047601 # number of floating regfile writes +system.cpu.misc_regfile_reads 714537 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 38347030 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 12236 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 12236 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 109 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1734 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1734 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 23446 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4603 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 28049 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 750272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 150784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 901056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 901056 # Total data (bytes) +system.cpu.toL2Bus.throughput 37717943 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 12006 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 12006 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 108 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1731 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1731 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 22984 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4598 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 27582 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 735488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 150592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 886080 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 886080 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 7148500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 7030500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 17584500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 17871250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3370500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3590750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.replacements 9791 # number of replacements -system.cpu.icache.tagsinuse 1591.709559 # Cycle average of tags in use -system.cpu.icache.total_refs 14740526 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 11723 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1257.402201 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1591.709559 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.777202 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.777202 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14740526 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14740526 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14740526 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14740526 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14740526 # number of overall hits -system.cpu.icache.overall_hits::total 14740526 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14531 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14531 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14531 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14531 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14531 # number of overall misses -system.cpu.icache.overall_misses::total 14531 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 399004500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 399004500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 399004500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 399004500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 399004500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 399004500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14755057 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14755057 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14755057 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14755057 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14755057 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14755057 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000985 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000985 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000985 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000985 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000985 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000985 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27458.846604 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27458.846604 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27458.846604 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27458.846604 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27458.846604 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27458.846604 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 306 # number of cycles access was blocked +system.cpu.icache.tags.replacements 9559 # number of replacements +system.cpu.icache.tags.tagsinuse 1595.799290 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 14741729 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 11492 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1282.781848 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1595.799290 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.779199 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.779199 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14741729 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14741729 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14741729 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14741729 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14741729 # number of overall hits +system.cpu.icache.overall_hits::total 14741729 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14307 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14307 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14307 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14307 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14307 # number of overall misses +system.cpu.icache.overall_misses::total 14307 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 399491250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 399491250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 399491250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 399491250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 399491250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 399491250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14756036 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14756036 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14756036 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14756036 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14756036 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14756036 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000970 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000970 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000970 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000970 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000970 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000970 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27922.782554 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27922.782554 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27922.782554 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27922.782554 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27922.782554 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27922.782554 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 236 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 43.714286 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 39.333333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2808 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2808 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2808 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2808 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2808 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2808 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11723 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 11723 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 11723 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 11723 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 11723 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 11723 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 297568500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 297568500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 297568500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 297568500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 297568500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 297568500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000795 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000795 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000795 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000795 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000795 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000795 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 25383.306321 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 25383.306321 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 25383.306321 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 25383.306321 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 25383.306321 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 25383.306321 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2815 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2815 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2815 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2815 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2815 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2815 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11492 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 11492 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 11492 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 11492 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 11492 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 11492 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 295512250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 295512250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 295512250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 295512250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 295512250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 295512250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000779 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000779 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000779 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000779 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000779 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000779 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 25714.605813 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 25714.605813 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 25714.605813 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 25714.605813 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 25714.605813 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 25714.605813 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2401.280211 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8740 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3578 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.442705 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.673510 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2001.216545 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 382.390156 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000539 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.061072 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.011670 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.073281 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 8670 # number of ReadReq hits +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2404.485668 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8502 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3587 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.370226 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 17.679636 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.666457 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 379.139575 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000540 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061269 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.011570 # 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number of replacements -system.cpu.dcache.tagsinuse 1461.104213 # Cycle average of tags in use -system.cpu.dcache.total_refs 28091806 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2247 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12501.916333 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1461.104213 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.356715 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.356715 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 21598707 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21598707 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492881 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492881 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 218 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 218 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28091588 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28091588 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28091588 # number of overall hits -system.cpu.dcache.overall_hits::total 28091588 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 971 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 971 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8222 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8222 # number of WriteReq misses +system.cpu.dcache.tags.replacements 158 # number of replacements +system.cpu.dcache.tags.tagsinuse 1457.925933 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28096273 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2245 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12515.043653 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1457.925933 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.355939 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.355939 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 21603146 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21603146 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492891 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492891 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28096037 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28096037 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28096037 # number of overall hits +system.cpu.dcache.overall_hits::total 28096037 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 988 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 988 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8212 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8212 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9193 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9193 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9193 # number of overall misses -system.cpu.dcache.overall_misses::total 9193 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 59585500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 59585500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 475543278 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 475543278 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 92000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 535128778 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 535128778 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 535128778 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 535128778 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21599678 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21599678 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9200 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9200 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9200 # number of overall misses +system.cpu.dcache.overall_misses::total 9200 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 60150500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 60150500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 476870547 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 476870547 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 537021047 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 537021047 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 537021047 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 537021047 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21604134 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21604134 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 219 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 219 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28100781 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28100781 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28100781 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28100781 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001265 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001265 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004566 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004566 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 237 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 237 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28105237 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28105237 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28105237 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28105237 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001263 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001263 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004219 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004219 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000327 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000327 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000327 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000327 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61365.087539 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61365.087539 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57837.907808 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 57837.907808 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 58210.462091 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 58210.462091 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 58210.462091 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 58210.462091 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21885 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60881.072874 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60881.072874 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58069.964321 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 58069.964321 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 58371.852935 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 58371.852935 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 58371.852935 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 58371.852935 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21919 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 353 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 336 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 61.997167 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 65.235119 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 109 # number of writebacks -system.cpu.dcache.writebacks::total 109 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 459 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 459 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6488 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6488 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6947 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6947 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6947 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6947 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 512 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 512 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1734 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1734 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 108 # number of writebacks +system.cpu.dcache.writebacks::total 108 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 475 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 475 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6481 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6481 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6956 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6956 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6956 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6956 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 513 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 513 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1731 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1731 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2246 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2246 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2246 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2246 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34660000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 34660000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116538997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 116538997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 151198997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 151198997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 151198997 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 151198997 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2244 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2244 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2244 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2244 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 35017250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 35017250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116268497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 116268497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 151285747 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 151285747 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 151285747 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 151285747 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004566 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004566 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004219 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004219 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67695.312500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67695.312500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67208.187428 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67208.187428 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67319.232858 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67319.232858 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67319.232858 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67319.232858 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68259.746589 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68259.746589 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67168.398036 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67168.398036 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67417.890820 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67417.890820 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67417.890820 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67417.890820 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index b57d95ab0..847011ac3 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -97,15 +97,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 237458632 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 6681 # number of replacements -system.cpu.icache.tagsinuse 1418.052773 # Cycle average of tags in use -system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 10798.423032 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1418.052773 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.692409 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.692409 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 6681 # number of replacements +system.cpu.icache.tags.tagsinuse 1418.052773 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 91894580 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8510 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10798.423032 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1418.052773 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.692409 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.692409 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 91894580 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 91894580 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 91894580 # number of demand (read+write) hits @@ -175,19 +175,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 23935.605170 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2074.070560 # Cycle average of tags in use -system.cpu.l2cache.total_refs 5956 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3109 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 1.915729 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.795178 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1705.018003 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 351.257379 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.052033 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.010720 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.063296 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2074.070560 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5956 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3109 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.915729 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 17.795178 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1705.018003 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 351.257379 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052033 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.010720 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.063296 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 5889 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 5942 # number of ReadReq hits @@ -311,15 +311,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1442.043392 # Cycle average of tags in use -system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1442.043392 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.352061 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 157 # number of replacements +system.cpu.dcache.tags.tagsinuse 1442.043392 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26495078 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11918.613585 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1442.043392 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.352061 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index e580bbf9c..191849c1b 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.074184 # Number of seconds simulated -sim_ticks 74184344000 # Number of ticks simulated -final_tick 74184344000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.074201 # Number of seconds simulated +sim_ticks 74201024500 # Number of ticks simulated +final_tick 74201024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 120810 # Simulator instruction rate (inst/s) -host_op_rate 132276 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52014122 # Simulator tick rate (ticks/s) -host_mem_usage 249648 # Number of bytes of host memory used -host_seconds 1426.23 # Real time elapsed on the host +host_inst_rate 81530 # Simulator instruction rate (inst/s) +host_op_rate 89268 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35110326 # Simulator tick rate (ticks/s) +host_mem_usage 249620 # Number of bytes of host memory used +host_seconds 2113.37 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 188656503 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 131136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 111808 # Number of bytes read from this memory -system.physmem.bytes_read::total 242944 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 131136 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 131136 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2049 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1747 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3796 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1767705 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1507164 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3274869 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1767705 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1767705 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1767705 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1507164 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3274869 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3796 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 131328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 111872 # Number of bytes read from this memory +system.physmem.bytes_read::total 243200 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 131328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 131328 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2052 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1748 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3800 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1769895 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1507688 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3277583 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1769895 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1769895 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1769895 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1507688 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3277583 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3801 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 3798 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 242944 # Total number of bytes read from memory +system.physmem.cpureqs 3803 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 243200 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 242944 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 243200 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 309 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 308 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 215 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 134 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 309 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 297 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 308 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 298 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 300 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 262 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 217 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 261 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 216 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 246 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 213 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 288 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 193 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 189 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 206 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 219 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 199 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 215 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 289 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 194 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 191 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 208 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 218 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 200 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 74184191000 # Total gap between requests +system.physmem.totGap 74201006000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 3796 # Categorize read packet sizes +system.physmem.readPktSize::6 3801 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,10 +85,10 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 2837 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 786 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 131 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2829 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 792 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 38 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -149,114 +149,114 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 376 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 621.446809 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 226.720612 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1211.628472 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 135 35.90% 35.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 51 13.56% 49.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 26 6.91% 56.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 29 7.71% 64.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 14 3.72% 67.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 14 3.72% 71.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 6 1.60% 73.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 5 1.33% 74.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 7 1.86% 76.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 7 1.86% 78.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 5 1.33% 79.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 6 1.60% 81.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 1 0.27% 81.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 5 1.33% 82.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 3 0.80% 83.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 4 1.06% 84.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 2 0.53% 85.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 3 0.80% 85.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 3 0.80% 86.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 1 0.27% 86.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 1 0.27% 87.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 5 1.33% 88.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 2 0.53% 89.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 1 0.27% 89.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 3 0.80% 90.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 3 0.80% 90.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 1 0.27% 91.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 1 0.27% 91.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 1 0.27% 91.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 1 0.27% 92.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 2 0.53% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 1 0.27% 92.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 1 0.27% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.27% 93.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.27% 93.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.27% 93.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 1 0.27% 94.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.27% 94.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 1 0.27% 94.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.27% 94.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.27% 95.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 1 0.27% 95.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.27% 95.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 3 0.80% 96.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.27% 96.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.27% 97.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 1 0.27% 97.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 1 0.27% 97.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 1 0.27% 97.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 1 0.27% 98.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.27% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 1 0.27% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 1 0.27% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 1 0.27% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 1 0.27% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 2 0.53% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 376 # Bytes accessed per row activation -system.physmem.totQLat 13471250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 86310000 # Sum of mem lat for all requests -system.physmem.totBusLat 18980000 # Total cycles spent in databus access -system.physmem.totBankLat 53858750 # Total cycles spent in bank access -system.physmem.avgQLat 3548.80 # Average queueing delay per request -system.physmem.avgBankLat 14188.29 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 389 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 616.966581 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 221.267348 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1216.553816 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 139 35.73% 35.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 59 15.17% 50.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 33 8.48% 59.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 24 6.17% 65.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 15 3.86% 69.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 13 3.34% 72.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 4 1.03% 73.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 7 1.80% 75.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 5 1.29% 76.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 8 2.06% 78.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 4 1.03% 79.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 4 1.03% 80.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 3 0.77% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 3 0.77% 82.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 5 1.29% 83.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 4 1.03% 84.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 4 1.03% 85.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 1 0.26% 86.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 1 0.26% 86.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 3 0.77% 87.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 3 0.77% 87.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 3 0.77% 88.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 2 0.51% 89.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 1 0.26% 89.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 3 0.77% 90.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 3 0.77% 91.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 1 0.26% 91.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 1 0.26% 91.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 1 0.26% 91.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 1 0.26% 92.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 2 0.51% 92.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 1 0.26% 92.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 1 0.26% 93.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 1 0.26% 93.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 1 0.26% 93.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 1 0.26% 93.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 1 0.26% 94.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 1 0.26% 94.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.26% 94.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 1 0.26% 94.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 1 0.26% 95.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 1 0.26% 95.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 4 1.03% 96.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 1 0.26% 96.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 1 0.26% 96.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 1 0.26% 97.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 1 0.26% 97.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 1 0.26% 97.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 1 0.26% 97.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 1 0.26% 98.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 1 0.26% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 1 0.26% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 1 0.26% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 1 0.26% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 1 0.26% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 2 0.51% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 389 # Bytes accessed per row activation +system.physmem.totQLat 12962000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 86183250 # Sum of mem lat for all requests +system.physmem.totBusLat 19005000 # Total cycles spent in databus access +system.physmem.totBankLat 54216250 # Total cycles spent in bank access +system.physmem.avgQLat 3410.16 # Average queueing delay per request +system.physmem.avgBankLat 14263.68 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22737.09 # Average memory access latency -system.physmem.avgRdBW 3.27 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 22673.84 # Average memory access latency +system.physmem.avgRdBW 3.28 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.27 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 3.28 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 3420 # Number of row buffer hits during reads +system.physmem.readRowHits 3412 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.09 # Row buffer hit rate for reads +system.physmem.readRowHitRate 89.77 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19542726.82 # Average gap between requests -system.membus.throughput 3274869 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 2721 # Transaction distribution -system.membus.trans_dist::ReadResp 2721 # Transaction distribution +system.physmem.avgGap 19521443.30 # Average gap between requests +system.membus.throughput 3277583 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 2726 # Transaction distribution +system.membus.trans_dist::ReadResp 2725 # Transaction distribution system.membus.trans_dist::UpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution system.membus.trans_dist::ReadExReq 1075 # Transaction distribution system.membus.trans_dist::ReadExResp 1075 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 7596 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 7596 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 242944 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 242944 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 242944 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side 7605 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 7605 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 243200 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 243200 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 243200 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 4823500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4684500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 35740248 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 35707998 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 94757540 # Number of BP lookups -system.cpu.branchPred.condPredicted 74764818 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6278340 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 44654246 # Number of BTB lookups -system.cpu.branchPred.BTBHits 43033777 # Number of BTB hits +system.cpu.branchPred.lookups 94803777 # Number of BP lookups +system.cpu.branchPred.condPredicted 74793629 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6279390 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 44652033 # Number of BTB lookups +system.cpu.branchPred.BTBHits 43049215 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 96.371075 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 4354951 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 88346 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 96.410425 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 4355984 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 88442 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -300,240 +300,240 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 148368689 # number of cpu cycles simulated +system.cpu.numCycles 148402050 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 39647823 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 380146219 # Number of instructions fetch has processed -system.cpu.fetch.Branches 94757540 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 47388728 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80358140 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 27268312 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7203967 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 39645282 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 380210735 # Number of instructions fetch has processed +system.cpu.fetch.Branches 94803777 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 47405199 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80366135 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 27283939 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7211893 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 5523 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 5835 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 69 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 36843987 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1833209 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 148189615 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.802214 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.153150 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 74 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 36839707 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1829204 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 148218142 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.802317 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.153165 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68000764 45.89% 45.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5268021 3.55% 49.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10540392 7.11% 56.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10285161 6.94% 63.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8646262 5.83% 69.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6545573 4.42% 73.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6244018 4.21% 77.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7997629 5.40% 83.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 24661795 16.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68020669 45.89% 45.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5263809 3.55% 49.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10529342 7.10% 56.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10284383 6.94% 63.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8663442 5.85% 69.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6544357 4.42% 73.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6237651 4.21% 77.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8018779 5.41% 83.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 24655710 16.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 148189615 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.638663 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.562173 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45498061 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5874830 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74793705 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1202536 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 20820483 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14321847 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 164416 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 392715815 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 749819 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 20820483 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 50886064 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 722985 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 600307 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 70546117 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4613659 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 371260855 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 69 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 344235 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3657023 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 27 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 631666093 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1581493948 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1564155420 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 17338528 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 148218142 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.638831 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.562032 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45496346 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5881053 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74801402 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1203851 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 20835490 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14335605 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 164633 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 392823460 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 736203 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 20835490 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50883815 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 724795 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 600466 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 70555670 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4617906 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 371356593 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 28 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 342994 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3662384 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 29 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 631760398 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1581883462 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1564582781 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 17300681 # Number of floating rename lookups system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 333621954 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25182 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25179 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13028807 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 42981884 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16417977 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5680787 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3667947 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 329134626 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.UndoneMaps 333716259 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 25188 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 25185 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13032916 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 43019038 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16425001 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5693552 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3686945 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 329243417 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 47203 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 249422621 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 787073 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 139456652 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 361881130 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 249464214 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 795417 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 139561180 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 362246737 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1987 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 148189615 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.683132 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.761818 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 148218142 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.683088 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.761802 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56042296 37.82% 37.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 22626121 15.27% 53.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 24808060 16.74% 69.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20320875 13.71% 83.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12548887 8.47% 92.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6516147 4.40% 96.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4031410 2.72% 99.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1113540 0.75% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 182279 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56048230 37.81% 37.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 22642926 15.28% 53.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24814212 16.74% 69.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20312337 13.70% 83.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12552656 8.47% 92.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6518158 4.40% 96.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4033272 2.72% 99.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1116001 0.75% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 180350 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 148189615 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 148218142 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 962595 38.42% 38.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5594 0.22% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 107 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 48 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1164588 46.49% 85.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 372359 14.86% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 965237 38.47% 38.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5595 0.22% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 98 0.00% 38.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 50 0.00% 38.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1168121 46.56% 85.25% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 370007 14.75% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 194884583 78.13% 78.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 979638 0.39% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33073 0.01% 78.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 164452 0.07% 78.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 254844 0.10% 78.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76427 0.03% 78.74% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 465912 0.19% 78.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206449 0.08% 79.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71875 0.03% 79.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 323 0.00% 79.04% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 38337954 15.37% 94.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13947091 5.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 194903493 78.13% 78.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 979289 0.39% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33083 0.01% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 164442 0.07% 78.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 254821 0.10% 78.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76413 0.03% 78.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 465720 0.19% 78.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206380 0.08% 79.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71858 0.03% 79.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 79.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 38359883 15.38% 94.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13948512 5.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 249422621 # Type of FU issued -system.cpu.iq.rate 1.681100 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2505291 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010044 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 646588556 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 466464832 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237860517 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3738665 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2192143 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1842020 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 250052019 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1875893 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2007355 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 249464214 # Type of FU issued +system.cpu.iq.rate 1.681002 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2509108 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010058 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 646714008 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 466681926 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237887502 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3737087 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2188015 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1841410 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 250098110 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1875212 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2005238 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13132400 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11727 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18993 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3773343 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13169554 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11470 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18663 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3780367 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 13 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 104 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 11 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 113 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 20820483 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 18849 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 902 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 329198829 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 786805 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 42981884 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16417977 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 20835490 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 18710 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 879 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 329307607 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 785363 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 43019038 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16425001 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 24795 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 191 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 274 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18993 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3888167 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3760327 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7648494 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 242926605 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 36835264 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6496016 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 182 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 275 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18663 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3889158 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3759638 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7648796 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 242968769 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 36856935 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6495445 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 17000 # number of nop insts executed -system.cpu.iew.exec_refs 50481074 # number of memory reference insts executed -system.cpu.iew.exec_branches 53424163 # Number of branches executed -system.cpu.iew.exec_stores 13645810 # Number of stores executed -system.cpu.iew.exec_rate 1.637317 # Inst execution rate -system.cpu.iew.wb_sent 240758455 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 239702537 # cumulative count of insts written-back -system.cpu.iew.wb_producers 148455856 # num instructions producing a value -system.cpu.iew.wb_consumers 267256641 # num instructions consuming a value +system.cpu.iew.exec_nop 16987 # number of nop insts executed +system.cpu.iew.exec_refs 50502724 # number of memory reference insts executed +system.cpu.iew.exec_branches 53433142 # Number of branches executed +system.cpu.iew.exec_stores 13645789 # Number of stores executed +system.cpu.iew.exec_rate 1.637233 # Inst execution rate +system.cpu.iew.wb_sent 240789077 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 239728912 # cumulative count of insts written-back +system.cpu.iew.wb_producers 148477198 # num instructions producing a value +system.cpu.iew.wb_consumers 267296630 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.615587 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.555481 # average fanout of values written-back +system.cpu.iew.wb_rate 1.615402 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.555477 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 140527929 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 140636703 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6124743 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 127369132 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.481292 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.186316 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6125970 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 127382652 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.481135 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.185870 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 57689921 45.29% 45.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 31670367 24.87% 70.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13785643 10.82% 80.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7636266 6.00% 86.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4374586 3.43% 90.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1321093 1.04% 91.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1699680 1.33% 92.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1314057 1.03% 93.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7877519 6.18% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 57681624 45.28% 45.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 31696418 24.88% 70.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13781439 10.82% 80.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7634613 5.99% 86.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4380226 3.44% 90.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1319827 1.04% 91.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1706186 1.34% 92.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1307951 1.03% 93.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7874368 6.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 127369132 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 127382652 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317409 # Number of instructions committed system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -544,220 +544,220 @@ system.cpu.commit.branches 40300311 # Nu system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. system.cpu.commit.int_insts 150106217 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 7877519 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 7874368 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 448685232 # The number of ROB reads -system.cpu.rob.rob_writes 679327064 # The number of ROB writes -system.cpu.timesIdled 2810 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 179074 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 448810677 # The number of ROB reads +system.cpu.rob.rob_writes 679560182 # The number of ROB writes +system.cpu.timesIdled 2800 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 183908 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303021 # Number of Instructions Simulated system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated -system.cpu.cpi 0.861092 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.861092 # CPI: Total CPI of All Threads -system.cpu.ipc 1.161317 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.161317 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1079239284 # number of integer regfile reads -system.cpu.int_regfile_writes 384835773 # number of integer regfile writes -system.cpu.fp_regfile_reads 2913699 # number of floating regfile reads -system.cpu.fp_regfile_writes 2498274 # number of floating regfile writes -system.cpu.misc_regfile_reads 54487026 # number of misc regfile reads +system.cpu.cpi 0.861285 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.861285 # CPI: Total CPI of All Threads +system.cpu.ipc 1.161056 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.161056 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1079439367 # number of integer regfile reads +system.cpu.int_regfile_writes 384873719 # number of integer regfile writes +system.cpu.fp_regfile_reads 2913212 # number of floating regfile reads +system.cpu.fp_regfile_writes 2497494 # number of floating regfile writes +system.cpu.misc_regfile_reads 54494427 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.toL2Bus.throughput 5142648 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 4861 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 4861 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 17 # Transaction distribution +system.cpu.toL2Bus.throughput 5172543 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 4897 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 4896 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 18 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1083 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1083 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 8180 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3727 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 11907 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 261696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 119680 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 381376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 381376 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 8247 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3732 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 11979 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 263808 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 119872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 383680 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 383680 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 128 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2998500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 3018000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6138496 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6609745 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2786987 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3106490 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.replacements 2359 # number of replacements -system.cpu.icache.tagsinuse 1350.344535 # Cycle average of tags in use -system.cpu.icache.total_refs 36838706 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4089 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 9009.221326 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1350.344535 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.659348 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.659348 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 36838706 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 36838706 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 36838706 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 36838706 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 36838706 # number of overall hits -system.cpu.icache.overall_hits::total 36838706 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5281 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5281 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5281 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5281 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5281 # number of overall misses -system.cpu.icache.overall_misses::total 5281 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 212968998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 212968998 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 212968998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 212968998 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 212968998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 212968998 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 36843987 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 36843987 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 36843987 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 36843987 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 36843987 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 36843987 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000143 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000143 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000143 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000143 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000143 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000143 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40327.399735 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 40327.399735 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 40327.399735 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 40327.399735 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 40327.399735 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 40327.399735 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1167 # number of cycles access was blocked +system.cpu.icache.tags.replacements 2391 # number of replacements +system.cpu.icache.tags.tagsinuse 1346.456608 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 36834377 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4122 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8936.044881 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1346.456608 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.657450 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.657450 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 36834377 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 36834377 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 36834377 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 36834377 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 36834377 # number of overall hits +system.cpu.icache.overall_hits::total 36834377 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5330 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5330 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5330 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5330 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5330 # number of overall misses +system.cpu.icache.overall_misses::total 5330 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 215954243 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 215954243 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 215954243 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 215954243 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 215954243 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 215954243 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 36839707 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 36839707 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 36839707 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 36839707 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 36839707 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 36839707 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000145 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000145 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000145 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000145 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000145 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000145 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40516.743527 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 40516.743527 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 40516.743527 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 40516.743527 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 40516.743527 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 40516.743527 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1739 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 20 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 21 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 58.350000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 82.809524 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1190 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1190 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1190 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1190 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1190 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1190 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4091 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4091 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4091 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4091 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4091 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4091 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 161081503 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 161081503 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 161081503 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 161081503 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 161081503 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 161081503 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000111 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000111 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000111 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39374.603520 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39374.603520 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39374.603520 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 39374.603520 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39374.603520 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 39374.603520 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1205 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1205 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1205 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1205 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1205 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1205 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4125 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4125 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4125 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4125 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4125 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4125 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 162387254 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 162387254 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 162387254 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 162387254 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 162387254 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 162387254 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000112 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000112 # 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Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.777656 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 4.992159 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1426.906678 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 533.876457 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.043546 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.016293 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.059991 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 2037 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 85 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2122 # 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mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54266.682903 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56660.846954 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54857.758621 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50864.418605 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50864.418605 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54145.802831 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53340.297653 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53775.092202 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54145.802831 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53340.297653 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53775.092202 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50782.093023 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50782.093023 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54266.682903 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53045.480549 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53705.077611 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54266.682903 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53045.480549 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53705.077611 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 57 # number of replacements -system.cpu.dcache.tagsinuse 1407.131551 # Cycle average of tags in use -system.cpu.dcache.total_refs 46775584 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1853 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 25243.164598 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1407.131551 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.343538 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.343538 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 34374175 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 34374175 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12356535 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12356535 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22465 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22465 # number of LoadLockedReq hits +system.cpu.dcache.tags.replacements 57 # number of replacements +system.cpu.dcache.tags.tagsinuse 1404.261851 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 46798452 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1855 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 25228.276011 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1404.261851 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.342837 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.342837 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 34397014 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 34397014 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12356557 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12356557 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22472 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22472 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 46730710 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 46730710 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 46730710 # number of overall hits -system.cpu.dcache.overall_hits::total 46730710 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1909 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1909 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 7752 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 7752 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 46753571 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 46753571 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 46753571 # number of overall hits +system.cpu.dcache.overall_hits::total 46753571 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1913 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1913 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 7730 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 7730 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9661 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9661 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9661 # number of overall misses -system.cpu.dcache.overall_misses::total 9661 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 115578500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 115578500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 443691996 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 443691996 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 141000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 141000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 559270496 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 559270496 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 559270496 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 559270496 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 34376084 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 34376084 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9643 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9643 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9643 # number of overall misses +system.cpu.dcache.overall_misses::total 9643 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 114314976 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 114314976 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 447415748 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 447415748 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 142500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 561730724 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 561730724 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 561730724 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 561730724 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 34398927 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 34398927 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22467 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 22467 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22474 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22474 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46740371 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46740371 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46740371 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46740371 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 46763214 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46763214 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46763214 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46763214 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000056 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000056 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000627 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000627 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000625 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000625 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000207 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000207 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000207 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000207 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60544.002095 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60544.002095 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57235.809598 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 57235.809598 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 57889.503778 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 57889.503778 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 57889.503778 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 57889.503778 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 581 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 112 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59756.913748 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59756.913748 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57880.433118 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 57880.433118 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71250 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 58252.693560 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 58252.693560 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 58252.693560 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 58252.693560 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 597 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 154 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.416667 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 56 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.272727 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 77 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 17 # number of writebacks -system.cpu.dcache.writebacks::total 17 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1137 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1137 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6669 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6669 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 18 # number of writebacks +system.cpu.dcache.writebacks::total 18 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1140 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1140 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6646 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6646 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7806 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7806 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7806 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7806 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 772 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 772 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1083 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1083 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1855 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1855 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1855 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1855 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 49331013 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 49331013 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 69111498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 69111498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 118442511 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 118442511 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 118442511 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 118442511 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 7786 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7786 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7786 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7786 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 773 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 773 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1084 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1084 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1857 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1857 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1857 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1857 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 48960262 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 48960262 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 69313496 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 69313496 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 118273758 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 118273758 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 118273758 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 118273758 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses @@ -945,14 +945,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63900.275907 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63900.275907 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63814.864266 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63814.864266 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63850.410243 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 63850.410243 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63850.410243 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 63850.410243 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63337.984476 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63337.984476 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63942.339483 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63942.339483 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63690.768982 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 63690.768982 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63690.768982 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 63690.768982 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index 6b5d6bef1..371d1c275 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -107,15 +107,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 464144608 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 1506 # number of replacements -system.cpu.icache.tagsinuse 1147.986161 # Cycle average of tags in use -system.cpu.icache.total_refs 189857001 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 3051 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 62227.794494 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1147.986161 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.560540 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.560540 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1506 # number of replacements +system.cpu.icache.tags.tagsinuse 1147.986161 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 189857001 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 62227.794494 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1147.986161 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.560540 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.560540 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 189857001 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 189857001 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 189857001 # number of demand (read+write) hits @@ -185,19 +185,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 34801.376598 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34801.376598 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 34801.376598 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 1675.655740 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1380 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2369 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.582524 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3.038044 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1169.032828 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 503.584868 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.051137 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 1675.655740 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1380 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.582524 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 3.038044 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.032828 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 503.584868 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.051137 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1322 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 57 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1379 # number of ReadReq hits @@ -321,15 +321,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 40 # number of replacements -system.cpu.dcache.tagsinuse 1363.611259 # Cycle average of tags in use -system.cpu.dcache.total_refs 42007358 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1789 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 23480.915595 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1363.611259 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.332913 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.332913 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 40 # number of replacements +system.cpu.dcache.tags.tagsinuse 1363.611259 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42007358 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 23480.915595 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.611259 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.332913 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.332913 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 29599357 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 29599357 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index a79e42f60..6ce379f53 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -65,15 +65,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 541126164 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 10362 # number of replacements -system.cpu.icache.tagsinuse 1591.579171 # Cycle average of tags in use -system.cpu.icache.total_refs 193433248 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 15741.638021 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1591.579171 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.777138 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.777138 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 10362 # number of replacements +system.cpu.icache.tags.tagsinuse 1591.579171 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1591.579171 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.777138 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.777138 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits @@ -143,19 +143,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 23294.433594 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23294.433594 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2678.340865 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8691 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 4097 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.121308 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 0.000453 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2275.282924 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 403.057488 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.069436 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.081736 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2678.340865 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8691 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.121308 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 0.000453 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.282924 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 403.057488 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069436 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.081736 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 8691 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 8691 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 2 # number of Writeback hits @@ -274,15 +274,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2 # number of replacements -system.cpu.dcache.tagsinuse 1237.203941 # Cycle average of tags in use -system.cpu.dcache.total_refs 76732337 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1576 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 48688.031091 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1237.203941 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.302052 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2 # number of replacements +system.cpu.dcache.tags.tagsinuse 1237.203941 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1237.203941 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.302052 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index a9e1bd99e..2e8d78059 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.144456 # Number of seconds simulated -sim_ticks 144456233500 # Number of ticks simulated -final_tick 144456233500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.144471 # Number of seconds simulated +sim_ticks 144470654000 # Number of ticks simulated +final_tick 144470654000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 74036 # Simulator instruction rate (inst/s) -host_op_rate 124090 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 80978511 # Simulator tick rate (ticks/s) -host_mem_usage 278896 # Number of bytes of host memory used -host_seconds 1783.88 # Real time elapsed on the host +host_inst_rate 76550 # Simulator instruction rate (inst/s) +host_op_rate 128304 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 83736451 # Simulator tick rate (ticks/s) +host_mem_usage 279024 # Number of bytes of host memory used +host_seconds 1725.30 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221362962 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 217280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125312 # Number of bytes read from this memory -system.physmem.bytes_read::total 342592 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 217280 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 217280 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3395 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1958 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5353 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1504123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 867474 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2371597 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1504123 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1504123 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1504123 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 867474 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2371597 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5356 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 216768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 124992 # Number of bytes read from this memory +system.physmem.bytes_read::total 341760 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 216768 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 216768 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3387 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1953 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5340 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1500429 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 865172 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2365602 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1500429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1500429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1500429 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 865172 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2365602 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5340 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 5495 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 342592 # Total number of bytes read from memory +system.physmem.cpureqs 5492 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 341760 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 342592 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 341760 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 139 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 290 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 357 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 448 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 355 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 333 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 327 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 397 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 380 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 339 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 278 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 230 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 277 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 210 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 465 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 387 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 283 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 152 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 286 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 358 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 449 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 359 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 325 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 326 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 398 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 381 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 337 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 280 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 229 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 276 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 207 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 464 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 383 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 282 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 144456205000 # Total gap between requests +system.physmem.totGap 144470612000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 5356 # Categorize read packet sizes +system.physmem.readPktSize::6 5340 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,11 +85,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 4319 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 866 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4308 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 868 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 144 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -149,79 +149,77 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 510 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 662.337255 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 234.191565 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1287.834177 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 176 34.51% 34.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 77 15.10% 49.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 39 7.65% 57.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 29 5.69% 62.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 22 4.31% 67.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 12 2.35% 69.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 18 3.53% 73.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 5 0.98% 74.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 13 2.55% 76.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 6 1.18% 77.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 3 0.59% 78.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 6 1.18% 79.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 3 0.59% 80.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 6 1.18% 81.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 7 1.37% 82.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 5 0.98% 83.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 1 0.20% 83.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 6 1.18% 85.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 2 0.39% 85.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 2 0.39% 85.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 2 0.39% 86.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 6 1.18% 87.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 1 0.20% 87.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 3 0.59% 88.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 3 0.59% 88.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 1 0.20% 89.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 2 0.39% 89.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 1 0.20% 89.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 2 0.39% 90.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 3 0.59% 90.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 1 0.20% 90.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 3 0.59% 91.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 1 0.20% 91.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 4 0.78% 92.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.20% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 3 0.59% 93.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 2 0.39% 93.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.20% 93.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 1 0.20% 93.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 4 0.78% 94.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 1 0.20% 94.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.20% 95.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 2 0.39% 95.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 1 0.20% 95.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 2 0.39% 96.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 2 0.39% 96.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 1 0.20% 96.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 1 0.20% 96.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 1 0.20% 97.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 1 0.20% 97.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 1 0.20% 97.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 1 0.20% 97.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 1 0.20% 97.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.20% 98.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.20% 98.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 1 0.20% 98.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 1 0.20% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 508 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 662.047244 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 229.931754 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1294.319008 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 181 35.63% 35.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 78 15.35% 50.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 41 8.07% 59.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 18 3.54% 62.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 27 5.31% 67.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 9 1.77% 69.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 15 2.95% 72.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 11 2.17% 74.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 9 1.77% 76.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 6 1.18% 77.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 4 0.79% 78.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 6 1.18% 79.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 5 0.98% 80.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 4 0.79% 81.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 6 1.18% 82.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 5 0.98% 83.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 3 0.59% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 3 0.59% 84.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 4 0.79% 85.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 1 0.20% 85.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 4 0.79% 86.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 4 0.79% 87.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 3 0.59% 87.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 1 0.20% 88.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 3 0.59% 88.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 1 0.20% 88.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 2 0.39% 89.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 6 1.18% 90.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 1 0.20% 90.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 1 0.20% 90.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 1 0.20% 91.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 1 0.20% 91.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 3 0.59% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 2 0.39% 92.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 3 0.59% 92.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 1 0.20% 93.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 2 0.39% 93.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 1 0.20% 93.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 4 0.79% 94.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 3 0.59% 95.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 1 0.20% 95.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 2 0.39% 95.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 1 0.20% 95.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 2 0.39% 96.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 1 0.20% 96.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 1 0.20% 96.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 1 0.20% 96.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 1 0.20% 97.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 2 0.39% 97.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 1 0.20% 97.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 1 0.20% 97.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 1 0.20% 98.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 1 0.20% 98.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 1 0.20% 98.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 1 0.20% 98.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::6912-6913 1 0.20% 98.82% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8129 1 0.20% 99.02% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 5 0.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 510 # Bytes accessed per row activation -system.physmem.totQLat 13729500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 120235750 # Sum of mem lat for all requests -system.physmem.totBusLat 26770000 # Total cycles spent in databus access -system.physmem.totBankLat 79736250 # Total cycles spent in bank access -system.physmem.avgQLat 2563.39 # Average queueing delay per request -system.physmem.avgBankLat 14887.28 # Average bank access latency per request -system.physmem.avgBusLat 4998.13 # Average bus latency per request -system.physmem.avgMemAccLat 22448.80 # Average memory access latency +system.physmem.bytesPerActivate::total 508 # Bytes accessed per row activation +system.physmem.totQLat 12730250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 118864000 # Sum of mem lat for all requests +system.physmem.totBusLat 26700000 # Total cycles spent in databus access +system.physmem.totBankLat 79433750 # Total cycles spent in bank access +system.physmem.avgQLat 2383.94 # Average queueing delay per request +system.physmem.avgBankLat 14875.23 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 22259.18 # Average memory access latency system.physmem.avgRdBW 2.37 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.37 # Average consumed read bandwidth in MB/s @@ -230,272 +228,272 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4844 # Number of row buffer hits during reads +system.physmem.readRowHits 4832 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.44 # Row buffer hit rate for reads +system.physmem.readRowHitRate 90.49 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 26970912.06 # Average gap between requests -system.membus.throughput 2371597 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 3826 # Transaction distribution -system.membus.trans_dist::ReadResp 3823 # Transaction distribution -system.membus.trans_dist::UpgradeReq 139 # Transaction distribution -system.membus.trans_dist::UpgradeResp 139 # Transaction distribution +system.physmem.avgGap 27054421.72 # Average gap between requests +system.membus.throughput 2365159 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3810 # Transaction distribution +system.membus.trans_dist::ReadResp 3809 # Transaction distribution +system.membus.trans_dist::UpgradeReq 152 # Transaction distribution +system.membus.trans_dist::UpgradeResp 152 # Transaction distribution system.membus.trans_dist::ReadExReq 1530 # Transaction distribution system.membus.trans_dist::ReadExResp 1530 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10987 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 10987 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 10987 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10987 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 342592 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 342592 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 342592 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 342592 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 342592 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10983 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 10983 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 10983 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10983 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 341696 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 341696 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 341696 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 341696 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 341696 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 7029500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6922500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 50887361 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 50657098 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 18668412 # Number of BP lookups -system.cpu.branchPred.condPredicted 18668412 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1491215 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11464480 # Number of BTB lookups -system.cpu.branchPred.BTBHits 10808529 # Number of BTB hits +system.cpu.branchPred.lookups 18662810 # Number of BP lookups +system.cpu.branchPred.condPredicted 18662810 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1489054 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11419999 # Number of BTB lookups +system.cpu.branchPred.BTBHits 10818987 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.278406 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1321942 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 23508 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.737197 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1313526 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 22992 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 289199941 # number of cpu cycles simulated +system.cpu.numCycles 289223613 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 23489092 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 206857811 # Number of instructions fetch has processed -system.cpu.fetch.Branches 18668412 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 12130471 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 54260755 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 15560780 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 178047703 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1375 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 7863 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22383448 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 227467 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 269615649 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.269321 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.757232 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 23462367 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 206597935 # Number of instructions fetch has processed +system.cpu.fetch.Branches 18662810 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 12132513 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 54232022 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 15527864 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 178098132 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1461 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 8383 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 64 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22359928 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 225896 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 269583947 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.268673 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.756592 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 216795166 80.41% 80.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2848237 1.06% 81.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2316890 0.86% 82.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2640281 0.98% 83.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3221568 1.19% 84.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3391687 1.26% 85.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3836150 1.42% 87.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2560999 0.95% 88.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 32004671 11.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 216790408 80.42% 80.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2847266 1.06% 81.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2313368 0.86% 82.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2651625 0.98% 83.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3218833 1.19% 84.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3390708 1.26% 85.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3829918 1.42% 87.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2557961 0.95% 88.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 31983860 11.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 269615649 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.064552 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.715276 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36944387 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 167005183 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 41608261 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10249032 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 13808786 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 336293429 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 13808786 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 45003701 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 116679127 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 28084 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 42750473 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 51345478 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 329924152 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 10957 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 26042658 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22711387 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 324 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 382666276 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 918470799 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 910237815 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 8232984 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 269583947 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.064527 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.714319 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 36913432 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 167057645 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 41544375 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10286977 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 13781518 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 336085554 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 13781518 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 44957189 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 116645963 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 32240 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 42740267 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 51426770 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 329706442 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 10945 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 26120234 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22717452 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 239 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 382540638 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 917473743 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 909278159 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 8195584 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 123236826 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2077 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2071 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 105014998 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 84558511 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 30136347 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 58291555 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 18982732 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 322974285 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4304 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 260692143 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 115978 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 101227039 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 210564251 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3059 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 269615649 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.966903 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.344359 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 123111188 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2136 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2172 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 105032755 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 84354587 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 30100906 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 58264869 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 19038031 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 322777816 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4259 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 260629412 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 116539 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 101038886 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 209946848 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3014 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 269583947 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.966784 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.343888 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 143415763 53.19% 53.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55488403 20.58% 73.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34156757 12.67% 86.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 19088088 7.08% 93.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10888681 4.04% 97.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4144802 1.54% 99.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1820810 0.68% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 476392 0.18% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 135953 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 143351146 53.17% 53.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 55555603 20.61% 73.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 34178684 12.68% 86.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19029881 7.06% 93.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10872516 4.03% 97.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4173623 1.55% 99.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1820350 0.68% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 470633 0.17% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 131511 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 269615649 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 269583947 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 130533 4.80% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2283697 84.00% 88.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 304445 11.20% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 130095 4.79% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2285309 84.07% 88.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 303076 11.15% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1210883 0.46% 0.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 162146963 62.20% 62.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 788849 0.30% 62.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7035772 2.70% 65.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1445624 0.55% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 65501773 25.13% 91.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 22562279 8.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1210969 0.46% 0.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 162174415 62.22% 62.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 791156 0.30% 62.99% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7035823 2.70% 65.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1446634 0.56% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.25% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 65423127 25.10% 91.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 22547288 8.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 260692143 # Type of FU issued -system.cpu.iq.rate 0.901425 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2718675 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010429 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 788942081 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 420863494 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 255312010 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4892507 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 3626050 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2350305 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 259737433 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2462502 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18945833 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 260629412 # Type of FU issued +system.cpu.iq.rate 0.901135 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2718480 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010430 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 788786495 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 420497128 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 255267923 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4891295 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 3603930 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2350852 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 259675050 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2461873 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18886019 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 27908924 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 26612 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 289609 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 9620630 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 27705000 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 26101 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 285579 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 9585192 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 51419 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 50399 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 13808786 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 85007909 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5442016 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 322978589 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 134528 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 84558511 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 30136347 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2042 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2673918 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13520 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 289609 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 642268 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 899522 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1541790 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 258904579 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 64718726 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1787564 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 13781518 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 85016114 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5459108 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 322782075 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 133200 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 84354587 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 30100909 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2090 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2675714 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 13368 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 285579 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 639541 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 899945 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1539486 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 258853338 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 64649488 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1776074 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 87077956 # number of memory reference insts executed -system.cpu.iew.exec_branches 14272272 # Number of branches executed -system.cpu.iew.exec_stores 22359230 # Number of stores executed -system.cpu.iew.exec_rate 0.895244 # Inst execution rate -system.cpu.iew.wb_sent 258260440 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 257662315 # cumulative count of insts written-back -system.cpu.iew.wb_producers 206077428 # num instructions producing a value -system.cpu.iew.wb_consumers 369317966 # num instructions consuming a value +system.cpu.iew.exec_refs 86992429 # number of memory reference insts executed +system.cpu.iew.exec_branches 14274182 # Number of branches executed +system.cpu.iew.exec_stores 22342941 # Number of stores executed +system.cpu.iew.exec_rate 0.894994 # Inst execution rate +system.cpu.iew.wb_sent 258213659 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 257618775 # cumulative count of insts written-back +system.cpu.iew.wb_producers 206032066 # num instructions producing a value +system.cpu.iew.wb_consumers 369264105 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.890949 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.557995 # average fanout of values written-back +system.cpu.iew.wb_rate 0.890725 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.557953 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 101692643 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 101495618 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1492367 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 255806863 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.865352 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.655114 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1490324 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 255802429 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.865367 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.654211 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 156513813 61.18% 61.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57168789 22.35% 83.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14010033 5.48% 89.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12060678 4.71% 93.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4174757 1.63% 95.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2964012 1.16% 96.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 898257 0.35% 96.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1048749 0.41% 97.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6967775 2.72% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 156431243 61.15% 61.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57241672 22.38% 83.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14031050 5.49% 89.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12055371 4.71% 93.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4173166 1.63% 95.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2967121 1.16% 96.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 906774 0.35% 96.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1044092 0.41% 97.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6951940 2.72% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 255806863 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 255802429 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221362962 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -506,220 +504,222 @@ system.cpu.commit.branches 12326938 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339553 # Number of committed integer instructions. system.cpu.commit.function_calls 797818 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6967775 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6951940 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 571894693 # The number of ROB reads -system.cpu.rob.rob_writes 659945778 # The number of ROB writes -system.cpu.timesIdled 5917549 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19584292 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 571709069 # The number of ROB reads +system.cpu.rob.rob_writes 659523764 # The number of ROB writes +system.cpu.timesIdled 5926858 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19639666 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221362962 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated -system.cpu.cpi 2.189728 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.189728 # CPI: Total CPI of All Threads -system.cpu.ipc 0.456678 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.456678 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 554359034 # number of integer regfile reads -system.cpu.int_regfile_writes 293931276 # number of integer regfile writes -system.cpu.fp_regfile_reads 3216619 # number of floating regfile reads -system.cpu.fp_regfile_writes 2010069 # number of floating regfile writes -system.cpu.misc_regfile_reads 133443045 # number of misc regfile reads +system.cpu.cpi 2.189907 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.189907 # CPI: Total CPI of All Threads +system.cpu.ipc 0.456640 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.456640 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 554085462 # number of integer regfile reads +system.cpu.int_regfile_writes 293886504 # number of integer regfile writes +system.cpu.fp_regfile_reads 3218743 # number of floating regfile reads +system.cpu.fp_regfile_writes 2010653 # number of floating regfile writes +system.cpu.misc_regfile_reads 133373003 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.toL2Bus.throughput 3896100 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7248 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7244 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 13 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 139 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 139 # Transaction distribution +system.cpu.toL2Bus.throughput 3891282 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7235 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7233 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 14 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 153 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 153 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1537 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1537 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 13426 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4292 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 17718 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 425152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 128768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 553920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 553920 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 8896 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4481500 # Layer occupancy (ticks) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 13393 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4315 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 17708 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 423616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 128704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 552320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 552320 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 9856 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4483500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 10173000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 10832250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3068000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3515652 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.replacements 4678 # number of replacements -system.cpu.icache.tagsinuse 1622.603356 # Cycle average of tags in use -system.cpu.icache.total_refs 22374543 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 6643 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3368.138341 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1622.603356 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.792287 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.792287 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 22374545 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22374545 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22374545 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22374545 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22374545 # number of overall hits -system.cpu.icache.overall_hits::total 22374545 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8903 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8903 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8903 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8903 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8903 # number of overall misses -system.cpu.icache.overall_misses::total 8903 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 349961000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 349961000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 349961000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 349961000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 349961000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 349961000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22383448 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22383448 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22383448 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22383448 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22383448 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22383448 # number of overall (read+write) accesses +system.cpu.icache.tags.replacements 4654 # number of replacements +system.cpu.icache.tags.tagsinuse 1616.215170 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22351029 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6622 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3375.268650 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1616.215170 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.789168 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.789168 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 22351029 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22351029 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22351029 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22351029 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22351029 # number of overall hits +system.cpu.icache.overall_hits::total 22351029 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8899 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8899 # 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average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38737.726670 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 38737.726670 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 38650.612637 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38650.612637 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38650.612637 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 38650.612637 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38650.612637 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 38650.612637 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # 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average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72252.900232 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 66499.869349 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 63174.509804 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 63174.509804 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65769.729093 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65169.811321 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 65550.121337 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65769.729093 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65169.811321 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 65550.121337 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.511782 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.977477 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.619749 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.511782 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.977477 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.619749 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65691.484652 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72919.621749 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 66493.768040 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 63360.457516 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 63360.457516 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65691.484652 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65430.875576 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 65596.189852 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65691.484652 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65430.875576 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 65596.189852 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -728,166 +728,166 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3396 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 431 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3827 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 139 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 139 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3388 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 423 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3811 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 152 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 152 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1530 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1530 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3396 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1961 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5357 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3396 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1961 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5357 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 181247500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25841000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 207088500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1390139 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1390139 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 77362000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 77362000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 181247500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 103203000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 284450500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 181247500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 103203000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 284450500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.511138 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.926882 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.538332 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3388 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1953 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5341 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3388 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1953 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5341 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 179944250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25531000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 205475250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1520152 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1520152 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 77356000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 77356000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 179944250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 102887000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 282831250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 179944250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 102887000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 282831250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.511782 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.917570 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.538201 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.993464 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.993464 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995446 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995446 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.511138 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.979520 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.619593 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.511138 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.979520 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.619593 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53370.877503 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59955.916473 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54112.490201 # average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.511782 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.977477 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.619749 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53370.877503 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52627.740948 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53098.842636 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53370.877503 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52627.740948 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53098.842636 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50559.477124 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50559.477124 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53112.234357 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52681.515617 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52954.736941 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53112.234357 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52681.515617 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52954.736941 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 56 # number of replacements -system.cpu.dcache.tagsinuse 1435.278677 # Cycle average of tags in use -system.cpu.dcache.total_refs 66130970 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1999 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33082.026013 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1435.278677 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.350410 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.350410 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 45616715 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 45616715 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20514054 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20514054 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 66130769 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 66130769 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 66130769 # number of overall hits -system.cpu.dcache.overall_hits::total 66130769 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 933 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 933 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1677 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1677 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2610 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2610 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2610 # number of overall misses -system.cpu.dcache.overall_misses::total 2610 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 56235500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 56235500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 104835500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 104835500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 161071000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 161071000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 161071000 # 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Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 45609763 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 45609763 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20514039 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20514039 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 66123802 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 66123802 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 66123802 # number of overall hits +system.cpu.dcache.overall_hits::total 66123802 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 934 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 934 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1692 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1692 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2626 # 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number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 45610697 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 66133379 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 66133379 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 66133379 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 66133379 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 66126428 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 66126428 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 66126428 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 66126428 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000082 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000082 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000039 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000039 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000039 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000039 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60273.847803 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60273.847803 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62513.714967 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62513.714967 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61713.026820 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61713.026820 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61713.026820 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61713.026820 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 227 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.000040 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000040 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000040 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000040 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59849.914347 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59849.914347 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62809.486998 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62809.486998 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61756.843869 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61756.843869 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61756.843869 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61756.843869 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 228 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 75.666667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 76 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 13 # number of writebacks -system.cpu.dcache.writebacks::total 13 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 467 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 467 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 469 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 469 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 469 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 469 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 466 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 466 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1675 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1675 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2141 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2141 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2141 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32012500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 32012500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 101366000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 101366000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 133378500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 133378500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 133378500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 133378500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 14 # number of writebacks +system.cpu.dcache.writebacks::total 14 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 472 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 472 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 475 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 475 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 475 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 475 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 462 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 462 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1689 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1689 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2151 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2151 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2151 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2151 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31756250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 31756250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 102039098 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 102039098 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 133795348 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 133795348 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 133795348 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 133795348 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000082 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000082 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68696.351931 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68696.351931 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60517.014925 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60517.014925 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62297.290986 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 62297.290986 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62297.290986 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 62297.290986 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000033 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000033 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68736.471861 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68736.471861 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60413.912374 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60413.912374 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62201.463505 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 62201.463505 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62201.463505 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 62201.463505 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index db00eb843..8e5c309b6 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -69,15 +69,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 501907914 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 2836 # number of replacements -system.cpu.icache.tagsinuse 1455.296642 # Cycle average of tags in use -system.cpu.icache.total_refs 173489674 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 36959.879421 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1455.296642 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.710594 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 2836 # number of replacements +system.cpu.icache.tags.tagsinuse 1455.296642 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 173489674 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 36959.879421 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296642 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.710594 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 173489674 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 173489674 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 173489674 # number of demand (read+write) hits @@ -147,19 +147,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 36414.784832 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.784832 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.784832 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2058.178686 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1862 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3164 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.588496 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1829.978580 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 228.178362 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.062811 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2058.178686 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1862 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.588496 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.978580 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 228.178362 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.062811 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1854 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 7 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1861 # number of ReadReq hits @@ -283,15 +283,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 41 # number of replacements -system.cpu.dcache.tagsinuse 1363.457571 # Cycle average of tags in use -system.cpu.dcache.total_refs 77195831 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 40522.745932 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1363.457571 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.332875 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 41 # number of replacements +system.cpu.dcache.tags.tagsinuse 1363.457571 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457571 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.332875 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits |