diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-25 13:14:42 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-25 13:14:42 -0400 |
| commit | 8fe556338db4cc50a3f1ba20306bc5e464941f2b (patch) | |
| tree | d95b1933c18d142f9c533f32ac7b84bd1f2d0da5 /tests/long/se/70.twolf/ref | |
| parent | 66e331c7bb7d503c35808325e1bfaa9f18f4bdb9 (diff) | |
| download | gem5-8fe556338db4cc50a3f1ba20306bc5e464941f2b.tar.xz | |
stats: Update stats to reflect use of SimpleDRAM
This patch bumps the stats to match the use of SimpleDRAM instead of
SimpleMemory in all inorder and O3 regressions, and also all
full-system regressions. A number of performance-related stats change,
and a whole bunch of stats are added for the memory controller.
Diffstat (limited to 'tests/long/se/70.twolf/ref')
4 files changed, 2486 insertions, 1851 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index feb13ce30..a6fa2a523 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.042001 # Number of seconds simulated -sim_ticks 42001440000 # Number of ticks simulated -final_tick 42001440000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.041975 # Number of seconds simulated +sim_ticks 41974805000 # Number of ticks simulated +final_tick 41974805000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 134131 # Simulator instruction rate (inst/s) -host_op_rate 134131 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61300636 # Simulator tick rate (ticks/s) -host_mem_usage 216520 # Number of bytes of host memory used -host_seconds 685.17 # Real time elapsed on the host +host_inst_rate 82989 # Simulator instruction rate (inst/s) +host_op_rate 82989 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37903288 # Simulator tick rate (ticks/s) +host_mem_usage 220440 # Number of bytes of host memory used +host_seconds 1107.42 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory @@ -19,14 +19,172 @@ system.physmem.bytes_inst_read::total 178816 # Nu system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 4257378 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3266936 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7524313 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4257378 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4257378 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4257378 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3266936 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7524313 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 4260079 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3269009 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7529088 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4260079 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4260079 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4260079 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3269009 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7529088 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 4938 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 4938 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 316032 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 316032 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 349 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 313 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 229 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 290 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 250 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 283 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 352 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 383 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 306 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 282 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 254 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 283 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 313 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 363 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 356 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 332 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 41974753000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 4938 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 3879 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 789 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 235 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 15273921 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 109715921 # Sum of mem lat for all requests +system.physmem.totBusLat 19752000 # Total cycles spent in databus access +system.physmem.totBankLat 74690000 # Total cycles spent in bank access +system.physmem.avgQLat 3093.14 # Average queueing delay per request +system.physmem.avgBankLat 15125.56 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 22218.70 # Average memory access latency +system.physmem.avgRdBW 7.53 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 7.53 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.05 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.00 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 4458 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.28 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 8500355.00 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -43,10 +201,10 @@ system.cpu.dtb.data_hits 26498122 # DT system.cpu.dtb.data_misses 33 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 26498155 # DTB accesses -system.cpu.itb.fetch_hits 10035828 # ITB hits +system.cpu.itb.fetch_hits 10035744 # ITB hits system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 10035877 # ITB accesses +system.cpu.itb.fetch_accesses 10035793 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,42 +218,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 84002881 # number of cpu cycles simulated +system.cpu.numCycles 83949611 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 13564877 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 9782208 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 4497797 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 7992443 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 3850454 # Number of BTB hits +system.cpu.branch_predictor.lookups 13564912 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 9782242 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 4497823 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 7992579 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 3850502 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 122 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 48.176183 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 5999677 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 7565200 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 73745294 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 48.175964 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 5999728 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 7565184 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 73745301 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 136320766 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 136320773 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 2206799 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 8058687 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 38528678 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 26769096 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 3520460 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 976479 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4496939 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 5743763 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 43.912410 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 57470351 # Number of Instructions Executed. +system.cpu.regfile_manager.regForwards 38528717 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 26769089 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 3520477 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 976488 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4496965 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 5743737 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 43.912663 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 57470360 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 458258 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 83639631 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 83639616 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 11378 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7720370 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 76282511 # Number of cycles cpu stages are processed. -system.cpu.activity 90.809399 # Percentage of cycles cpu is active +system.cpu.timesIdled 11375 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7667023 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 76282588 # Number of cycles cpu stages are processed. +system.cpu.activity 90.867113 # Percentage of cycles cpu is active system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed @@ -107,144 +265,144 @@ system.cpu.committedInsts 91903056 # Nu system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) -system.cpu.cpi 0.914038 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.913458 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.914038 # CPI: Total CPI of All Threads -system.cpu.ipc 1.094046 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.913458 # CPI: Total CPI of All Threads +system.cpu.ipc 1.094741 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.094046 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 27781439 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 56221442 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 66.927993 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 34555420 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 49447461 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 58.864006 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 34024816 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 1.094741 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 27728071 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 56221540 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 66.970578 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 34502106 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 49447505 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 58.901411 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 33971546 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 49978065 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 59.495656 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65973303 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 18029578 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.463047 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 30058791 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 53944090 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.216952 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.utilization 59.533409 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65920043 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 18029568 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.476655 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 30005535 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 53944076 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.257684 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 8127 # number of replacements -system.cpu.icache.tagsinuse 1492.293343 # Cycle average of tags in use -system.cpu.icache.total_refs 10024070 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1492.468291 # Cycle average of tags in use +system.cpu.icache.total_refs 10023999 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 10012 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1001.205553 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1001.198462 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1492.293343 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.728659 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.728659 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10024070 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10024070 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10024070 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10024070 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10024070 # number of overall hits -system.cpu.icache.overall_hits::total 10024070 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11754 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11754 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11754 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11754 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11754 # number of overall misses -system.cpu.icache.overall_misses::total 11754 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 284626500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 284626500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 284626500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 284626500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 284626500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 284626500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 10035824 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 10035824 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 10035824 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 10035824 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 10035824 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 10035824 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001171 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001171 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001171 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001171 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001171 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001171 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24215.288412 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 24215.288412 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 24215.288412 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 24215.288412 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 24215.288412 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 24215.288412 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1492.468291 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.728744 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.728744 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 10023999 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10023999 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10023999 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10023999 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10023999 # number of overall hits +system.cpu.icache.overall_hits::total 10023999 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11743 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11743 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11743 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11743 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11743 # number of overall misses +system.cpu.icache.overall_misses::total 11743 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 259067500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 259067500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 259067500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 259067500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 259067500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 259067500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 10035742 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 10035742 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 10035742 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 10035742 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 10035742 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 10035742 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001170 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001170 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001170 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001170 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001170 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001170 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22061.440858 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22061.440858 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22061.440858 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22061.440858 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22061.440858 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22061.440858 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 184 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 67 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 30.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 16.750000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1742 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1742 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1742 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1742 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1742 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1742 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1731 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1731 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1731 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1731 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1731 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1731 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10012 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 10012 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 10012 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 10012 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 10012 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 10012 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 231904000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 231904000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 231904000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 231904000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 231904000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 231904000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 210374500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 210374500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 210374500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 210374500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 210374500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 210374500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000998 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000998 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000998 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000998 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23162.604874 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23162.604874 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23162.604874 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 23162.604874 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23162.604874 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 23162.604874 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21012.235318 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21012.235318 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21012.235318 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21012.235318 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21012.235318 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21012.235318 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1441.465399 # Cycle average of tags in use -system.cpu.dcache.total_refs 26491189 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1441.629591 # Cycle average of tags in use +system.cpu.dcache.total_refs 26491183 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11916.864148 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11916.861448 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1441.465399 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.351920 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.351920 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 19995639 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 19995639 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6495550 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6495550 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26491189 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26491189 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26491189 # number of overall hits -system.cpu.dcache.overall_hits::total 26491189 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 559 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 559 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5553 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5553 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 6112 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 6112 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 6112 # number of overall misses -system.cpu.dcache.overall_misses::total 6112 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 28955000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 28955000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 305088500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 305088500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 334043500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 334043500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 334043500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 334043500 # number of overall miss cycles +system.cpu.dcache.occ_blocks::cpu.data 1441.629591 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.351960 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.351960 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 19995637 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 19995637 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6495546 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6495546 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26491183 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26491183 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26491183 # number of overall hits +system.cpu.dcache.overall_hits::total 26491183 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 561 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 561 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5557 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5557 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 6118 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 6118 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 6118 # number of overall misses +system.cpu.dcache.overall_misses::total 6118 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 28389500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 28389500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 249397000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 249397000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 277786500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 277786500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 277786500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 277786500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -255,38 +413,38 @@ system.cpu.dcache.overall_accesses::cpu.data 26497301 system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000854 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000854 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000855 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000855 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000231 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000231 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000231 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000231 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51797.853309 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51797.853309 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54941.202953 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54941.202953 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54653.714005 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54653.714005 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54653.714005 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54653.714005 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50605.169340 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50605.169340 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44879.791254 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44879.791254 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45404.789147 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45404.789147 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45404.789147 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45404.789147 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 82457 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 63919 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 827 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 99.706167 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 77.290206 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 107 # number of writebacks system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 84 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3805 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3805 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3889 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3889 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3889 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3889 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 86 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 86 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3809 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3809 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3895 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3895 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3895 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3895 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses @@ -295,14 +453,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24156000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24156000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 96637000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 96637000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 120793000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 120793000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 120793000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 120793000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23282500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23282500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 80468500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 80468500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 103751000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 103751000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 103751000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 103751000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -311,28 +469,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50854.736842 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50854.736842 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55284.324943 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55284.324943 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54337.831759 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 54337.831759 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54337.831759 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 54337.831759 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49015.789474 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49015.789474 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46034.610984 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46034.610984 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46671.614935 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 46671.614935 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46671.614935 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 46671.614935 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2189.683531 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2189.948520 # Cycle average of tags in use system.cpu.l2cache.total_refs 7285 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.219683 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.845444 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1820.840268 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 350.997820 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 17.843388 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1821.063413 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 351.041719 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.055568 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.010712 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.066824 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.055574 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.010713 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.066832 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 7218 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 7271 # number of ReadReq hits @@ -357,17 +515,17 @@ system.cpu.l2cache.demand_misses::total 4938 # nu system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4938 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 149399500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 23132500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 172532000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 94615000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 94615000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 149399500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 117747500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 267147000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 149399500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 117747500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 267147000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 127870000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22259000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 150129000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 78446500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 78446500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 127870000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 100705500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 228575500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 127870000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 100705500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 228575500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 10012 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 10487 # number of ReadReq accesses(hits+misses) @@ -392,17 +550,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.403596 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.279065 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.403596 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53471.546170 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54816.350711 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 53648.009950 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54944.831591 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54944.831591 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53471.546170 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54919.542910 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 54100.243013 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53471.546170 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54919.542910 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 54100.243013 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 45765.926986 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52746.445498 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 46681.902985 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 45555.458769 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 45555.458769 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 45765.926986 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46970.848881 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 46289.084650 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 45765.926986 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46970.848881 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 46289.084650 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -422,17 +580,17 @@ system.cpu.l2cache.demand_mshr_misses::total 4938 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115312500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17984000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 133296500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 73481500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 73481500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115312500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 91465500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 206778000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115312500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 91465500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 206778000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 92500808 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16940683 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 109441491 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 57047489 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 57047489 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 92500808 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 73988172 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 166488980 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 92500808 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 73988172 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 166488980 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.306665 # mshr miss rate for ReadReq accesses @@ -444,17 +602,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.403596 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.279065 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.403596 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41271.474588 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42616.113744 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41447.916667 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42672.183508 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42672.183508 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41271.474588 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42661.147388 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41874.848117 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41271.474588 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42661.147388 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41874.848117 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33106.946314 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40143.798578 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34030.314366 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33128.623113 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33128.623113 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33106.946314 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34509.408582 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33715.872823 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33106.946314 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34509.408582 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33715.872823 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index c18f0c43e..ca5f0ff42 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,52 +1,210 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023660 # Number of seconds simulated -sim_ticks 23659827000 # Number of ticks simulated -final_tick 23659827000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023631 # Number of seconds simulated +sim_ticks 23630830000 # Number of ticks simulated +final_tick 23630830000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 188397 # Simulator instruction rate (inst/s) -host_op_rate 188397 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52951506 # Simulator tick rate (ticks/s) -host_mem_usage 217548 # Number of bytes of host memory used -host_seconds 446.82 # Real time elapsed on the host +host_inst_rate 120910 # Simulator instruction rate (inst/s) +host_op_rate 120910 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 33941778 # Simulator tick rate (ticks/s) +host_mem_usage 221472 # Number of bytes of host memory used +host_seconds 696.22 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 197632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138432 # Number of bytes read from this memory -system.physmem.bytes_read::total 336064 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 197632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 197632 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3088 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2163 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5251 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8353062 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5850930 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14203992 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8353062 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8353062 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8353062 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5850930 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 14203992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 197248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138368 # Number of bytes read from this memory +system.physmem.bytes_read::total 335616 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 197248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 197248 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3082 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2162 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5244 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8347062 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5855402 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14202463 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8347062 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8347062 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8347062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5855402 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 14202463 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5244 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 5244 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 335616 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 335616 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 369 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 342 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 252 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 318 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 255 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 295 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 377 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 403 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 324 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 298 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 279 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 287 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 325 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 386 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 380 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 354 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 23630742000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 5244 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 3183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1271 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 583 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 23669737 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 116101737 # Sum of mem lat for all requests +system.physmem.totBusLat 20976000 # Total cycles spent in databus access +system.physmem.totBankLat 71456000 # Total cycles spent in bank access +system.physmem.avgQLat 4513.68 # Average queueing delay per request +system.physmem.avgBankLat 13626.24 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 22139.92 # Average memory access latency +system.physmem.avgRdBW 14.20 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 14.20 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.09 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.00 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 4702 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.66 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 4506243.71 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 23229098 # DTB read hits -system.cpu.dtb.read_misses 198676 # DTB read misses +system.cpu.dtb.read_hits 23223355 # DTB read hits +system.cpu.dtb.read_misses 199967 # DTB read misses system.cpu.dtb.read_acv 4 # DTB read access violations -system.cpu.dtb.read_accesses 23427774 # DTB read accesses -system.cpu.dtb.write_hits 7078776 # DTB write hits -system.cpu.dtb.write_misses 1365 # DTB write misses -system.cpu.dtb.write_acv 4 # DTB write access violations -system.cpu.dtb.write_accesses 7080141 # DTB write accesses -system.cpu.dtb.data_hits 30307874 # DTB hits -system.cpu.dtb.data_misses 200041 # DTB misses -system.cpu.dtb.data_acv 8 # DTB access violations -system.cpu.dtb.data_accesses 30507915 # DTB accesses -system.cpu.itb.fetch_hits 14959914 # ITB hits -system.cpu.itb.fetch_misses 83 # ITB misses +system.cpu.dtb.read_accesses 23423322 # DTB read accesses +system.cpu.dtb.write_hits 7080030 # DTB write hits +system.cpu.dtb.write_misses 1356 # DTB write misses +system.cpu.dtb.write_acv 2 # DTB write access violations +system.cpu.dtb.write_accesses 7081386 # DTB write accesses +system.cpu.dtb.data_hits 30303385 # DTB hits +system.cpu.dtb.data_misses 201323 # DTB misses +system.cpu.dtb.data_acv 6 # DTB access violations +system.cpu.dtb.data_accesses 30504708 # DTB accesses +system.cpu.itb.fetch_hits 14954333 # ITB hits +system.cpu.itb.fetch_misses 120 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14959997 # ITB accesses +system.cpu.itb.fetch_accesses 14954453 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,146 +218,146 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 47319655 # number of cpu cycles simulated +system.cpu.numCycles 47261661 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15036576 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 10900203 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 965407 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 8822625 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7081383 # Number of BTB hits +system.cpu.BPredUnit.lookups 15031497 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10899201 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 964727 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 8732701 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7076597 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1488044 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 3227 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 15623244 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 128299344 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15036576 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 8569427 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22397875 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4641617 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5564099 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 1487345 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 3368 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15614500 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 128263242 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15031497 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 8563942 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22389896 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4636452 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5551739 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1980 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14959914 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 337946 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 47229880 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.716487 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.372485 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 2133 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14954333 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 338853 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 47196510 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.717643 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.372831 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24832005 52.58% 52.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2392801 5.07% 57.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1209799 2.56% 60.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1776867 3.76% 63.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2804961 5.94% 69.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1173464 2.48% 72.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1230763 2.61% 75.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 789158 1.67% 76.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11020062 23.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24806614 52.56% 52.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2389980 5.06% 57.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1210958 2.57% 60.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1776777 3.76% 63.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2802179 5.94% 69.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1172690 2.48% 72.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1230204 2.61% 74.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 789239 1.67% 76.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11017869 23.34% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 47229880 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.317766 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.711333 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17466031 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4264969 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20777128 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1090965 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3630787 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2547167 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12222 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 125218187 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 32252 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3630787 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18637244 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 968362 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8091 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20675127 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3310269 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 122217574 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 404537 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2431302 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 89737060 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 158727741 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 148984302 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9743439 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 47196510 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.318048 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.713896 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17460604 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4250656 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20766421 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1092488 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3626341 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2544445 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12397 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 125174951 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 32088 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3626341 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18627234 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 962190 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8129 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20670858 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3301758 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 122185352 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 402329 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2427096 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 89707747 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 158670699 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 148931458 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9739241 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 21309699 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1072 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1080 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8762996 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 25566964 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8306109 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2633900 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 924738 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 106206807 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2480 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 97009064 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 188398 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21564802 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16193043 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2091 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 47229880 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.053977 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.874944 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 21280386 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1002 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1014 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8742077 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 25560713 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8304198 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2649829 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 949216 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 106168633 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2274 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 96984807 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 186233 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21527282 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16158700 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1885 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 47196510 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.054915 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.875207 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12465875 26.39% 26.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 9434862 19.98% 46.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8477387 17.95% 64.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6321383 13.38% 77.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4949351 10.48% 88.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2846830 6.03% 94.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1724266 3.65% 97.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 801279 1.70% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 208647 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12446961 26.37% 26.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9431395 19.98% 46.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8468096 17.94% 64.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6320682 13.39% 77.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4944837 10.48% 88.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2848295 6.03% 94.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1728522 3.66% 97.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 798557 1.69% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 209165 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 47229880 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 47196510 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 189791 12.08% 12.08% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 12.08% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 12.08% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 221 0.01% 12.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 7127 0.45% 12.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 5711 0.36% 12.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 843066 53.68% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.59% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 445505 28.36% 94.95% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 79246 5.05% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 189157 12.05% 12.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 12.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 12.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 237 0.02% 12.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 7151 0.46% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 5547 0.35% 12.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 843237 53.72% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.60% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 445222 28.36% 94.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 79100 5.04% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 59007350 60.83% 60.83% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 480907 0.50% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58989351 60.82% 60.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 480619 0.50% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2801835 2.89% 64.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115568 0.12% 64.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2386144 2.46% 66.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 311424 0.32% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 759643 0.78% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2802202 2.89% 64.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115471 0.12% 64.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2386536 2.46% 66.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 311369 0.32% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 759928 0.78% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.89% # Type of FU issued @@ -221,84 +379,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.89% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23975074 24.71% 92.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7170793 7.39% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23967188 24.71% 92.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7171817 7.39% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 97009064 # Type of FU issued -system.cpu.iq.rate 2.050080 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1570667 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016191 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 227877046 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 118983933 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87385352 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15130027 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 8824854 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7067767 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90585387 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7994337 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1520935 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 96984807 # Type of FU issued +system.cpu.iq.rate 2.052082 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1569651 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016185 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 227791870 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 118912637 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87370988 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15130138 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 8820177 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7068200 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90559677 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7994774 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1518774 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5570766 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 20063 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34811 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1805006 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5564515 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 19809 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34734 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1803095 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10523 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10505 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3630787 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 133855 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17474 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 116506957 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 391259 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 25566964 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8306109 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2480 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3139 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 46 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34811 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 570809 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 508196 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1079005 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 95710462 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23428475 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1298602 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3626341 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 131070 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17619 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 116470742 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 396615 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 25560713 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8304198 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2274 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3005 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 33 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 34734 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 570082 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 507540 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1077622 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 95693120 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23424012 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1291687 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10297670 # number of nop insts executed -system.cpu.iew.exec_refs 30508815 # number of memory reference insts executed -system.cpu.iew.exec_branches 12080088 # Number of branches executed -system.cpu.iew.exec_stores 7080340 # Number of stores executed -system.cpu.iew.exec_rate 2.022637 # Inst execution rate -system.cpu.iew.wb_sent 94996847 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 94453119 # cumulative count of insts written-back -system.cpu.iew.wb_producers 64630172 # num instructions producing a value -system.cpu.iew.wb_consumers 90018458 # num instructions consuming a value +system.cpu.iew.exec_nop 10299835 # number of nop insts executed +system.cpu.iew.exec_refs 30505591 # number of memory reference insts executed +system.cpu.iew.exec_branches 12076727 # Number of branches executed +system.cpu.iew.exec_stores 7081579 # Number of stores executed +system.cpu.iew.exec_rate 2.024752 # Inst execution rate +system.cpu.iew.wb_sent 94981894 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 94439188 # cumulative count of insts written-back +system.cpu.iew.wb_producers 64622529 # num instructions producing a value +system.cpu.iew.wb_consumers 90009959 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.996065 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717966 # average fanout of values written-back +system.cpu.iew.wb_rate 1.998220 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717949 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24605076 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 24568706 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 953560 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43599093 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.107912 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.734433 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 952874 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43570169 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.109311 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.735421 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 17053308 39.11% 39.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9978024 22.89% 62.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4508053 10.34% 72.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2287531 5.25% 77.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1622514 3.72% 81.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1125878 2.58% 83.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 721380 1.65% 85.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 820634 1.88% 87.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5481771 12.57% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 17034200 39.10% 39.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9970297 22.88% 61.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4508116 10.35% 72.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2285317 5.25% 77.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1618875 3.72% 81.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1127711 2.59% 83.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 720325 1.65% 85.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 818054 1.88% 87.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5487274 12.59% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43599093 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43570169 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -309,70 +467,70 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5481771 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5487274 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 154624413 # The number of ROB reads -system.cpu.rob.rob_writes 236671244 # The number of ROB writes -system.cpu.timesIdled 1995 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 89775 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 154553616 # The number of ROB reads +system.cpu.rob.rob_writes 236594431 # The number of ROB writes +system.cpu.timesIdled 1889 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 65151 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.562127 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.562127 # CPI: Total CPI of All Threads -system.cpu.ipc 1.778959 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.778959 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 129495815 # number of integer regfile reads -system.cpu.int_regfile_writes 70794338 # number of integer regfile writes -system.cpu.fp_regfile_reads 6191717 # number of floating regfile reads -system.cpu.fp_regfile_writes 6049387 # number of floating regfile writes -system.cpu.misc_regfile_reads 714327 # number of misc regfile reads +system.cpu.cpi 0.561438 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.561438 # CPI: Total CPI of All Threads +system.cpu.ipc 1.781142 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.781142 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 129470706 # number of integer regfile reads +system.cpu.int_regfile_writes 70779763 # number of integer regfile writes +system.cpu.fp_regfile_reads 6192026 # number of floating regfile reads +system.cpu.fp_regfile_writes 6049557 # number of floating regfile writes +system.cpu.misc_regfile_reads 714457 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 10388 # number of replacements -system.cpu.icache.tagsinuse 1605.369069 # Cycle average of tags in use -system.cpu.icache.total_refs 14946221 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 12326 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1212.576748 # Average number of references to valid blocks. +system.cpu.icache.replacements 10301 # number of replacements +system.cpu.icache.tagsinuse 1602.585562 # Cycle average of tags in use +system.cpu.icache.total_refs 14940827 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 12238 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1220.855287 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1605.369069 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.783872 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.783872 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14946221 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14946221 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14946221 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14946221 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14946221 # number of overall hits -system.cpu.icache.overall_hits::total 14946221 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13693 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 13693 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 13693 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13693 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13693 # number of overall misses -system.cpu.icache.overall_misses::total 13693 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 189030000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 189030000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 189030000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 189030000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 189030000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 189030000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14959914 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14959914 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14959914 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14959914 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14959914 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14959914 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000915 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000915 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000915 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000915 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000915 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000915 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13804.863799 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13804.863799 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13804.863799 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13804.863799 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13804.863799 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13804.863799 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1602.585562 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.782512 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.782512 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14940827 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14940827 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14940827 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14940827 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14940827 # number of overall hits +system.cpu.icache.overall_hits::total 14940827 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 13506 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 13506 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 13506 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 13506 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 13506 # number of overall misses +system.cpu.icache.overall_misses::total 13506 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 154262500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 154262500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 154262500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 154262500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 154262500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 154262500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14954333 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14954333 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14954333 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14954333 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14954333 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14954333 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000903 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000903 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000903 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000903 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000903 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000903 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11421.775507 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 11421.775507 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 11421.775507 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 11421.775507 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 11421.775507 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 11421.775507 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,300 +539,300 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1367 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1367 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1367 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1367 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1367 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1367 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12326 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 12326 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 12326 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 12326 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 12326 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 12326 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 130707500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 130707500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 130707500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 130707500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 130707500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 130707500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000824 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000824 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000824 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000824 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000824 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000824 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10604.210612 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10604.210612 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10604.210612 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 10604.210612 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10604.210612 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 10604.210612 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1268 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1268 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1268 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1268 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1268 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1268 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12238 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 12238 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 12238 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 12238 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 12238 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 12238 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 106604500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 106604500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 106604500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 106604500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 106604500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 106604500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000818 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000818 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000818 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000818 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000818 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000818 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8710.941330 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8710.941330 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8710.941330 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 8710.941330 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8710.941330 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 8710.941330 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 158 # number of replacements -system.cpu.dcache.tagsinuse 1458.278820 # Cycle average of tags in use -system.cpu.dcache.total_refs 28189701 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2243 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12567.855996 # Average number of references to valid blocks. +system.cpu.dcache.replacements 157 # number of replacements +system.cpu.dcache.tagsinuse 1457.159640 # Cycle average of tags in use +system.cpu.dcache.total_refs 28186155 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2241 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12577.489960 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1458.278820 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.356025 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.356025 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 21696214 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21696214 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6493021 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6493021 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 466 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 466 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28189235 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28189235 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28189235 # number of overall hits -system.cpu.dcache.overall_hits::total 28189235 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 958 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 958 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8082 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8082 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 1457.159640 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.355752 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.355752 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 21692653 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21692653 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6493028 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6493028 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 474 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 474 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28185681 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28185681 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28185681 # number of overall hits +system.cpu.dcache.overall_hits::total 28185681 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 936 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 936 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8075 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8075 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9040 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9040 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9040 # number of overall misses -system.cpu.dcache.overall_misses::total 9040 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29562000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29562000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 293120000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 293120000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 44000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 44000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 322682000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 322682000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 322682000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 322682000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21697172 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21697172 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9011 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9011 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9011 # number of overall misses +system.cpu.dcache.overall_misses::total 9011 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29131500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29131500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 231947500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 231947500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 54000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 54000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 261079000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 261079000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 261079000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 261079000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21693589 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21693589 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 467 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 467 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28198275 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28198275 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28198275 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28198275 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000044 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000044 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001243 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001243 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002141 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002141 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000321 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000321 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000321 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000321 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30858.037578 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30858.037578 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36268.250433 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 36268.250433 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 44000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 44000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35694.911504 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 35694.911504 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35694.911504 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35694.911504 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 11 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 475 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 475 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28194692 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28194692 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28194692 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28194692 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000043 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000043 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001242 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001242 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002105 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002105 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000320 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000320 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000320 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000320 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31123.397436 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 31123.397436 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28724.148607 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28724.148607 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 54000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 54000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28973.365886 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28973.365886 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28973.365886 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28973.365886 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 59 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.500000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 108 # number of writebacks -system.cpu.dcache.writebacks::total 108 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 446 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 446 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6352 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6352 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6798 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6798 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6798 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6798 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 512 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 512 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1730 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1730 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 107 # number of writebacks +system.cpu.dcache.writebacks::total 107 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 428 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 428 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6343 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6343 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6771 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6771 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6771 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6771 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 508 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 508 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1732 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1732 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2242 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2242 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2242 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2242 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18075000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 18075000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 68210000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 68210000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 42000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 42000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 86285000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 86285000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 86285000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 86285000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 2240 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2240 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2240 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2240 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17831000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17831000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 55893500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 55893500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 52000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 52000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 73724500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 73724500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 73724500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 73724500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.002141 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.002141 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35302.734375 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35302.734375 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39427.745665 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39427.745665 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 42000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 42000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38485.727029 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 38485.727029 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38485.727029 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 38485.727029 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.002105 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000079 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000079 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35100.393701 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35100.393701 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32271.073903 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32271.073903 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 52000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 52000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32912.723214 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 32912.723214 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32912.723214 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 32912.723214 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2420.789907 # Cycle average of tags in use -system.cpu.l2cache.total_refs 9306 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3612 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.576412 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2409.771273 # Cycle average of tags in use +system.cpu.l2cache.total_refs 9224 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3603 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.560089 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.694475 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2023.389229 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 379.706203 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 17.696686 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2016.662499 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 375.412087 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000540 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.061749 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.011588 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.073877 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 9238 # number of ReadReq hits +system.cpu.l2cache.occ_percent::cpu.inst 0.061544 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.011457 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.073540 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 9156 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 54 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 9292 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 108 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 108 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 9238 # 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mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.362180 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.251839 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964748 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.362180 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 24057.612589 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34494.767033 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 25400.249081 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28464.712947 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28464.712947 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 24057.612589 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 29733.757632 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 26397.777651 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 24057.612589 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29733.757632 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 26397.777651 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index a5a9d98b7..49d6eef8e 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,32 +1,190 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.075929 # Number of seconds simulated -sim_ticks 75929256000 # Number of ticks simulated -final_tick 75929256000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.075917 # Number of seconds simulated +sim_ticks 75916922000 # Number of ticks simulated +final_tick 75916922000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 126863 # Simulator instruction rate (inst/s) -host_op_rate 138901 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55895176 # Simulator tick rate (ticks/s) -host_mem_usage 231880 # Number of bytes of host memory used -host_seconds 1358.42 # Real time elapsed on the host -sim_insts 172333091 # Number of instructions simulated -sim_ops 188686573 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 132864 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 112384 # Number of bytes read from this memory -system.physmem.bytes_read::total 245248 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 132864 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 132864 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2076 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1756 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3832 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1749839 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1480115 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3229954 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1749839 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1749839 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1749839 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1480115 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3229954 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 139176 # Simulator instruction rate (inst/s) +host_op_rate 152383 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61310301 # Simulator tick rate (ticks/s) +host_mem_usage 236468 # Number of bytes of host memory used +host_seconds 1238.24 # Real time elapsed on the host +sim_insts 172333316 # Number of instructions simulated +sim_ops 188686798 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 132736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 112320 # Number of bytes read from this memory +system.physmem.bytes_read::total 245056 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 132736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 132736 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2074 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1755 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3829 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1748438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1479512 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3227950 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1748438 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1748438 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1748438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1479512 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3227950 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3829 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 3829 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 245056 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 245056 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 320 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 234 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 192 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 239 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 228 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 195 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 224 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 283 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 245 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 249 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 248 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 265 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 250 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 236 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 181 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 240 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 75916775000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 3829 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 2774 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 838 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 153 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 44 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 12309321 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 87055321 # Sum of mem lat for all requests +system.physmem.totBusLat 15316000 # Total cycles spent in databus access +system.physmem.totBankLat 59430000 # Total cycles spent in bank access +system.physmem.avgQLat 3214.76 # Average queueing delay per request +system.physmem.avgBankLat 15521.02 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 22735.79 # Average memory access latency +system.physmem.avgRdBW 3.23 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 3.23 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.00 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 3315 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.58 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 19826788.98 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,141 +228,141 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 151858513 # number of cpu cycles simulated +system.cpu.numCycles 151833845 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 96795637 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 76023233 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 6554345 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 46458722 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 44211681 # Number of BTB hits +system.cpu.BPredUnit.lookups 96840599 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 76060531 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 6557597 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 46497854 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 44230275 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 4476295 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 89485 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 40599440 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 388212036 # Number of instructions fetch has processed -system.cpu.fetch.Branches 96795637 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48687976 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 82231847 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 28434690 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7095448 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 11 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 8914 # Number of stall cycles due to pending traps +system.cpu.BPredUnit.usedRAS 4471070 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 89483 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 40605581 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 388281645 # Number of instructions fetch has processed +system.cpu.fetch.Branches 96840599 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48701345 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 82243787 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 28438511 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7066827 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 8646 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.CacheLines 37656314 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1885789 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 151799953 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.799634 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.153355 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 37664937 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1885880 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 151789722 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.799994 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.153176 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 69738143 45.94% 45.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5498940 3.62% 49.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10708649 7.05% 56.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10436622 6.88% 63.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8785452 5.79% 69.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6828707 4.50% 73.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6299043 4.15% 77.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8356617 5.51% 83.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 25147780 16.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 69716020 45.93% 45.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5494868 3.62% 49.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10713361 7.06% 56.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10448438 6.88% 63.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8787039 5.79% 69.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6829673 4.50% 73.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6296859 4.15% 77.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8361926 5.51% 83.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 25141538 16.56% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151799953 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.637407 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.556406 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 46621790 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5807519 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 76550031 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1109408 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 21711205 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14812709 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 162826 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 401248063 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 743977 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 21711205 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 52126095 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 710072 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 694282 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 72094443 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4463856 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 378978195 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 318341 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3575220 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 642418416 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1614444989 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1596851669 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 17593320 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 298092251 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 344326165 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 33370 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 33366 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12643089 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 43991113 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16880527 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5791698 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3695359 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 334838724 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 55508 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 252834206 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 902162 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 144982237 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 373879643 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 4278 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151799953 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.665575 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.759908 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 151789722 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.637806 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.557280 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 46630303 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5777884 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 76557243 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1112705 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 21711587 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14823931 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 162890 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 401294311 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 730539 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 21711587 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 52135013 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 698137 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 692737 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 72105161 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4447087 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 379004822 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 318070 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3558685 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 642471315 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1614529203 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1596934770 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 17594433 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 298092611 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 344378704 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 33379 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 33376 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12572106 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 43979277 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16887724 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5767479 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3738298 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 334855562 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 55454 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 252836764 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 889769 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 145001031 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 373941866 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 4179 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151789722 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.665704 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.759623 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 58349265 38.44% 38.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 22992328 15.15% 53.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25145387 16.56% 70.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20486668 13.50% 83.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12884605 8.49% 92.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6585084 4.34% 96.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4053755 2.67% 99.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1118158 0.74% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 184703 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 58337035 38.43% 38.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 22987248 15.14% 53.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25139726 16.56% 70.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20501728 13.51% 83.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12883464 8.49% 92.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6586273 4.34% 96.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4061259 2.68% 99.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1111807 0.73% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 181182 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151799953 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151789722 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 967156 37.45% 37.45% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5599 0.22% 37.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 37.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 37.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 37.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 37.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 37.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 37.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 37.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 37.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 37.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 37.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 37.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 37.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 37.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 37.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 37.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 37.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 37.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 37.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 95 0.00% 37.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 37.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 37.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 37.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 37.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 33 0.00% 37.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 37.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 37.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 37.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1198375 46.40% 84.07% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 411308 15.93% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 964155 37.62% 37.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5594 0.22% 37.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 37.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 37.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 37.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 37.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 37.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 37.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 37.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 37.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 37.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 37.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 37.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 37.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 37.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 37.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 37.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 37.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 37.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 37.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 94 0.00% 37.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 37.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 37.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 1 0.00% 37.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 37.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 24 0.00% 37.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 37.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 37.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 37.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1191140 46.48% 84.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 401719 15.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 197345283 78.05% 78.05% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 996010 0.39% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 197361954 78.06% 78.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 995375 0.39% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.45% # Type of FU issued @@ -223,167 +381,167 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.45% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33191 0.01% 78.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 164019 0.06% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 254959 0.10% 78.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76456 0.03% 78.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 467688 0.18% 78.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206418 0.08% 78.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71860 0.03% 78.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 78.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 39024792 15.43% 94.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 14193209 5.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33153 0.01% 78.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 164117 0.06% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 255226 0.10% 78.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76451 0.03% 78.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 467799 0.19% 78.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206454 0.08% 78.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71861 0.03% 78.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 78.96% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 39017631 15.43% 94.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 14186422 5.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 252834206 # Type of FU issued -system.cpu.iq.rate 1.664933 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2582566 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010214 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 657177755 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 477646556 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 240591983 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3775338 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2248788 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1851684 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 253520354 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1896418 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2029780 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 252836764 # Type of FU issued +system.cpu.iq.rate 1.665220 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2562727 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010136 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 657141484 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 477682512 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 240592268 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3774262 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2248392 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1852132 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 253504217 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1895274 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2034571 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14135615 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 17349 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19653 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4229879 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14123734 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 16793 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 19636 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4237031 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 21711205 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 12896 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 616 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 334912035 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 838129 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 43991113 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16880527 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 32938 # Number of dispatched non-speculative instructions +system.cpu.iew.iewSquashCycles 21711587 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4884 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 553 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 334928786 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 838607 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 43979277 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16887724 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 32914 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 159 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 266 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 19653 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4103971 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3924992 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8028963 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 245839126 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 37402304 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6995080 # Number of squashed instructions skipped in execute +system.cpu.iew.iewLSQFullEvents 218 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 19636 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4106046 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3927041 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8033087 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 245835770 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 37393574 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7000994 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 17803 # number of nop insts executed -system.cpu.iew.exec_refs 51215601 # number of memory reference insts executed -system.cpu.iew.exec_branches 54034095 # Number of branches executed -system.cpu.iew.exec_stores 13813297 # Number of stores executed -system.cpu.iew.exec_rate 1.618870 # Inst execution rate -system.cpu.iew.wb_sent 243576806 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 242443667 # cumulative count of insts written-back -system.cpu.iew.wb_producers 150073604 # num instructions producing a value -system.cpu.iew.wb_consumers 269189037 # num instructions consuming a value +system.cpu.iew.exec_nop 17770 # number of nop insts executed +system.cpu.iew.exec_refs 51200144 # number of memory reference insts executed +system.cpu.iew.exec_branches 54041718 # Number of branches executed +system.cpu.iew.exec_stores 13806570 # Number of stores executed +system.cpu.iew.exec_rate 1.619110 # Inst execution rate +system.cpu.iew.wb_sent 243578722 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 242444400 # cumulative count of insts written-back +system.cpu.iew.wb_producers 150079170 # num instructions producing a value +system.cpu.iew.wb_consumers 269183647 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.596510 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.557503 # average fanout of values written-back +system.cpu.iew.wb_rate 1.596774 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.557534 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 146211047 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 51230 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6401258 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 130088749 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.450556 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.162504 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 146227575 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 51275 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 6404316 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 130078136 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.450676 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.162324 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59880842 46.03% 46.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 32046581 24.63% 70.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13987597 10.75% 81.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7657894 5.89% 87.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4414755 3.39% 90.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1334314 1.03% 91.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1737378 1.34% 93.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1284458 0.99% 94.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7744930 5.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 59851320 46.01% 46.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 32072665 24.66% 70.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13982527 10.75% 81.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7658050 5.89% 87.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4412794 3.39% 90.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1335206 1.03% 91.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1737015 1.34% 93.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1288451 0.99% 94.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7740108 5.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 130088749 # Number of insts commited each cycle -system.cpu.commit.committedInsts 172347479 # Number of instructions committed -system.cpu.commit.committedOps 188700961 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 130078136 # Number of insts commited each cycle +system.cpu.commit.committedInsts 172347704 # Number of instructions committed +system.cpu.commit.committedOps 188701186 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 42506146 # Number of memory references committed -system.cpu.commit.loads 29855498 # Number of loads committed +system.cpu.commit.refs 42506236 # Number of memory references committed +system.cpu.commit.loads 29855543 # Number of loads committed system.cpu.commit.membars 22408 # Number of memory barriers committed -system.cpu.commit.branches 40306325 # Number of branches committed +system.cpu.commit.branches 40306370 # Number of branches committed system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. -system.cpu.commit.int_insts 150130273 # Number of committed integer instructions. +system.cpu.commit.int_insts 150130453 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 7744930 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 7740108 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 457250626 # The number of ROB reads -system.cpu.rob.rob_writes 691654263 # The number of ROB writes -system.cpu.timesIdled 1589 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 58560 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 172333091 # Number of Instructions Simulated -system.cpu.committedOps 188686573 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 172333091 # Number of Instructions Simulated -system.cpu.cpi 0.881192 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.881192 # CPI: Total CPI of All Threads -system.cpu.ipc 1.134827 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.134827 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1091994433 # number of integer regfile reads -system.cpu.int_regfile_writes 388620965 # number of integer regfile writes -system.cpu.fp_regfile_reads 2912840 # number of floating regfile reads -system.cpu.fp_regfile_writes 2511233 # number of floating regfile writes -system.cpu.misc_regfile_reads 474441039 # number of misc regfile reads -system.cpu.misc_regfile_writes 832064 # number of misc regfile writes -system.cpu.icache.replacements 2657 # number of replacements -system.cpu.icache.tagsinuse 1370.154308 # Cycle average of tags in use -system.cpu.icache.total_refs 37651093 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4401 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8555.122245 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 457261588 # The number of ROB reads +system.cpu.rob.rob_writes 691688263 # The number of ROB writes +system.cpu.timesIdled 1182 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 44123 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 172333316 # Number of Instructions Simulated +system.cpu.committedOps 188686798 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 172333316 # Number of Instructions Simulated +system.cpu.cpi 0.881048 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.881048 # CPI: Total CPI of All Threads +system.cpu.ipc 1.135013 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.135013 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1091959933 # number of integer regfile reads +system.cpu.int_regfile_writes 388658885 # number of integer regfile writes +system.cpu.fp_regfile_reads 2913610 # number of floating regfile reads +system.cpu.fp_regfile_writes 2511674 # number of floating regfile writes +system.cpu.misc_regfile_reads 474503072 # number of misc regfile reads +system.cpu.misc_regfile_writes 832154 # number of misc regfile writes +system.cpu.icache.replacements 2619 # number of replacements +system.cpu.icache.tagsinuse 1372.300046 # Cycle average of tags in use +system.cpu.icache.total_refs 37659845 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4361 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 8635.598487 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1370.154308 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.669021 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.669021 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 37651093 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 37651093 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 37651093 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 37651093 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 37651093 # number of overall hits -system.cpu.icache.overall_hits::total 37651093 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5221 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5221 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5221 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5221 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5221 # number of overall misses -system.cpu.icache.overall_misses::total 5221 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 109554000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 109554000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 109554000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 109554000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 109554000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 109554000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 37656314 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 37656314 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 37656314 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 37656314 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 37656314 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 37656314 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000139 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000139 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000139 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000139 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000139 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000139 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20983.336526 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20983.336526 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20983.336526 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20983.336526 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20983.336526 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20983.336526 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1372.300046 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.670068 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.670068 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 37659851 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 37659851 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 37659851 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 37659851 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 37659851 # number of overall hits +system.cpu.icache.overall_hits::total 37659851 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5086 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5086 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5086 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5086 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5086 # number of overall misses +system.cpu.icache.overall_misses::total 5086 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 90441000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 90441000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 90441000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 90441000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 90441000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 90441000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 37664937 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 37664937 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 37664937 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 37664937 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 37664937 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 37664937 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000135 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000135 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000135 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000135 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000135 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000135 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17782.343689 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17782.343689 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17782.343689 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17782.343689 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17782.343689 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17782.343689 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -392,246 +550,250 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 819 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 819 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 819 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 819 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 819 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 819 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4402 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4402 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4402 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4402 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4402 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4402 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 80099500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 80099500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 80099500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 80099500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 80099500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 80099500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000117 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000117 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000117 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18196.160836 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18196.160836 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18196.160836 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18196.160836 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18196.160836 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18196.160836 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 719 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 719 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 719 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 719 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 719 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 719 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4367 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4367 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4367 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4367 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4367 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4367 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 67648000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 67648000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 67648000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 67648000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 67648000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 67648000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000116 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000116 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000116 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15490.725899 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15490.725899 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15490.725899 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15490.725899 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15490.725899 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15490.725899 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 57 # number of replacements -system.cpu.dcache.tagsinuse 1414.265666 # Cycle average of tags in use -system.cpu.dcache.total_refs 47308069 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1866 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 25352.662915 # Average number of references to valid blocks. +system.cpu.dcache.replacements 59 # number of replacements +system.cpu.dcache.tagsinuse 1419.994069 # Cycle average of tags in use +system.cpu.dcache.total_refs 47294954 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1868 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 25318.497859 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1414.265666 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.345280 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.345280 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 34892726 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 34892726 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12356654 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12356654 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 30268 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 30268 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 28421 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 28421 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 47249380 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 47249380 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 47249380 # number of overall hits -system.cpu.dcache.overall_hits::total 47249380 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1980 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1980 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 7633 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 7633 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 1419.994069 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.346678 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.346678 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 34879202 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 34879202 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12356978 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12356978 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 30300 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 30300 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 28466 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 28466 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 47236180 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 47236180 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 47236180 # number of overall hits +system.cpu.dcache.overall_hits::total 47236180 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1958 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1958 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 7309 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 7309 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9613 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9613 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9613 # number of overall misses -system.cpu.dcache.overall_misses::total 9613 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 63002000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 63002000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 235161500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 235161500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 68000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 68000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 298163500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 298163500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 298163500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 298163500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 34894706 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 34894706 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9267 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9267 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9267 # number of overall misses +system.cpu.dcache.overall_misses::total 9267 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 54618000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 54618000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 158059500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 158059500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 66000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 66000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 212677500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 212677500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 212677500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 212677500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 34881160 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 34881160 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 30270 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 30270 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 28421 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 28421 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 47258993 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 47258993 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 47258993 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 47258993 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000057 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000057 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000617 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000617 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 30302 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 30302 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 28466 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 28466 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 47245447 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 47245447 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 47245447 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 47245447 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000056 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000056 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000591 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000591 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000066 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000066 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000203 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000203 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000203 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000203 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31819.191919 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 31819.191919 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30808.528757 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30808.528757 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 34000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 34000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31016.696141 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31016.696141 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31016.696141 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31016.696141 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.000196 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000196 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000196 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000196 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27894.790603 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 27894.790603 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21625.324942 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 21625.324942 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 33000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 33000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22949.983814 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22949.983814 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22949.983814 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22949.983814 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 9 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 8 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 9 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 8 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 18 # number of writebacks system.cpu.dcache.writebacks::total 18 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1197 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1197 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6550 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6550 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1172 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1172 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6221 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6221 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7747 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7747 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7747 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7747 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 783 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 783 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1083 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1083 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1866 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1866 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1866 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1866 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26488000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26488000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 38587500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 38587500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 65075500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 65075500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 65075500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 65075500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 7393 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7393 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7393 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7393 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 786 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 786 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1088 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1088 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1874 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1874 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1874 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1874 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23408500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23408500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 28137000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 28137000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 51545500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 51545500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 51545500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 51545500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000039 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000039 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33828.863346 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33828.863346 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35630.193906 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35630.193906 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34874.330118 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34874.330118 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34874.330118 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34874.330118 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29781.806616 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29781.806616 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25861.213235 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25861.213235 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27505.602988 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27505.602988 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27505.602988 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27505.602988 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 1997.690169 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2410 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2765 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.871609 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 1993.584817 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2372 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2758 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.860044 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3.999879 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1450.944432 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 542.745858 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000122 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.044279 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.016563 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 23276655 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 23276655 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53338835 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 43051148 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 96389983 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53338835 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 43051148 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 96389983 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.475361 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.866242 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.534965 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992613 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992613 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.475361 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.939507 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.614508 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.475361 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.939507 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.614508 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 25717.856798 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 29080.136765 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 26548.049383 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 21652.702326 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 21652.702326 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 25717.856798 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 24530.568661 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 25173.670149 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 25717.856798 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 24530.568661 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 25173.670149 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index d3a442923..17b1f3559 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,166 +1,325 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.084599 # Number of seconds simulated -sim_ticks 84599483500 # Number of ticks simulated -final_tick 84599483500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.084594 # Number of seconds simulated +sim_ticks 84594088000 # Number of ticks simulated +final_tick 84594088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 50330 # Simulator instruction rate (inst/s) -host_op_rate 84358 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32239425 # Simulator tick rate (ticks/s) -host_mem_usage 239332 # Number of bytes of host memory used -host_seconds 2624.10 # Real time elapsed on the host +host_inst_rate 94248 # Simulator instruction rate (inst/s) +host_op_rate 157968 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60367706 # Simulator tick rate (ticks/s) +host_mem_usage 238096 # Number of bytes of host memory used +host_seconds 1401.31 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221362960 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 220032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 124672 # Number of bytes read from this memory -system.physmem.bytes_read::total 344704 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 220032 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 220032 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3438 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1948 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5386 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2600867 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1473673 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4074540 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2600867 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2600867 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2600867 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1473673 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4074540 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 220544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 124864 # Number of bytes read from this memory +system.physmem.bytes_read::total 345408 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 220544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 220544 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3446 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1951 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5397 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2607085 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1476037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4083122 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2607085 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2607085 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2607085 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1476037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4083122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5399 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 5664 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 345408 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 345408 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 265 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 309 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 318 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 319 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 318 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 313 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 372 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 333 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 312 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 261 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 280 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 363 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 438 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 441 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 357 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 367 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 298 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 84594067000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 5399 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 265 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 4217 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 943 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 188 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 16379877 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 123109877 # Sum of mem lat for all requests +system.physmem.totBusLat 21596000 # Total cycles spent in databus access +system.physmem.totBankLat 85134000 # Total cycles spent in bank access +system.physmem.avgQLat 3033.87 # Average queueing delay per request +system.physmem.avgBankLat 15768.48 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 22802.35 # Average memory access latency +system.physmem.avgRdBW 4.08 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 4.08 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.00 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 4777 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 88.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 15668469.53 # Average gap between requests system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 169198968 # number of cpu cycles simulated +system.cpu.numCycles 169188177 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 20690463 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 20690463 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2250102 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 15079710 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 13739283 # Number of BTB hits +system.cpu.BPredUnit.lookups 20680258 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 20680258 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2246160 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 15085015 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 13721428 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 27218141 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 227440359 # Number of instructions fetch has processed -system.cpu.fetch.Branches 20690463 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13739283 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 59726319 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 19306281 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 65395131 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 224 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1651 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 25701311 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 473765 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 169122323 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.213301 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.334482 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27164568 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 227213982 # Number of instructions fetch has processed +system.cpu.fetch.Branches 20680258 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13721428 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 59660749 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 19257155 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 65568957 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 236 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1768 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 25653013 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 474244 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 169131808 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.211225 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.333765 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 111062519 65.67% 65.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3230504 1.91% 67.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2469579 1.46% 69.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3091757 1.83% 70.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3527779 2.09% 72.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3730060 2.21% 75.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4582508 2.71% 77.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2803800 1.66% 79.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 34623817 20.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 111136116 65.71% 65.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3216747 1.90% 67.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2468197 1.46% 69.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3082745 1.82% 70.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3525528 2.08% 72.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3731818 2.21% 75.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4565922 2.70% 77.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2807540 1.66% 79.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 34597195 20.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 169122323 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.122285 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.344218 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 40123368 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 55633776 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 46741593 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9842729 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 16780857 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 365282924 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 16780857 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 47679812 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14629061 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 22937 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 48366453 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 41643203 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 356095908 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 40 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 17377193 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22149388 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 410376112 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 987879370 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 977929387 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9949983 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 169131808 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.122232 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.342966 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 40083092 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 55790408 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 46646195 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9876583 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 16735530 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 364948187 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 16735530 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 47642140 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14699446 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 23267 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 48304644 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 41726781 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 355757826 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 35 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 17417112 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22198638 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 51 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 410011414 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 986948203 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 977030227 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9917976 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259428603 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 150947509 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1877 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1873 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 89979833 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 89683170 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 32866708 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 59054771 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 19177166 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 343137266 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5038 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 271920674 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 307949 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 121254430 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 247003349 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3792 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 169122323 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.607834 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.514763 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 150582811 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1844 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1841 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 90083407 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89641616 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 32814586 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 59002795 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 19228439 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 342836678 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4827 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 271794183 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 309279 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 120959244 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 246380396 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3581 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 169131808 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.606996 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.512238 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 47444811 28.05% 28.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 46907027 27.74% 55.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 33033517 19.53% 75.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20154930 11.92% 87.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 13461767 7.96% 95.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4965301 2.94% 98.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2426983 1.44% 99.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 577544 0.34% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 150443 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 47364329 28.00% 28.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 46969212 27.77% 55.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 33133132 19.59% 75.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20170100 11.93% 87.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 13409099 7.93% 95.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4965437 2.94% 98.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2407480 1.42% 99.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 564206 0.33% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 148813 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 169122323 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 169131808 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 134207 5.09% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2238473 84.87% 89.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 264949 10.04% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 133221 5.02% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2254463 85.01% 90.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 264273 9.97% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1212573 0.45% 0.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 177106081 65.13% 65.58% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.58% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1583088 0.58% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1212759 0.45% 0.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 177009113 65.13% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1584136 0.58% 66.16% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.16% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.16% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.16% # Type of FU issued @@ -186,84 +345,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.16% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.16% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.16% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 68507215 25.19% 91.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 23511717 8.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 68507132 25.21% 91.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 23481043 8.64% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 271920674 # Type of FU issued -system.cpu.iq.rate 1.607106 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2637629 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009700 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 710614385 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 460072874 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 264170911 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5294864 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4624558 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2540762 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 270691856 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2653874 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 19027871 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 271794183 # Type of FU issued +system.cpu.iq.rate 1.606461 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2651957 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009757 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 710390564 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 459507075 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 264054683 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 5290846 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4594594 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2539782 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 270581714 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2651667 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 19012084 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 33033584 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 33172 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 306303 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12350992 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 32992030 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 32876 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 306652 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12298870 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 49574 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 49471 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 16780857 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 570141 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 256886 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 343142304 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 262882 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 89683170 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 32866708 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1845 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 170649 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 30071 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 306303 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1331965 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1023841 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2355806 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 268743201 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 67386869 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3177473 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 16735530 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 583808 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 272322 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 342841505 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 257255 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 89641616 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 32814586 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1824 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 184475 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 30365 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 306652 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1330858 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1021453 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2352311 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 268621044 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 67379328 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3173139 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 90490770 # number of memory reference insts executed -system.cpu.iew.exec_branches 14773340 # Number of branches executed -system.cpu.iew.exec_stores 23103901 # Number of stores executed -system.cpu.iew.exec_rate 1.588326 # Inst execution rate -system.cpu.iew.wb_sent 267665043 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 266711673 # cumulative count of insts written-back -system.cpu.iew.wb_producers 215305025 # num instructions producing a value -system.cpu.iew.wb_consumers 378544002 # num instructions consuming a value +system.cpu.iew.exec_refs 90456785 # number of memory reference insts executed +system.cpu.iew.exec_branches 14766526 # Number of branches executed +system.cpu.iew.exec_stores 23077457 # Number of stores executed +system.cpu.iew.exec_rate 1.587706 # Inst execution rate +system.cpu.iew.wb_sent 267534302 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 266594465 # cumulative count of insts written-back +system.cpu.iew.wb_producers 215217179 # num instructions producing a value +system.cpu.iew.wb_consumers 378376353 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.576320 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.568771 # average fanout of values written-back +system.cpu.iew.wb_rate 1.575728 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.568791 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 121862932 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 121559121 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2250269 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 152341466 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.453071 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.928588 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2246323 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 152396278 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.452548 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.926116 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 52729760 34.61% 34.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57497101 37.74% 72.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14043120 9.22% 81.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11929275 7.83% 89.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4291590 2.82% 92.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2949185 1.94% 94.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1071112 0.70% 94.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 989747 0.65% 95.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6840576 4.49% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 52678390 34.57% 34.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57577424 37.78% 72.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14059718 9.23% 81.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11956991 7.85% 89.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4305123 2.82% 92.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2949818 1.94% 94.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1066386 0.70% 94.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 992195 0.65% 95.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6810233 4.47% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 152341466 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 152396278 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221362960 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -274,70 +433,70 @@ system.cpu.commit.branches 12326938 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339549 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6840576 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6810233 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 488726782 # The number of ROB reads -system.cpu.rob.rob_writes 703273689 # The number of ROB writes -system.cpu.timesIdled 1665 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 76645 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 488508126 # The number of ROB reads +system.cpu.rob.rob_writes 702620216 # The number of ROB writes +system.cpu.timesIdled 1506 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 56369 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221362960 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated -system.cpu.cpi 1.281119 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.281119 # CPI: Total CPI of All Threads -system.cpu.ipc 0.780567 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.780567 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 567776084 # number of integer regfile reads -system.cpu.int_regfile_writes 302793169 # number of integer regfile writes -system.cpu.fp_regfile_reads 3492670 # number of floating regfile reads -system.cpu.fp_regfile_writes 2212557 # number of floating regfile writes -system.cpu.misc_regfile_reads 139469476 # number of misc regfile reads +system.cpu.cpi 1.281038 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.281038 # CPI: Total CPI of All Threads +system.cpu.ipc 0.780617 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.780617 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 567639196 # number of integer regfile reads +system.cpu.int_regfile_writes 302703765 # number of integer regfile writes +system.cpu.fp_regfile_reads 3495797 # number of floating regfile reads +system.cpu.fp_regfile_writes 2211250 # number of floating regfile writes +system.cpu.misc_regfile_reads 139399302 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.icache.replacements 5445 # number of replacements -system.cpu.icache.tagsinuse 1641.882453 # Cycle average of tags in use -system.cpu.icache.total_refs 25692314 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 7414 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3465.378203 # Average number of references to valid blocks. +system.cpu.icache.replacements 5641 # number of replacements +system.cpu.icache.tagsinuse 1641.401127 # Cycle average of tags in use +system.cpu.icache.total_refs 25643925 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7612 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 3368.881372 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1641.882453 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.801700 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.801700 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25692314 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25692314 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25692314 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25692314 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25692314 # number of overall hits -system.cpu.icache.overall_hits::total 25692314 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8997 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8997 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8997 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8997 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8997 # number of overall misses -system.cpu.icache.overall_misses::total 8997 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 180939500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 180939500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 180939500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 180939500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 180939500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 180939500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25701311 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25701311 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25701311 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25701311 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25701311 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25701311 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000350 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000350 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000350 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000350 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000350 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000350 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20111.092586 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20111.092586 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20111.092586 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20111.092586 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20111.092586 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20111.092586 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1641.401127 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.801465 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.801465 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25643925 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25643925 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25643925 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25643925 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25643925 # number of overall hits +system.cpu.icache.overall_hits::total 25643925 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 9088 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 9088 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 9088 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 9088 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 9088 # number of overall misses +system.cpu.icache.overall_misses::total 9088 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 147639500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 147639500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 147639500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 147639500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 147639500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 147639500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25653013 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25653013 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25653013 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25653013 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25653013 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25653013 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000354 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000354 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000354 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000354 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000354 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000354 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16245.543574 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16245.543574 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16245.543574 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16245.543574 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16245.543574 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16245.543574 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -346,94 +505,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1358 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1358 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1358 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1358 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1358 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1358 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7639 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 7639 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 7639 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 7639 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 7639 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 7639 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 132852000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 132852000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 132852000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 132852000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 132852000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 132852000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000297 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000297 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000297 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000297 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000297 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000297 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17391.281581 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17391.281581 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17391.281581 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17391.281581 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17391.281581 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17391.281581 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1211 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1211 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1211 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1211 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1211 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1211 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7877 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 7877 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 7877 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 7877 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 7877 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 7877 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 110101000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 110101000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 110101000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 110101000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 110101000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 110101000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000307 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000307 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000307 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13977.529516 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13977.529516 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13977.529516 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13977.529516 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13977.529516 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13977.529516 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 56 # number of replacements -system.cpu.dcache.tagsinuse 1423.300553 # Cycle average of tags in use -system.cpu.dcache.total_refs 68703636 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1986 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34593.975831 # Average number of references to valid blocks. +system.cpu.dcache.replacements 57 # number of replacements +system.cpu.dcache.tagsinuse 1426.186042 # Cycle average of tags in use +system.cpu.dcache.total_refs 68712448 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1990 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34528.868342 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1423.300553 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.347485 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.347485 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 48189408 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 48189408 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513941 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513941 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 68703349 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 68703349 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 68703349 # number of overall hits -system.cpu.dcache.overall_hits::total 68703349 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 819 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 819 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1789 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1789 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2608 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2608 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2608 # number of overall misses -system.cpu.dcache.overall_misses::total 2608 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 26356000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 26356000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 66785500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 66785500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 93141500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 93141500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 93141500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 93141500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 48190227 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 48190227 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 1426.186042 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.348190 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.348190 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 48198272 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 48198272 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513902 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513902 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 68712174 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 68712174 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 68712174 # number of overall hits +system.cpu.dcache.overall_hits::total 68712174 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 735 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 735 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1828 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1828 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2563 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2563 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2563 # number of overall misses +system.cpu.dcache.overall_misses::total 2563 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 27231000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 27231000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 45096500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 45096500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 72327500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 72327500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 72327500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 72327500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 48199007 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 48199007 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 68705957 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 68705957 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 68705957 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 68705957 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000087 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000087 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000038 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000038 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000038 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000038 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32180.708181 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32180.708181 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37331.190609 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37331.190609 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35713.765337 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 35713.765337 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35713.765337 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35713.765337 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 68714737 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 68714737 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 68714737 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 68714737 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000015 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000015 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000037 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000037 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000037 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000037 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37048.979592 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 37048.979592 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24669.857768 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 24669.857768 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28219.859540 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28219.859540 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28219.859540 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28219.859540 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -442,140 +601,138 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 14 # number of writebacks -system.cpu.dcache.writebacks::total 14 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 394 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 394 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 396 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 396 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 396 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 396 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 425 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1787 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1787 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2212 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2212 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2212 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2212 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14781500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 14781500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 63139500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 63139500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 77921000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 77921000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 77921000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 77921000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 15 # number of writebacks +system.cpu.dcache.writebacks::total 15 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 302 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 302 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 4 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 4 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 306 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 306 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 306 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 306 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 433 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 433 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1824 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1824 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2257 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2257 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2257 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2257 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17292000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17292000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 41315500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 41315500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 58607500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 58607500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 58607500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 58607500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000087 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34780 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34780 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35332.680470 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35332.680470 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35226.491863 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 35226.491863 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35226.491863 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 35226.491863 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000033 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000033 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39935.334873 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39935.334873 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22651.041667 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22651.041667 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25966.991582 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25966.991582 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25966.991582 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25966.991582 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2567.757374 # Cycle average of tags in use -system.cpu.l2cache.total_refs 4009 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3834 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 1.045644 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2578.706153 # Cycle average of tags in use +system.cpu.l2cache.total_refs 4200 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3851 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 1.090626 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 1.880074 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2276.476463 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 289.400837 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000057 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.069473 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.008832 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.078362 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 3975 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::writebacks 1.137844 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2281.948056 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 295.620253 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000035 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.069640 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.009022 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.078696 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 4166 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 31 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 4006 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 14 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 14 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits +system.cpu.l2cache.ReadReq_hits::total 4197 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 15 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 15 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3975 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 4166 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 39 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 4014 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3975 # number of overall hits +system.cpu.l2cache.demand_hits::total 4205 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 4166 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 39 # number of overall hits -system.cpu.l2cache.overall_hits::total 4014 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3438 # 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average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 24746.270420 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 24764.514510 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 24714.079365 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 24746.270420 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |