diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-04-30 14:17:43 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-04-30 14:17:43 -0500 |
| commit | f71fa1715793c764ffa95411e87b73179a7c7b3f (patch) | |
| tree | b4095efe0bda4413326c5860754921b7d8ae78e3 /tests/long/se/70.twolf/ref | |
| parent | 42fe2df35495685e616f74ad3342953714c7dcc1 (diff) | |
| download | gem5-f71fa1715793c764ffa95411e87b73179a7c7b3f.tar.xz | |
stats: arm: updates
Diffstat (limited to 'tests/long/se/70.twolf/ref')
| -rw-r--r-- | tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt | 642 | ||||
| -rw-r--r-- | tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt | 1248 |
2 files changed, 945 insertions, 945 deletions
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index f50e78f71..fc0b314ed 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.131756 # Number of seconds simulated -sim_ticks 131756455500 # Number of ticks simulated -final_tick 131756455500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.131767 # Number of seconds simulated +sim_ticks 131767151500 # Number of ticks simulated +final_tick 131767151500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 150043 # Simulator instruction rate (inst/s) -host_op_rate 158169 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 114724713 # Simulator tick rate (ticks/s) -host_mem_usage 245376 # Number of bytes of host memory used -host_seconds 1148.46 # Real time elapsed on the host -sim_insts 172317809 # Number of instructions simulated -sim_ops 181650742 # Number of ops (including micro ops) simulated +host_inst_rate 176753 # Simulator instruction rate (inst/s) +host_op_rate 186327 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 135158895 # Simulator tick rate (ticks/s) +host_mem_usage 309748 # Number of bytes of host memory used +host_seconds 974.91 # Real time elapsed on the host +sim_insts 172317810 # Number of instructions simulated +sim_ops 181650743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 138304 # Number of bytes read from this memory @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 138304 # Nu system.physmem.num_reads::cpu.inst 2161 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory system.physmem.num_reads::total 3869 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1049694 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 829652 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1879346 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1049694 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1049694 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1049694 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 829652 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1879346 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1049609 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 829585 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1879194 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1049609 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1049609 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1049609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 829585 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1879194 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 3869 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 3869 # Number of DRAM read bursts, including those serviced by the write queue @@ -52,11 +52,11 @@ system.physmem.perBankRdBursts::7 222 # Pe system.physmem.perBankRdBursts::8 249 # Per bank write bursts system.physmem.perBankRdBursts::9 218 # Per bank write bursts system.physmem.perBankRdBursts::10 295 # Per bank write bursts -system.physmem.perBankRdBursts::11 201 # Per bank write bursts +system.physmem.perBankRdBursts::11 200 # Per bank write bursts system.physmem.perBankRdBursts::12 183 # Per bank write bursts system.physmem.perBankRdBursts::13 218 # Per bank write bursts system.physmem.perBankRdBursts::14 224 # Per bank write bursts -system.physmem.perBankRdBursts::15 204 # Per bank write bursts +system.physmem.perBankRdBursts::15 205 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 131756361000 # Total gap between requests +system.physmem.totGap 131767057000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3618 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 238 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3619 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 237 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 895 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 274.663687 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 183.028895 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 274.690311 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 245 27.37% 27.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 357 39.89% 67.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 81 9.05% 76.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 51 5.70% 82.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 43 4.80% 86.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 26 2.91% 89.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 22 2.46% 92.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 16 1.79% 93.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 54 6.03% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 895 # Bytes accessed per row activation -system.physmem.totQLat 26795500 # Total ticks spent queuing -system.physmem.totMemAccLat 99339250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 907 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 272.793826 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 180.627814 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 276.033343 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 260 28.67% 28.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 352 38.81% 67.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 83 9.15% 76.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 54 5.95% 82.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 42 4.63% 87.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 20 2.21% 89.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 22 2.43% 91.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 19 2.09% 93.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 55 6.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 907 # Bytes accessed per row activation +system.physmem.totQLat 28218000 # Total ticks spent queuing +system.physmem.totMemAccLat 100761750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 19345000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6925.69 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7293.36 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25675.69 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26043.36 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s @@ -216,49 +216,49 @@ system.physmem.busUtilRead 0.01 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 2968 # Number of row buffer hits during reads +system.physmem.readRowHits 2961 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.71 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.53 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34054370.90 # Average gap between requests -system.physmem.pageHitRate 76.71 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3069360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1674750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 16169400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 34057135.44 # Average gap between requests +system.physmem.pageHitRate 76.53 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3114720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1699500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16200600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 8605343760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3539591415 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 75945924750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 88111773435 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.773046 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 126343729250 # Time in different power states -system.physmem_0.memoryStateTime::REF 4399460000 # Time in different power states +system.physmem_0.refreshEnergy 8606360880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3598001595 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 75904039500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 88129416795 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.827838 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 126271035750 # Time in different power states +system.physmem_0.memoryStateTime::REF 4399980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1010946750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1095966750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3681720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2008875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 13774800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3742200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2041875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13954200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 8605343760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3587668065 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 75903760500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 88116237720 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.806861 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 126271447000 # Time in different power states -system.physmem_1.memoryStateTime::REF 4399460000 # Time in different power states +system.physmem_1.refreshEnergy 8606360880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3577878315 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 75921691500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 88125668970 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.799395 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 126300767500 # Time in different power states +system.physmem_1.memoryStateTime::REF 4399980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1080937500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1066235000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 49934475 # Number of BP lookups -system.cpu.branchPred.condPredicted 39666705 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5743450 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24374227 # Number of BTB lookups -system.cpu.branchPred.BTBHits 23299942 # Number of BTB hits +system.cpu.branchPred.lookups 49934214 # Number of BP lookups +system.cpu.branchPred.condPredicted 39669228 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5745476 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 24397430 # Number of BTB lookups +system.cpu.branchPred.BTBHits 23302007 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.592537 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1908561 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 139 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 95.510089 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1908013 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 140 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -377,24 +377,24 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 263512911 # number of cpu cycles simulated +system.cpu.numCycles 263534303 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 172317809 # Number of instructions committed -system.cpu.committedOps 181650742 # Number of ops (including micro ops) committed -system.cpu.discardedOps 11759003 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 172317810 # Number of instructions committed +system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed +system.cpu.discardedOps 11762366 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.529226 # CPI: cycles per instruction -system.cpu.ipc 0.653925 # IPC: instructions per cycle -system.cpu.tickCycles 257129929 # Number of cycles that the object actually ticked -system.cpu.idleCycles 6382982 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.529350 # CPI: cycles per instruction +system.cpu.ipc 0.653872 # IPC: instructions per cycle +system.cpu.tickCycles 257146871 # Number of cycles that the object actually ticked +system.cpu.idleCycles 6387432 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1377.698550 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40765676 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1377.696434 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40764379 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22522.472928 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22521.756354 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1377.698550 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1377.696434 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.336352 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.336352 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id @@ -404,72 +404,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1358 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.431641 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 81538034 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 81538034 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 28357756 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28357756 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 81535444 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 81535444 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28356460 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28356460 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 12362641 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 12362641 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 465 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 465 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 464 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 464 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40720397 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40720397 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40720862 # number of overall hits -system.cpu.dcache.overall_hits::total 40720862 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 789 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 789 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 40719101 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40719101 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40719565 # number of overall hits +system.cpu.dcache.overall_hits::total 40719565 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 791 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 791 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1646 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 1646 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 2435 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2435 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2436 # number of overall misses -system.cpu.dcache.overall_misses::total 2436 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57528734 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57528734 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 127304750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 127304750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 184833484 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 184833484 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 184833484 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 184833484 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28358545 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28358545 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2437 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2437 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2438 # number of overall misses +system.cpu.dcache.overall_misses::total 2438 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 59434234 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 59434234 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 127677000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 127677000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 187111234 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 187111234 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 187111234 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 187111234 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28357251 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28357251 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 466 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 466 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 465 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 465 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 40722832 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 40722832 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 40723298 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 40723298 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 40721538 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 40721538 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 40722003 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 40722003 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000133 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002146 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.002146 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002151 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.002151 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72913.477820 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72913.477820 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77341.889429 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 77341.889429 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 75906.974949 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 75906.974949 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 75875.814450 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 75875.814450 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75138.096081 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 75138.096081 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77568.043742 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77568.043742 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76779.332786 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76779.332786 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76747.840033 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76747.840033 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -480,14 +480,14 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 16 # number of writebacks system.cpu.dcache.writebacks::total 16 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 80 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 548 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 548 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 626 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 626 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 626 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 626 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 628 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 628 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 628 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 628 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1098 # number of WriteReq MSHR misses @@ -498,91 +498,91 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1809 system.cpu.dcache.demand_mshr_misses::total 1809 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1810 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51124264 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 51124264 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85250250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 85250250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52911264 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 52911264 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85210500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85210500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 69500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 69500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136374514 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 136374514 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136444014 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 136444014 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 138121764 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 138121764 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138191264 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 138191264 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002146 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002146 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002151 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002151 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71904.731364 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71904.731364 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77641.393443 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77641.393443 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74418.092827 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74418.092827 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77605.191257 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77605.191257 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 69500 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 69500 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75386.685462 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75386.685462 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75383.433149 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75383.433149 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76352.550580 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76352.550580 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76348.764641 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76348.764641 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 2891 # number of replacements -system.cpu.icache.tags.tagsinuse 1424.909257 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 71597353 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4688 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 15272.472910 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2892 # number of replacements +system.cpu.icache.tags.tagsinuse 1425.992142 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 71598587 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4690 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 15266.223241 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1424.909257 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.695756 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.695756 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1425.992142 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.696285 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.696285 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1798 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 490 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 129 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1067 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.877441 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 143208772 # Number of tag accesses -system.cpu.icache.tags.data_accesses 143208772 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 71597353 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 71597353 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 71597353 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 71597353 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 71597353 # number of overall hits -system.cpu.icache.overall_hits::total 71597353 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4689 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4689 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4689 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4689 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4689 # number of overall misses -system.cpu.icache.overall_misses::total 4689 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 200357248 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 200357248 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 200357248 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 200357248 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 200357248 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 200357248 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 71602042 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 71602042 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 71602042 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 71602042 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 71602042 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 71602042 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000065 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000065 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000065 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000065 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000065 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000065 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42729.206227 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42729.206227 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42729.206227 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42729.206227 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42729.206227 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42729.206227 # average overall miss latency +system.cpu.icache.tags.age_task_id_blocks_1024::3 128 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1069 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.877930 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 143211246 # Number of tag accesses +system.cpu.icache.tags.data_accesses 143211246 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 71598587 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 71598587 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 71598587 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 71598587 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 71598587 # number of overall hits +system.cpu.icache.overall_hits::total 71598587 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4691 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4691 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4691 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4691 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4691 # number of overall misses +system.cpu.icache.overall_misses::total 4691 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 200040248 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 200040248 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 200040248 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 200040248 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 200040248 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 200040248 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 71603278 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 71603278 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 71603278 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 71603278 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 71603278 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 71603278 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42643.412492 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42643.412492 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42643.412492 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42643.412492 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42643.412492 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42643.412492 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -591,66 +591,66 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4689 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4689 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4689 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4689 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4689 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4689 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192396752 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 192396752 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192396752 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 192396752 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192396752 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 192396752 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000065 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000065 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000065 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41031.510343 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41031.510343 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41031.510343 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 41031.510343 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41031.510343 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 41031.510343 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4691 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4691 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4691 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4691 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4691 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4691 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192077752 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 192077752 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192077752 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 192077752 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192077752 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 192077752 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40946.014069 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40946.014069 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40946.014069 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 40946.014069 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40946.014069 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 40946.014069 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2001.520504 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2606 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2003.582702 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2608 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2787 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.935056 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.935773 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 3.029170 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.676370 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 490.814964 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 3.029186 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1509.739376 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 490.814139 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046011 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046074 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.014978 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.061082 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.061144 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 2787 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 520 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 157 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2005 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 155 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2007 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.085052 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 56005 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 56005 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2525 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 56021 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 56021 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 2527 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 80 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2605 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2607 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2525 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 2527 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 88 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2613 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2525 # number of overall hits +system.cpu.l2cache.demand_hits::total 2615 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2527 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 88 # number of overall hits -system.cpu.l2cache.overall_hits::total 2613 # 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miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.951381 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.597938 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461506 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.597754 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461309 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.951381 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.597938 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74489.949168 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78539.952532 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75405.400572 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77125.458716 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77125.458716 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74489.949168 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77644.599303 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75887.866701 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74489.949168 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77644.599303 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75887.866701 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.597754 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74331.908503 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81367.484177 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75922.210300 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77088.990826 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77088.990826 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74331.908503 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78659.262485 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76249.485332 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74331.908503 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78659.262485 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76249.485332 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -736,70 +736,70 @@ system.cpu.l2cache.demand_mshr_misses::total 3870 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2162 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3870 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134003000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 40696500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 174699500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70437750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70437750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134003000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 111134250 # 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mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992714 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.460883 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.595476 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.595293 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.460883 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.595476 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61981.036078 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65851.941748 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62841.546763 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64621.788991 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64621.788991 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61981.036078 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65066.891101 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63342.958656 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61981.036078 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65066.891101 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63342.958656 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.595293 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61824.468085 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68751.618123 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63364.388489 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64585.321101 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64585.321101 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61824.468085 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66092.798595 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63708.268734 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61824.468085 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66092.798595 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63708.268734 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 5401 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5400 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 5403 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5402 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9377 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9381 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3636 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 13013 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 13017 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300160 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 416896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 417024 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6515 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 6517 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 6515 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 6517 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6515 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3273500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 6517 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3274500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7496248 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7498748 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3020486 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3019736 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.trans_dist::ReadReq 2779 # Transaction distribution system.membus.trans_dist::ReadResp 2779 # Transaction distribution @@ -820,9 +820,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 3869 # Request fanout histogram -system.membus.reqLayer0.occupancy 4526500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4517000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 20559750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20556500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 3b1c45895..e84c7e623 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.085027 # Number of seconds simulated -sim_ticks 85027009000 # Number of ticks simulated -final_tick 85027009000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.085032 # Number of seconds simulated +sim_ticks 85032044000 # Number of ticks simulated +final_tick 85032044000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 123827 # Simulator instruction rate (inst/s) -host_op_rate 130534 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61105425 # Simulator tick rate (ticks/s) -host_mem_usage 242728 # Number of bytes of host memory used -host_seconds 1391.48 # Real time elapsed on the host -sim_insts 172303021 # Number of instructions simulated -sim_ops 181635953 # Number of ops (including micro ops) simulated +host_inst_rate 98638 # Simulator instruction rate (inst/s) +host_op_rate 103981 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48678127 # Simulator tick rate (ticks/s) +host_mem_usage 307440 # Number of bytes of host memory used +host_seconds 1746.82 # Real time elapsed on the host +sim_insts 172303022 # Number of instructions simulated +sim_ops 181635954 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 127040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 47680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 71040 # Number of bytes read from this memory -system.physmem.bytes_read::total 245760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 47488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 71360 # Number of bytes read from this memory +system.physmem.bytes_read::total 245888 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 127040 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 127040 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 1985 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 745 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 1110 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3840 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1494113 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 560763 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 835499 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2890376 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1494113 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1494113 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1494113 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 560763 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 835499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2890376 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3840 # Number of read requests accepted +system.physmem.num_reads::cpu.data 742 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 1115 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3842 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1494025 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 558472 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 839213 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2891710 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1494025 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1494025 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1494025 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 558472 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 839213 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2891710 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3842 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 3840 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 3842 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 245760 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 245888 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 245760 # Total read bytes from the system interface side +system.physmem.bytesReadSys 245888 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -48,11 +48,11 @@ system.physmem.neitherReadNorWriteReqs 0 # Nu system.physmem.perBankRdBursts::0 309 # Per bank write bursts system.physmem.perBankRdBursts::1 220 # Per bank write bursts system.physmem.perBankRdBursts::2 142 # Per bank write bursts -system.physmem.perBankRdBursts::3 304 # Per bank write bursts +system.physmem.perBankRdBursts::3 310 # Per bank write bursts system.physmem.perBankRdBursts::4 300 # Per bank write bursts system.physmem.perBankRdBursts::5 302 # Per bank write bursts system.physmem.perBankRdBursts::6 262 # Per bank write bursts -system.physmem.perBankRdBursts::7 237 # Per bank write bursts +system.physmem.perBankRdBursts::7 233 # Per bank write bursts system.physmem.perBankRdBursts::8 252 # Per bank write bursts system.physmem.perBankRdBursts::9 219 # Per bank write bursts system.physmem.perBankRdBursts::10 292 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 85026865500 # Total gap between requests +system.physmem.totGap 85031900500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 3840 # Read request sizes (log2) +system.physmem.readPktSize::6 3842 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,16 +94,16 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2543 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 851 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 162 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 86 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2554 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 839 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 163 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 88 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 40 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 36 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -190,26 +190,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 767 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 319.332464 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 200.822648 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 307.559029 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 236 30.77% 30.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 188 24.51% 55.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 81 10.56% 65.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 90 11.73% 77.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 32 4.17% 81.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 41 5.35% 87.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 12 1.56% 88.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 16 2.09% 90.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 71 9.26% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 767 # Bytes accessed per row activation -system.physmem.totQLat 42919435 # Total ticks spent queuing -system.physmem.totMemAccLat 114919435 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 19200000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11176.94 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 763 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 320.083879 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 201.433795 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 309.783352 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 232 30.41% 30.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 191 25.03% 55.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 88 11.53% 66.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 86 11.27% 78.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 27 3.54% 81.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 37 4.85% 86.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 11 1.44% 88.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 17 2.23% 90.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 74 9.70% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 763 # Bytes accessed per row activation +system.physmem.totQLat 43141443 # Total ticks spent queuing +system.physmem.totMemAccLat 115178943 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 19210000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11228.90 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29926.94 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 29978.90 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.89 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.89 # Average system read bandwidth in MiByte/s @@ -218,51 +218,51 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgRdQLen 2.30 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 3071 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.97 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.93 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 22142412.89 # Average gap between requests -system.physmem.pageHitRate 79.97 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2691360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1468500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 16192800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 22132196.90 # Average gap between requests +system.physmem.pageHitRate 79.93 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2729160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1489125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16177200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 5553475200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2327866605 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 48973677750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 56875372215 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.916551 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 81470624236 # Time in different power states +system.physmem_0.actBackEnergy 2330695800 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 48971187750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 56875754235 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.921152 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 81466351731 # Time in different power states system.physmem_0.memoryStateTime::REF 2839200000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 716299514 # Time in different power states +system.physmem_0.memoryStateTime::ACT 720558269 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3107160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1695375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 13657800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3016440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1645875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13548600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 5553475200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2285718525 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 49010649750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 56868303810 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.833418 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 81532427147 # Time in different power states +system.physmem_1.actBackEnergy 2293230555 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 49004052000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 56868968670 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.841346 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 81522647918 # Time in different power states system.physmem_1.memoryStateTime::REF 2839200000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 654496603 # Time in different power states +system.physmem_1.memoryStateTime::ACT 665486082 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 85926168 # Number of BP lookups -system.cpu.branchPred.condPredicted 68405800 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6016539 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 40105937 # Number of BTB lookups -system.cpu.branchPred.BTBHits 39014203 # Number of BTB hits +system.cpu.branchPred.lookups 85925704 # Number of BP lookups +system.cpu.branchPred.condPredicted 68401753 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6018362 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 40106814 # Number of BTB lookups +system.cpu.branchPred.BTBHits 39018678 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.277874 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3700977 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 81896 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.286905 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3705148 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 81894 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -381,96 +381,96 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 170054019 # number of cpu cycles simulated +system.cpu.numCycles 170064089 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5612946 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 349281739 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85926168 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42715180 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 158272644 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 12047045 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1757 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 5613343 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 349288276 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85925704 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42723826 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 158284040 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 12050671 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1737 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 2232 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 78951619 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 17953 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 169913124 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.150597 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.047113 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 2225 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 78959765 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 17996 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 169926703 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.150511 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.047128 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 17360928 10.22% 10.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30199989 17.77% 27.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31841897 18.74% 46.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 90510310 53.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 17361476 10.22% 10.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30212798 17.78% 28.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31840839 18.74% 46.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 90511590 53.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 169913124 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.505287 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.053946 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17565564 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 17109843 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 122664763 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6724358 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5848596 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11135936 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 189930 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 306620744 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27649027 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5848596 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37751386 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8466295 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 579465 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 108929053 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8338329 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 278664885 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13415182 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3050613 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 842331 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2187361 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 37352 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 26454 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 483122463 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1196977553 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 297589838 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3006277 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 169926703 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.505255 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.053863 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17566577 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 17110905 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 122676579 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6722207 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5850435 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11136607 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 190140 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 306627324 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27647944 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5850435 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37756146 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8468505 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 579113 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 108935441 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8337063 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 278668040 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13416082 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3052051 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 841470 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2187697 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 36000 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 26450 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 483113762 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1196983953 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 297587542 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3006013 # Number of floating rename lookups system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 190145534 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 23528 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23432 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13338171 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 34140942 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14477069 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2549253 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1790153 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 264824262 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 45858 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 214907174 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5191222 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 83234167 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 219950944 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 642 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 169913124 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.264806 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.017451 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 190136833 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 23525 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23424 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13336678 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 34143660 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14476609 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2548114 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1810648 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 264825192 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 45854 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 214913936 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5193552 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 83235092 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 219939501 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 638 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 169926703 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.264745 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.017460 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52840350 31.10% 31.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 36091754 21.24% 52.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 65793999 38.72% 91.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 13568282 7.99% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1571301 0.92% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 47256 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 182 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52848454 31.10% 31.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 36099011 21.24% 52.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 65787739 38.72% 91.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13574201 7.99% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1569834 0.92% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 47276 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 188 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 169913124 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 169926703 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35600908 66.11% 66.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 152918 0.28% 66.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35606881 66.11% 66.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 152777 0.28% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.39% # attempts to use FU when none available @@ -489,22 +489,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.39% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 1064 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 35736 0.07% 66.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 241 0.00% 66.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 1069 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 35731 0.07% 66.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 243 0.00% 66.46% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 1033 0.00% 66.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 34370 0.06% 66.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 1036 0.00% 66.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 34373 0.06% 66.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 14078817 26.14% 92.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3947857 7.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 14081261 26.14% 92.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3945561 7.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 167349433 77.87% 77.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 918954 0.43% 78.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 167354642 77.87% 77.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 918991 0.43% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.30% # Type of FU issued @@ -523,105 +523,105 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.30% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33017 0.02% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33018 0.02% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 165198 0.08% 78.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 245711 0.11% 78.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 165174 0.08% 78.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 245708 0.11% 78.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 460497 0.21% 78.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206696 0.10% 78.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 460494 0.21% 78.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206680 0.10% 78.85% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 32005154 14.89% 93.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13374554 6.22% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 32007537 14.89% 93.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13373732 6.22% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 214907174 # Type of FU issued -system.cpu.iq.rate 1.263758 # Inst issue rate -system.cpu.iq.fu_busy_cnt 53853149 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.250588 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 654819591 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 346099299 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 204603377 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3952252 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2011948 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1806382 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266627232 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2133091 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1600790 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 214913936 # Type of FU issued +system.cpu.iq.rate 1.263723 # Inst issue rate +system.cpu.iq.fu_busy_cnt 53859137 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.250608 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 654855291 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 346101904 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 204603491 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3951973 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2011176 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1806361 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266640239 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2132834 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1601131 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6244798 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7531 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7120 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1832435 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6247516 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7571 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7104 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1831975 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 25844 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 768 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 25920 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 745 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5848596 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5681557 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 36821 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 264886087 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 5850435 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5682032 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 37041 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 264886958 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 34140942 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14477069 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23450 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3913 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 29719 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7120 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3233413 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3247375 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6480788 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 207526427 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 30720305 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7380747 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 34143660 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14476609 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23446 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3875 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 29998 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 7104 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3234550 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3248118 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6482668 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 207528127 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 30721496 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7385809 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 15967 # number of nop insts executed -system.cpu.iew.exec_refs 43860812 # number of memory reference insts executed -system.cpu.iew.exec_branches 44937004 # Number of branches executed -system.cpu.iew.exec_stores 13140507 # Number of stores executed -system.cpu.iew.exec_rate 1.220356 # Inst execution rate -system.cpu.iew.wb_sent 206744573 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 206409759 # cumulative count of insts written-back -system.cpu.iew.wb_producers 129475490 # num instructions producing a value -system.cpu.iew.wb_consumers 221697589 # num instructions consuming a value +system.cpu.iew.exec_nop 15912 # number of nop insts executed +system.cpu.iew.exec_refs 43861162 # number of memory reference insts executed +system.cpu.iew.exec_branches 44936179 # Number of branches executed +system.cpu.iew.exec_stores 13139666 # Number of stores executed +system.cpu.iew.exec_rate 1.220294 # Inst execution rate +system.cpu.iew.wb_sent 206744895 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 206409852 # cumulative count of insts written-back +system.cpu.iew.wb_producers 129477271 # num instructions producing a value +system.cpu.iew.wb_consumers 221697359 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.213789 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.584018 # average fanout of values written-back +system.cpu.iew.wb_rate 1.213718 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.584027 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 69541306 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 69541697 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5841613 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158471260 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.146267 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.646384 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5843462 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158482976 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.146182 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.646662 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 73683520 46.50% 46.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 41279039 26.05% 72.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 22557642 14.23% 86.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9629639 6.08% 92.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3553008 2.24% 95.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2147976 1.36% 96.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1280790 0.81% 97.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 986719 0.62% 97.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3352927 2.12% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 73704941 46.51% 46.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 41274815 26.04% 72.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 22552900 14.23% 86.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9628649 6.08% 92.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3549516 2.24% 95.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2148015 1.36% 96.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1280291 0.81% 97.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 986897 0.62% 97.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3356952 2.12% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158471260 # Number of insts commited each cycle -system.cpu.commit.committedInsts 172317409 # Number of instructions committed -system.cpu.commit.committedOps 181650341 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 158482976 # Number of insts commited each cycle +system.cpu.commit.committedInsts 172317410 # Number of instructions committed +system.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 40540778 # Number of memory references committed system.cpu.commit.loads 27896144 # Number of loads committed system.cpu.commit.membars 22408 # Number of memory barriers committed -system.cpu.commit.branches 40300311 # Number of branches committed +system.cpu.commit.branches 40300312 # Number of branches committed system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. system.cpu.commit.int_insts 143085667 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 138987812 76.51% 76.51% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 138987813 76.51% 76.51% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 77.01% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 77.01% # Class of committed instruction @@ -654,186 +654,186 @@ system.cpu.commit.op_class_0::MemRead 27896144 15.36% 93.04% # Cl system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 181650341 # Class of committed instruction -system.cpu.commit.bw_lim_events 3352927 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 406304779 # The number of ROB reads -system.cpu.rob.rob_writes 513839131 # The number of ROB writes -system.cpu.timesIdled 3408 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 140895 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 172303021 # Number of Instructions Simulated -system.cpu.committedOps 181635953 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.986947 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.986947 # CPI: Total CPI of All Threads -system.cpu.ipc 1.013225 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.013225 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 218958782 # number of integer regfile reads -system.cpu.int_regfile_writes 114515411 # number of integer regfile writes -system.cpu.fp_regfile_reads 2904346 # number of floating regfile reads -system.cpu.fp_regfile_writes 2441525 # number of floating regfile writes -system.cpu.cc_regfile_reads 709584302 # number of cc regfile reads -system.cpu.cc_regfile_writes 229541480 # number of cc regfile writes -system.cpu.misc_regfile_reads 59315386 # number of misc regfile reads +system.cpu.commit.op_class_0::total 181650342 # Class of committed instruction +system.cpu.commit.bw_lim_events 3356952 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 406312862 # The number of ROB reads +system.cpu.rob.rob_writes 513841850 # The number of ROB writes +system.cpu.timesIdled 3415 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 137386 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 172303022 # Number of Instructions Simulated +system.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.987006 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.987006 # CPI: Total CPI of All Threads +system.cpu.ipc 1.013165 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.013165 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 218961575 # number of integer regfile reads +system.cpu.int_regfile_writes 114515726 # number of integer regfile writes +system.cpu.fp_regfile_reads 2904225 # number of floating regfile reads +system.cpu.fp_regfile_writes 2441500 # number of floating regfile writes +system.cpu.cc_regfile_reads 709589041 # number of cc regfile reads +system.cpu.cc_regfile_writes 229545726 # number of cc regfile writes +system.cpu.misc_regfile_reads 59313943 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.dcache.tags.replacements 72889 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.417696 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 41115745 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 73401 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 560.152382 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 72899 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.418278 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 41116599 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 73411 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 560.087712 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 506067250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.417696 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998863 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998863 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 511.418278 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998864 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998864 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 165 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 226 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 42 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 82529901 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 82529901 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 28729389 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28729389 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12341441 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12341441 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 82531693 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 82531693 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28730266 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28730266 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12341417 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12341417 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 361 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 361 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22147 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22147 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22148 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22148 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41070830 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41070830 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41071191 # number of overall hits -system.cpu.dcache.overall_hits::total 41071191 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89283 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89283 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 22846 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 22846 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 116 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 116 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 41071683 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41071683 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41072044 # number of overall hits +system.cpu.dcache.overall_hits::total 41072044 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89294 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89294 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 22870 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22870 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 118 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 118 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 260 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 260 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 112129 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 112129 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 112245 # number of overall misses -system.cpu.dcache.overall_misses::total 112245 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 853218237 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 853218237 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 244809935 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 244809935 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 112164 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 112164 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 112282 # number of overall misses +system.cpu.dcache.overall_misses::total 112282 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 853196487 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 853196487 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 241173427 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 241173427 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2319500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 2319500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1098028172 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1098028172 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1098028172 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1098028172 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28818672 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28818672 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 1094369914 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1094369914 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1094369914 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1094369914 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28819560 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28819560 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 477 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 477 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 479 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 479 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22408 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22408 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41182959 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41182959 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41183436 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41183436 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 41183847 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41183847 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41184326 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41184326 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003098 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003098 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001848 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001848 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.243187 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.243187 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011604 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011604 # miss rate for LoadLockedReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001850 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001850 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.246347 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.246347 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011603 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011603 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.002723 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.002723 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002725 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002725 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9556.334767 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9556.334767 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10715.658540 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10715.658540 # average WriteReq miss latency +system.cpu.dcache.overall_miss_rate::cpu.data 0.002726 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002726 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9554.913958 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9554.913958 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10545.405641 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10545.405641 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8921.153846 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8921.153846 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9792.544052 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9792.544052 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9782.423912 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9782.423912 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9756.873097 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9756.873097 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9746.619351 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9746.619351 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 167 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 10490 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 9765 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 844 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 848 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.500000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 12.428910 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 11.515330 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 64871 # number of writebacks -system.cpu.dcache.writebacks::total 64871 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24560 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 24560 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14281 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 14281 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 64878 # number of writebacks +system.cpu.dcache.writebacks::total 64878 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24567 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 24567 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14301 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 14301 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 260 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 260 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 38841 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 38841 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 38841 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 38841 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64723 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64723 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8565 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 8565 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 113 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 113 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 73288 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 73288 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 73401 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 73401 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 526941010 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 526941010 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 81775757 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 81775757 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 905500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 905500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 608716767 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 608716767 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 609622267 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 609622267 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 38868 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 38868 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 38868 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 38868 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64727 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 64727 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8569 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 8569 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 115 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 115 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 73296 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 73296 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 73411 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 73411 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 526755010 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 526755010 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 81248758 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 81248758 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 920500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 920500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 608003768 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 608003768 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 608924268 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 608924268 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002246 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002246 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000693 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000693 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.236897 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.236897 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.240084 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.240084 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001780 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.001780 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001782 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001782 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8141.479999 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8141.479999 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9547.665733 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9547.665733 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8013.274336 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8013.274336 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8305.817692 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 8305.817692 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8305.367325 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 8305.367325 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8138.103264 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8138.103264 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9481.708251 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9481.708251 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8004.347826 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8004.347826 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8295.183475 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8295.183475 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8294.727875 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8294.727875 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 54441 # number of replacements -system.cpu.icache.tags.tagsinuse 510.602621 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 78893897 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 54953 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1435.661329 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 84271974250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.602621 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997271 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997271 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 54462 # number of replacements +system.cpu.icache.tags.tagsinuse 510.603252 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78902001 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 54974 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1435.260323 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 84278847250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.603252 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997272 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997272 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id @@ -841,188 +841,188 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 272 system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 48 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 157958145 # Number of tag accesses -system.cpu.icache.tags.data_accesses 157958145 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 78893897 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78893897 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78893897 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78893897 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78893897 # number of overall hits -system.cpu.icache.overall_hits::total 78893897 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 57699 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 57699 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 57699 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 57699 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 57699 # number of overall misses -system.cpu.icache.overall_misses::total 57699 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 607673936 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 607673936 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 607673936 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 607673936 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 607673936 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 607673936 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78951596 # 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average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70120.489245 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68483.547464 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74454.466755 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70120.489245 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1043,116 +1043,116 @@ system.cpu.l2cache.overall_mshr_hits::cpu.inst 6 system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1985 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 507 # 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number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 70744400 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15940250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15940250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 119139257 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 48849500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 167988757 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 119139257 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 48849500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 70744400 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 238733157 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.036108 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.007796 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.020793 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027559 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027559 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.036122 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.010150 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.021269 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.036122 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.010150 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027443 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027443 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.036108 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.010107 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.021241 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.036108 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.010107 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.035355 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60551.012091 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65340.729783 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61525.485152 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37943.132743 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 37943.132743 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69349.789916 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69349.789916 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60551.012091 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66621.476510 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62207.604029 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60551.012091 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66621.476510 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37943.132743 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52540.313574 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.035300 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60019.776826 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65166.831683 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61063.657430 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 39193.573407 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 39193.573407 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67258.438819 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67258.438819 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60019.776826 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65834.905660 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61602.037770 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60019.776826 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65834.905660 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 39193.573407 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52677.219109 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 119718 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 119718 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 64871 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 2155 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 119749 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 119749 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 64878 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 2153 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 8636 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 8636 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 109906 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 211673 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 321579 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3516992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8849408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 12366400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2155 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 195380 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.011030 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.104442 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 109948 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 211700 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 321648 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3518336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8850496 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 12368832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2153 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 195416 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.011018 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.104385 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 193225 98.90% 98.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 2155 1.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 193263 98.90% 98.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 2153 1.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 195380 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 161483500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 195416 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 161509500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 82836732 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 82870477 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 110205232 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 110219231 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadReq 3602 # Transaction distribution -system.membus.trans_dist::ReadResp 3602 # Transaction distribution -system.membus.trans_dist::ReadExReq 238 # Transaction distribution -system.membus.trans_dist::ReadExResp 238 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7680 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 245760 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 245760 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 3605 # Transaction distribution +system.membus.trans_dist::ReadResp 3605 # Transaction distribution +system.membus.trans_dist::ReadExReq 237 # Transaction distribution +system.membus.trans_dist::ReadExResp 237 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7684 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7684 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 245888 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 245888 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3840 # Request fanout histogram +system.membus.snoop_fanout::samples 3842 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3840 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3842 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3840 # Request fanout histogram -system.membus.reqLayer0.occupancy 4975502 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3842 # Request fanout histogram +system.membus.reqLayer0.occupancy 4969720 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 20238053 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20244552 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |