diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-06-22 14:33:09 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-06-22 14:33:09 -0700 |
| commit | 5b08e211ab35fd6d936dafda45014c78b5e68300 (patch) | |
| tree | 771950b6f1e0c775d83a5f03f2387f2e3850cc58 /tests/long/se/70.twolf/ref | |
| parent | b085db84afcbb4824d34b8755f4c09c1fcfefcee (diff) | |
| download | gem5-5b08e211ab35fd6d936dafda45014c78b5e68300.tar.xz | |
stats: update for O3 changes
Mostly small differences in total ticks, but O3 stall causes
shifted significantly.
30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8%
slower.
Diffstat (limited to 'tests/long/se/70.twolf/ref')
9 files changed, 2071 insertions, 2026 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 78509c3e8..104ffdb52 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -115,6 +116,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -599,7 +601,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/cpu2000/binaries/alpha/tru64/twolf +executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 @@ -628,9 +630,9 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -641,27 +643,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout index c12c73ccb..2cc52ce3f 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -1,12 +1,12 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 16:27:55 -gem5 started Jan 22 2014 19:15:16 -gem5 executing on u200540-lin -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2 +gem5 compiled Jun 21 2014 10:36:29 +gem5 started Jun 21 2014 12:55:52 +gem5 executing on phenom +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -23,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 23461709500 because target called exit() +122 123 124 Exiting @ tick 23058360500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index a6580fdc8..22a3b525f 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023496 # Number of seconds simulated -sim_ticks 23495860500 # Number of ticks simulated -final_tick 23495860500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023058 # Number of seconds simulated +sim_ticks 23058360500 # Number of ticks simulated +final_tick 23058360500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 162171 # Simulator instruction rate (inst/s) -host_op_rate 162171 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45264552 # Simulator tick rate (ticks/s) -host_mem_usage 273204 # Number of bytes of host memory used -host_seconds 519.08 # Real time elapsed on the host +host_inst_rate 185322 # Simulator instruction rate (inst/s) +host_op_rate 185322 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50763012 # Simulator tick rate (ticks/s) +host_mem_usage 226392 # Number of bytes of host memory used +host_seconds 454.24 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 196096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 196416 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 138432 # Number of bytes read from this memory -system.physmem.bytes_read::total 334528 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 196096 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 196096 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3064 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 334848 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 196416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 196416 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3069 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2163 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5227 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8345981 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5891761 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14237742 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8345981 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8345981 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8345981 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5891761 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 14237742 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5227 # Number of read requests accepted +system.physmem.num_reads::total 5232 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8518212 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6003549 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14521761 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8518212 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8518212 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8518212 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6003549 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 14521761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5232 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5227 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5232 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 334528 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 334848 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 334528 # Total read bytes from the system interface side +system.physmem.bytesReadSys 334848 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 469 # Per bank write bursts +system.physmem.perBankRdBursts::0 471 # Per bank write bursts system.physmem.perBankRdBursts::1 291 # Per bank write bursts system.physmem.perBankRdBursts::2 302 # Per bank write bursts system.physmem.perBankRdBursts::3 524 # Per bank write bursts system.physmem.perBankRdBursts::4 220 # Per bank write bursts -system.physmem.perBankRdBursts::5 226 # Per bank write bursts -system.physmem.perBankRdBursts::6 220 # Per bank write bursts -system.physmem.perBankRdBursts::7 285 # Per bank write bursts -system.physmem.perBankRdBursts::8 236 # Per bank write bursts -system.physmem.perBankRdBursts::9 280 # Per bank write bursts +system.physmem.perBankRdBursts::5 225 # Per bank write bursts +system.physmem.perBankRdBursts::6 219 # Per bank write bursts +system.physmem.perBankRdBursts::7 286 # Per bank write bursts +system.physmem.perBankRdBursts::8 240 # Per bank write bursts +system.physmem.perBankRdBursts::9 278 # Per bank write bursts system.physmem.perBankRdBursts::10 248 # Per bank write bursts -system.physmem.perBankRdBursts::11 254 # Per bank write bursts +system.physmem.perBankRdBursts::11 253 # Per bank write bursts system.physmem.perBankRdBursts::12 398 # Per bank write bursts -system.physmem.perBankRdBursts::13 336 # Per bank write bursts +system.physmem.perBankRdBursts::13 338 # Per bank write bursts system.physmem.perBankRdBursts::14 491 # Per bank write bursts -system.physmem.perBankRdBursts::15 447 # Per bank write bursts +system.physmem.perBankRdBursts::15 448 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 23495733500 # Total gap between requests +system.physmem.totGap 23058233500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5227 # Read request sizes (log2) +system.physmem.readPktSize::6 5232 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,12 +90,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1191 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 631 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3262 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1223 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 633 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -186,92 +186,92 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 867 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 383.188005 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 230.923786 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 354.572905 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 252 29.07% 29.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 197 22.72% 51.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 79 9.11% 60.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 57 6.57% 67.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 42 4.84% 72.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 41 4.73% 77.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 51 5.88% 82.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 24 2.77% 85.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 124 14.30% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 867 # Bytes accessed per row activation -system.physmem.totQLat 41053500 # Total ticks spent queuing -system.physmem.totMemAccLat 139059750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26135000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7854.12 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 871 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 381.722158 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 229.044875 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 356.837953 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 257 29.51% 29.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 194 22.27% 51.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 84 9.64% 61.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 65 7.46% 68.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 35 4.02% 72.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 36 4.13% 77.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 31 3.56% 80.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 43 4.94% 85.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 126 14.47% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 871 # Bytes accessed per row activation +system.physmem.totQLat 38517250 # Total ticks spent queuing +system.physmem.totMemAccLat 136617250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26160000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7361.86 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26604.12 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 14.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26111.86 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 14.52 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 14.24 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 14.52 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.11 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4351 # Number of row buffer hits during reads +system.physmem.readRowHits 4353 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.24 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.20 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4495070.50 # Average gap between requests -system.physmem.pageHitRate 83.24 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 21787630000 # Time in different power states -system.physmem.memoryStateTime::REF 784420000 # Time in different power states +system.physmem.avgGap 4407154.72 # Average gap between requests +system.physmem.pageHitRate 83.20 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 21416461750 # Time in different power states +system.physmem.memoryStateTime::REF 769860000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 919340000 # Time in different power states +system.physmem.memoryStateTime::ACT 869038750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 14237742 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 3522 # Transaction distribution -system.membus.trans_dist::ReadResp 3522 # Transaction distribution -system.membus.trans_dist::ReadExReq 1705 # Transaction distribution -system.membus.trans_dist::ReadExResp 1705 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10454 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10454 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 334528 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 334528 # Total data (bytes) +system.membus.throughput 14521761 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3525 # Transaction distribution +system.membus.trans_dist::ReadResp 3525 # Transaction distribution +system.membus.trans_dist::ReadExReq 1707 # Transaction distribution +system.membus.trans_dist::ReadExResp 1707 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10464 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10464 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334848 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 334848 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 334848 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6755000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6496500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 48973500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 48985000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 14867597 # Number of BP lookups -system.cpu.branchPred.condPredicted 10786733 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 927657 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8507235 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6975722 # Number of BTB hits +system.cpu.branchPred.lookups 15361032 # Number of BP lookups +system.cpu.branchPred.condPredicted 11166301 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 940671 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8650721 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7195754 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.997523 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1468896 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3134 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 83.180974 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1505004 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3205 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 23141508 # DTB read hits -system.cpu.dtb.read_misses 194908 # DTB read misses -system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 23336416 # DTB read accesses -system.cpu.dtb.write_hits 7073051 # DTB write hits -system.cpu.dtb.write_misses 1111 # DTB write misses -system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_accesses 7074162 # DTB write accesses -system.cpu.dtb.data_hits 30214559 # DTB hits -system.cpu.dtb.data_misses 196019 # DTB misses -system.cpu.dtb.data_acv 3 # DTB access violations -system.cpu.dtb.data_accesses 30410578 # DTB accesses -system.cpu.itb.fetch_hits 14761442 # ITB hits -system.cpu.itb.fetch_misses 106 # ITB misses +system.cpu.dtb.read_hits 23573955 # DTB read hits +system.cpu.dtb.read_misses 207074 # DTB read misses +system.cpu.dtb.read_acv 4 # DTB read access violations +system.cpu.dtb.read_accesses 23781029 # DTB read accesses +system.cpu.dtb.write_hits 7120317 # DTB write hits +system.cpu.dtb.write_misses 1134 # DTB write misses +system.cpu.dtb.write_acv 4 # DTB write access violations +system.cpu.dtb.write_accesses 7121451 # DTB write accesses +system.cpu.dtb.data_hits 30694272 # DTB hits +system.cpu.dtb.data_misses 208208 # DTB misses +system.cpu.dtb.data_acv 8 # DTB access violations +system.cpu.dtb.data_accesses 30902480 # DTB accesses +system.cpu.itb.fetch_hits 15234213 # ITB hits +system.cpu.itb.fetch_misses 102 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14761548 # ITB accesses +system.cpu.itb.fetch_accesses 15234315 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -285,238 +285,239 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 46991722 # number of cpu cycles simulated +system.cpu.numCycles 46116722 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15493602 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 127144789 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14867597 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 8444618 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22164191 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4494518 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5543985 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 114 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2326 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 15940932 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 131589057 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15361032 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 8700758 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22892353 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5007718 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 2994752 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 90 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2134 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 14761442 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 326314 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46736650 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.720451 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.375825 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 15234213 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 364576 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 45860852 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.869311 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.407633 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24572459 52.58% 52.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2364267 5.06% 57.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1190852 2.55% 60.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1750659 3.75% 63.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2760354 5.91% 69.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1155374 2.47% 72.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1219764 2.61% 74.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 773397 1.65% 76.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10949524 23.43% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 22968499 50.08% 50.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2435887 5.31% 55.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1214898 2.65% 58.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1783514 3.89% 61.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2844070 6.20% 68.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1193047 2.60% 70.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1264346 2.76% 73.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 807487 1.76% 75.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11349104 24.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46736650 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.316388 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.705685 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17320813 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4244089 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20558459 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1092640 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3520649 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2518881 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12242 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 124135665 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 32164 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3520649 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18467014 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 956444 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7682 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20482522 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3302339 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 121292511 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 99 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 405307 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2418029 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 89077183 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 157604141 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 150534696 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7069444 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 45860852 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.333090 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.853391 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16942268 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2554020 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 21969696 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 376134 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4018734 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2597948 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12434 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 128314772 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 36360 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4018734 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17696753 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 830389 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7936 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21575239 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1731801 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 125347310 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 9609 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 982853 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 675750 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 22720 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 92019426 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 162776933 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 155390791 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7386141 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 20649822 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 718 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 707 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8775432 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 25394818 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8253633 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2570331 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 907077 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 105549830 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2075 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 96657653 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 179218 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 20902238 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15662437 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1686 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46736650 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.068134 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.876130 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 23592065 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 733 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 723 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 3333773 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26203423 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8541215 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2901793 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1268500 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 108868755 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1841 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 97966771 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 305092 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 24205687 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 18927840 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1452 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 45860852 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.136174 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.932064 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12165151 26.03% 26.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 9350062 20.01% 46.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8404811 17.98% 64.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6298333 13.48% 77.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4922419 10.53% 88.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2869013 6.14% 94.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1725015 3.69% 97.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 796629 1.70% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 205217 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12004778 26.18% 26.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8735781 19.05% 45.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7795942 17.00% 62.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6187579 13.49% 75.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4939987 10.77% 86.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3238381 7.06% 93.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1831298 3.99% 97.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 880120 1.92% 99.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 246986 0.54% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46736650 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 45860852 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 189767 12.10% 12.10% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 12.10% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 12.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 186 0.01% 12.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 7209 0.46% 12.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 5897 0.38% 12.94% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 843167 53.74% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 445094 28.37% 95.05% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 77619 4.95% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 202355 11.05% 11.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 107 0.01% 11.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 8618 0.47% 11.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 9498 0.52% 12.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 955023 52.14% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 532552 29.07% 93.25% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 123630 6.75% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58783696 60.82% 60.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 479813 0.50% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2802274 2.90% 64.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115457 0.12% 64.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2387860 2.47% 66.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 311147 0.32% 67.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 760157 0.79% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23859982 24.69% 92.60% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7156941 7.40% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 59518834 60.75% 60.75% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 484423 0.49% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2816502 2.87% 64.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115449 0.12% 64.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2407923 2.46% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 312382 0.32% 67.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 763359 0.78% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24335343 24.84% 92.64% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7212230 7.36% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 96657653 # Type of FU issued -system.cpu.iq.rate 2.056908 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1568939 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016232 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 226667825 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 117702286 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87133167 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15132288 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 8786528 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7070448 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90230128 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7996457 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1520956 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 97966771 # Type of FU issued +system.cpu.iq.rate 2.124322 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1831783 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.018698 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 228533724 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 123769088 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 88239146 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15397545 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9344200 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7119957 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 91612691 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8185856 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1667830 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5398620 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 18484 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34785 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1752530 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6207225 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 16318 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 37199 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2040112 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10530 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2127 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 40236 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2728 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3520649 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 133897 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18217 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 115793083 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 374761 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 25394818 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8253633 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2075 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2932 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 43 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34785 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 541104 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 495336 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1036440 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 95417746 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23336859 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1239907 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4018734 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 14986 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 580703 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 119442937 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 327587 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 26203423 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8541215 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1841 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 22416 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 558101 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 37199 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 549687 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 504581 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1054268 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 96742235 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23781507 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1224536 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10241178 # number of nop insts executed -system.cpu.iew.exec_refs 30411225 # number of memory reference insts executed -system.cpu.iew.exec_branches 12030179 # Number of branches executed -system.cpu.iew.exec_stores 7074366 # Number of stores executed -system.cpu.iew.exec_rate 2.030522 # Inst execution rate -system.cpu.iew.wb_sent 94727613 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 94203615 # cumulative count of insts written-back -system.cpu.iew.wb_producers 64511907 # num instructions producing a value -system.cpu.iew.wb_consumers 89904657 # num instructions consuming a value +system.cpu.iew.exec_nop 10572341 # number of nop insts executed +system.cpu.iew.exec_refs 30903185 # number of memory reference insts executed +system.cpu.iew.exec_branches 12219901 # Number of branches executed +system.cpu.iew.exec_stores 7121678 # Number of stores executed +system.cpu.iew.exec_rate 2.097769 # Inst execution rate +system.cpu.iew.wb_sent 95961828 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 95359103 # cumulative count of insts written-back +system.cpu.iew.wb_producers 65705546 # num instructions producing a value +system.cpu.iew.wb_consumers 92226364 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.004685 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717559 # average fanout of values written-back +system.cpu.iew.wb_rate 2.067777 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.712438 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23891142 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 27540320 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 915882 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43216001 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.126598 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.743951 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 928822 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 41842118 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.196425 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.812600 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16755601 38.77% 38.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9919008 22.95% 61.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4484606 10.38% 72.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2269127 5.25% 77.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1610437 3.73% 81.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1128955 2.61% 83.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 722092 1.67% 85.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 821021 1.90% 87.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5505154 12.74% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16239554 38.81% 38.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9401519 22.47% 61.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4137637 9.89% 71.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2136234 5.11% 76.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1534088 3.67% 79.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1088589 2.60% 82.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 699410 1.67% 84.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 798893 1.91% 86.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5806194 13.88% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43216001 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 41842118 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -562,228 +563,229 @@ system.cpu.commit.op_class_0::MemWrite 6501103 7.07% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction -system.cpu.commit.bw_lim_events 5505154 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5806194 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 153504004 # The number of ROB reads -system.cpu.rob.rob_writes 235133069 # The number of ROB writes -system.cpu.timesIdled 5418 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 255072 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 155478259 # The number of ROB reads +system.cpu.rob.rob_writes 242937786 # The number of ROB writes +system.cpu.timesIdled 5286 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 255870 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.558231 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.558231 # CPI: Total CPI of All Threads -system.cpu.ipc 1.791373 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.791373 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 129151691 # number of integer regfile reads -system.cpu.int_regfile_writes 70572840 # number of integer regfile writes -system.cpu.fp_regfile_reads 6193374 # number of floating regfile reads -system.cpu.fp_regfile_writes 6052358 # number of floating regfile writes -system.cpu.misc_regfile_reads 714605 # number of misc regfile reads +system.cpu.cpi 0.547837 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.547837 # CPI: Total CPI of All Threads +system.cpu.ipc 1.825362 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.825362 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 130779467 # number of integer regfile reads +system.cpu.int_regfile_writes 71543363 # number of integer regfile writes +system.cpu.fp_regfile_reads 6233836 # number of floating regfile reads +system.cpu.fp_regfile_writes 6101151 # number of floating regfile writes +system.cpu.misc_regfile_reads 718857 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 37684936 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 11995 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 11995 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 109 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1731 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1731 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22964 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4597 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27561 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 734848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 885440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 885440 # Total data (bytes) +system.cpu.toL2Bus.throughput 37986395 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 11847 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 11847 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1732 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1732 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22674 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4591 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27265 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 725568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 875904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 875904 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 7026500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 6950000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 17802750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 17583000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3545000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3542750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 9548 # number of replacements -system.cpu.icache.tags.tagsinuse 1597.278061 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 14747183 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 11482 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1284.374064 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 9401 # number of replacements +system.cpu.icache.tags.tagsinuse 1598.407560 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 15220036 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 11337 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1342.510011 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1597.278061 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.779921 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.779921 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1934 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 760 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 930 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.944336 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 29534364 # Number of tag accesses -system.cpu.icache.tags.data_accesses 29534364 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 14747183 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14747183 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14747183 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14747183 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14747183 # number of overall hits -system.cpu.icache.overall_hits::total 14747183 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14258 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14258 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14258 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14258 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14258 # number of overall misses -system.cpu.icache.overall_misses::total 14258 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 414157250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 414157250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 414157250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 414157250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 414157250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 414157250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14761441 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14761441 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14761441 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14761441 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14761441 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14761441 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000966 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000966 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000966 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000966 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000966 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000966 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29047.359377 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 29047.359377 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 29047.359377 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 29047.359377 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 29047.359377 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 29047.359377 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1598.407560 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.780472 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.780472 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1936 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 757 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 931 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 30479761 # Number of tag accesses +system.cpu.icache.tags.data_accesses 30479761 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 15220036 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 15220036 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 15220036 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 15220036 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 15220036 # number of overall hits +system.cpu.icache.overall_hits::total 15220036 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14176 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14176 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14176 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14176 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14176 # number of overall misses +system.cpu.icache.overall_misses::total 14176 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 411369250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 411369250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 411369250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 411369250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 411369250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 411369250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 15234212 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 15234212 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 15234212 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 15234212 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 15234212 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 15234212 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000931 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000931 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000931 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000931 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000931 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000931 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29018.711202 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 29018.711202 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 29018.711202 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 29018.711202 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 29018.711202 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 29018.711202 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 61.600000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 40.200000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2776 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2776 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2776 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2776 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2776 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2776 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11482 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 11482 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 11482 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 11482 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 11482 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 11482 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 306274750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 306274750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 306274750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 306274750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 306274750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 306274750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000778 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000778 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000778 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000778 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000778 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000778 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26674.338094 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26674.338094 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26674.338094 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 26674.338094 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26674.338094 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 26674.338094 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2839 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2839 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2839 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2839 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2839 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2839 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11337 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 11337 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 11337 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 11337 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 11337 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 11337 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 302662500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 302662500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 302662500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 302662500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 302662500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 302662500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000744 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000744 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000744 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000744 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000744 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000744 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26696.877481 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26696.877481 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26696.877481 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 26696.877481 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26696.877481 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 26696.877481 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2409.001155 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8488 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3589 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.365004 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2409.556828 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8337 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3591 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.321637 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.673690 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2011.868133 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 379.459331 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000539 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061397 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.011580 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.073517 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3589 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 17.688406 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2013.956930 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 377.911492 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000540 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061461 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.011533 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.073534 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3591 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 909 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.109528 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 116000 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 116000 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 8418 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 55 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 8473 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 109 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 109 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 8418 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 81 # 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Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 114811 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 114811 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 8268 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 54 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 8322 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 25 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 25 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 8268 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 8347 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 8268 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 79 # 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Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2242 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12647.512935 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1456.991941 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.355711 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.355711 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1456.621503 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.355620 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.355620 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2085 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 542 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 545 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1388 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.509033 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 56220748 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 56220748 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21606921 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21606921 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492872 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492872 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 225 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 225 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28099793 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28099793 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28099793 # number of overall hits -system.cpu.dcache.overall_hits::total 28099793 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1002 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1002 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8231 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8231 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 56732342 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 56732342 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21862715 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21862715 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492763 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492763 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 246 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 246 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28355478 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28355478 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28355478 # number of overall hits +system.cpu.dcache.overall_hits::total 28355478 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 985 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 985 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8340 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8340 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9233 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9233 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9233 # number of overall misses -system.cpu.dcache.overall_misses::total 9233 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 62924000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 62924000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 508720531 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 508720531 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9325 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9325 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9325 # number of overall misses +system.cpu.dcache.overall_misses::total 9325 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 61174750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 61174750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 507348010 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 507348010 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 571644531 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 571644531 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 571644531 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 571644531 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21607923 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21607923 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 568522760 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 568522760 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 568522760 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 568522760 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21863700 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21863700 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 226 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 226 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28109026 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28109026 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28109026 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28109026 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001266 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001266 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004425 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004425 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000328 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000328 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000328 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000328 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62798.403194 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62798.403194 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61805.434455 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61805.434455 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 247 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28364803 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28364803 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28364803 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28364803 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001283 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001283 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004049 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004049 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000329 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000329 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000329 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000329 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62106.345178 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62106.345178 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60833.094724 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60833.094724 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61913.195170 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61913.195170 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61913.195170 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61913.195170 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 23691 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60967.588204 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60967.588204 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60967.588204 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60967.588204 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 27950 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 343 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 875 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 69.069971 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.942857 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 109 # number of writebacks -system.cpu.dcache.writebacks::total 109 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 490 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 490 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6500 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6500 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6990 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6990 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6990 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6990 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 512 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 512 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1731 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1731 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 107 # number of writebacks +system.cpu.dcache.writebacks::total 107 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 476 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 476 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6608 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6608 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7084 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7084 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7084 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7084 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 509 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 509 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1732 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1732 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2243 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2243 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2243 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2243 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36779750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36779750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 124808747 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 124808747 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2241 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2241 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2241 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2241 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36463750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36463750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 124994997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 124994997 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161588497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 161588497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161588497 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 161588497 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161458747 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 161458747 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161458747 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 161458747 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004425 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004425 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71835.449219 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71835.449219 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72102.106875 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72102.106875 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004049 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004049 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000079 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000079 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71638.015717 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71638.015717 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72168.012125 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72168.012125 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72041.238074 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72041.238074 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72041.238074 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72041.238074 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72047.633646 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72047.633646 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72047.633646 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72047.633646 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini index 03d137b4d..289d5c40d 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -118,6 +118,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -698,7 +699,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/cpu2000/binaries/arm/linux/twolf +executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 @@ -727,9 +728,9 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -740,27 +741,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout index ce396dba2..8dd189a74 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 18:25:13 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing +gem5 compiled Jun 21 2014 11:22:42 +gem5 started Jun 21 2014 21:53:28 +gem5 executing on phenom +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x5949040 + 0: system.cpu.isa: ISA system set to: 0 0x4f074c0 info: Entering event queue @ 0. Starting simulation... TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 @@ -22,4 +22,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 74219931000 because target called exit() +122 123 124 Exiting @ tick 74056845500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 59645b4d8..eafc895c2 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.074209 # Number of seconds simulated -sim_ticks 74208571000 # Number of ticks simulated -final_tick 74208571000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.074057 # Number of seconds simulated +sim_ticks 74056845500 # Number of ticks simulated +final_tick 74056845500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109569 # Simulator instruction rate (inst/s) -host_op_rate 119969 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47190079 # Simulator tick rate (ticks/s) -host_mem_usage 316768 # Number of bytes of host memory used -host_seconds 1572.55 # Real time elapsed on the host +host_inst_rate 115398 # Simulator instruction rate (inst/s) +host_op_rate 126351 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49598898 # Simulator tick rate (ticks/s) +host_mem_usage 265028 # Number of bytes of host memory used +host_seconds 1493.11 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 188656503 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 131456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 111808 # Number of bytes read from this memory -system.physmem.bytes_read::total 243264 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 131456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 131456 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2054 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1747 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3801 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1771440 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1506672 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3278112 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1771440 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1771440 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1771440 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1506672 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3278112 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3802 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 131840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 112192 # Number of bytes read from this memory +system.physmem.bytes_read::total 244032 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 131840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 131840 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2060 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1753 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3813 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1780254 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1514944 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3295198 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1780254 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1780254 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1780254 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1514944 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3295198 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3814 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 3802 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 3814 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 243328 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 244096 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 243328 # Total read bytes from the system interface side +system.physmem.bytesReadSys 244096 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 306 # Per bank write bursts -system.physmem.perBankRdBursts::1 216 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 307 # Per bank write bursts +system.physmem.perBankRdBursts::1 215 # Per bank write bursts system.physmem.perBankRdBursts::2 134 # Per bank write bursts -system.physmem.perBankRdBursts::3 308 # Per bank write bursts -system.physmem.perBankRdBursts::4 298 # Per bank write bursts +system.physmem.perBankRdBursts::3 310 # Per bank write bursts +system.physmem.perBankRdBursts::4 299 # Per bank write bursts system.physmem.perBankRdBursts::5 300 # Per bank write bursts system.physmem.perBankRdBursts::6 265 # Per bank write bursts -system.physmem.perBankRdBursts::7 217 # Per bank write bursts +system.physmem.perBankRdBursts::7 223 # Per bank write bursts system.physmem.perBankRdBursts::8 246 # Per bank write bursts -system.physmem.perBankRdBursts::9 215 # Per bank write bursts +system.physmem.perBankRdBursts::9 213 # Per bank write bursts system.physmem.perBankRdBursts::10 289 # Per bank write bursts -system.physmem.perBankRdBursts::11 192 # Per bank write bursts +system.physmem.perBankRdBursts::11 196 # Per bank write bursts system.physmem.perBankRdBursts::12 190 # Per bank write bursts -system.physmem.perBankRdBursts::13 208 # Per bank write bursts -system.physmem.perBankRdBursts::14 218 # Per bank write bursts -system.physmem.perBankRdBursts::15 200 # Per bank write bursts +system.physmem.perBankRdBursts::13 207 # Per bank write bursts +system.physmem.perBankRdBursts::14 219 # Per bank write bursts +system.physmem.perBankRdBursts::15 201 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 74208552500 # Total gap between requests +system.physmem.totGap 74056827000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 3802 # Read request sizes (log2) +system.physmem.readPktSize::6 3814 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2914 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 704 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2889 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 752 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,72 +186,74 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 765 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 315.649673 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 194.993895 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 311.806865 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 244 31.90% 31.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 208 27.19% 59.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 73 9.54% 68.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 46 6.01% 74.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 29 3.79% 78.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 70 9.15% 87.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 12 1.57% 89.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 15 1.96% 91.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 68 8.89% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 765 # Bytes accessed per row activation -system.physmem.totQLat 30320750 # Total ticks spent queuing -system.physmem.totMemAccLat 101608250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 19010000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7974.95 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 775 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 313.641290 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 192.687696 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 311.293227 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 258 33.29% 33.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 189 24.39% 57.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 87 11.23% 68.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 51 6.58% 75.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 41 5.29% 80.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 31 4.00% 84.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 43 5.55% 90.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 10 1.29% 91.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 65 8.39% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 775 # Bytes accessed per row activation +system.physmem.totQLat 30109750 # Total ticks spent queuing +system.physmem.totMemAccLat 101622250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 19070000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7894.53 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26724.95 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.28 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26644.53 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.30 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.28 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.30 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 3030 # Number of row buffer hits during reads +system.physmem.readRowHits 3033 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.69 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.52 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19518293.66 # Average gap between requests -system.physmem.pageHitRate 79.69 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 70857777500 # Time in different power states -system.physmem.memoryStateTime::REF 2477800000 # Time in different power states +system.physmem.avgGap 19417101.99 # Average gap between requests +system.physmem.pageHitRate 79.52 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 70721348250 # Time in different power states +system.physmem.memoryStateTime::REF 2472860000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 867720500 # Time in different power states +system.physmem.memoryStateTime::ACT 861203250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 3278112 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 2731 # Transaction distribution -system.membus.trans_dist::ReadResp 2730 # Transaction distribution -system.membus.trans_dist::ReadExReq 1071 # Transaction distribution -system.membus.trans_dist::ReadExResp 1071 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7603 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7603 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 243264 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 243264 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 243264 # Total data (bytes) +system.membus.throughput 3295198 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 2737 # Transaction distribution +system.membus.trans_dist::ReadResp 2736 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 1077 # Transaction distribution +system.membus.trans_dist::ReadExResp 1077 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7631 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7631 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 244032 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 244032 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 244032 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 4745000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4541000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 35718000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 35636248 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 94830067 # Number of BP lookups -system.cpu.branchPred.condPredicted 74823235 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6280063 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 44671635 # Number of BTB lookups -system.cpu.branchPred.BTBHits 43055955 # Number of BTB hits +system.cpu.branchPred.lookups 95688557 # Number of BP lookups +system.cpu.branchPred.condPredicted 75485372 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6295432 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 45268261 # Number of BTB lookups +system.cpu.branchPred.BTBHits 43530249 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 96.383208 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 4354004 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 88575 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 96.160639 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 4420185 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 89338 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -337,240 +339,241 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 148417143 # number of cpu cycles simulated +system.cpu.numCycles 148113692 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 39654365 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 380231735 # Number of instructions fetch has processed -system.cpu.fetch.Branches 94830067 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 47409959 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80369944 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 27285630 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7202415 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 10 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 5794 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 40192835 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 385592009 # Number of instructions fetch has processed +system.cpu.fetch.Branches 95688557 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 47950434 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 81543775 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 28012255 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 4465673 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 5818 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 50 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 36851066 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1832690 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 148222429 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.802512 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.153204 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 43 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 37392446 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1863811 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 147907378 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.849949 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.160123 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68020985 45.89% 45.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5256509 3.55% 49.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10534999 7.11% 56.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10284828 6.94% 63.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8666572 5.85% 69.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6537070 4.41% 73.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6246175 4.21% 77.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8016813 5.41% 83.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 24658478 16.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 66535735 44.98% 44.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5361707 3.63% 48.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10726789 7.25% 55.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10405351 7.04% 62.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8725871 5.90% 68.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6634741 4.49% 73.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6328592 4.28% 77.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8060301 5.45% 83.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 25128291 16.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 148222429 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.638943 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.561913 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45507597 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5871716 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74805608 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1201041 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 20836467 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14340186 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 164591 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 392845308 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 733522 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 20836467 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 50894479 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 722812 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 602318 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 70557272 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4609081 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 371354915 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 44 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 338748 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3656059 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 24 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 631764461 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1588652531 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1506975247 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3198470 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 147907378 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.646048 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.603352 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45234948 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3964725 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 76674416 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 488435 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 21544854 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14463585 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 165860 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 398867240 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 776962 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 21544854 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 49978288 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 80802 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 634035 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 72417632 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3251767 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 377266574 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 64 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 883323 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2242172 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 19804 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 7460 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 639899653 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1616068029 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1531504010 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3330597 # Number of floating rename lookups system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 333720322 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25119 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25116 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13019783 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 43012506 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16421309 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5620383 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3639856 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 329245944 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 47173 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 249482695 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 793526 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 139565421 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 362544222 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1957 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 148222429 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.683164 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.761970 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 341855514 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 25341 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 25337 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 6011835 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 44415560 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16956234 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 6645157 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4213095 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 334591306 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 47320 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 251099486 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1072213 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 144899766 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 380484892 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2104 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 147907378 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.697681 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.790678 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56049781 37.81% 37.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 22646407 15.28% 53.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 24808421 16.74% 69.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20317592 13.71% 83.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12547069 8.47% 92.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6521251 4.40% 96.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4032352 2.72% 99.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1118421 0.75% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 181135 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56583019 38.26% 38.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 21897324 14.80% 53.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24121591 16.31% 69.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20330444 13.75% 83.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12466477 8.43% 91.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6673732 4.51% 96.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4321605 2.92% 98.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1302038 0.88% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 211148 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 148222429 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 147907378 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 964061 38.35% 38.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5595 0.22% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 96 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 48 0.00% 38.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1168003 46.46% 85.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 376162 14.96% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1040958 39.39% 39.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5589 0.21% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 39.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 97 0.00% 39.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 39.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 39.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 356 0.01% 39.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 39.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 45 0.00% 39.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 39.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 39.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 39.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1222208 46.25% 85.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 373303 14.13% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 194908316 78.12% 78.12% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 978999 0.39% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33072 0.01% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 164299 0.07% 78.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 255151 0.10% 78.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76428 0.03% 78.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 465968 0.19% 78.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206368 0.08% 79.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71868 0.03% 79.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 38371220 15.38% 94.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13950685 5.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 195834645 77.99% 77.99% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 981127 0.39% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33203 0.01% 78.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 164429 0.07% 78.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 259909 0.10% 78.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76654 0.03% 78.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 470113 0.19% 78.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206582 0.08% 78.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71910 0.03% 78.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 78.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 38922233 15.50% 94.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 14078361 5.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 249482695 # Type of FU issued -system.cpu.iq.rate 1.680956 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2513965 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010077 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 646755779 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 466684925 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237894917 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3739531 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2191886 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1842592 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 250120414 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1876246 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2009109 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 251099486 # Type of FU issued +system.cpu.iq.rate 1.695316 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2642556 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010524 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 650051417 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 477257433 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 239511768 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3769702 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2301296 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1862518 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 251853224 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1888818 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2264941 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13163022 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11141 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18733 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3776675 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14566076 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14946 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20827 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4311600 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 14 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 100 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 16 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 115 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 20836467 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 18579 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 909 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 329310121 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 781513 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 43012506 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16421309 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 24765 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 190 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 272 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18733 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3888765 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3761308 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7650073 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 242977304 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 36862847 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6505391 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 21544854 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1947 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2849 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 334655682 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 756589 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 44415560 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16956234 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 24912 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 319 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2632 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 20827 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3907560 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3770350 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7677910 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 244706645 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 37396904 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6392841 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 17004 # number of nop insts executed -system.cpu.iew.exec_refs 50511963 # number of memory reference insts executed -system.cpu.iew.exec_branches 53432662 # Number of branches executed -system.cpu.iew.exec_stores 13649116 # Number of stores executed -system.cpu.iew.exec_rate 1.637124 # Inst execution rate -system.cpu.iew.wb_sent 240796428 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 239737509 # cumulative count of insts written-back -system.cpu.iew.wb_producers 148472463 # num instructions producing a value -system.cpu.iew.wb_consumers 267293668 # num instructions consuming a value +system.cpu.iew.exec_nop 17056 # number of nop insts executed +system.cpu.iew.exec_refs 51162912 # number of memory reference insts executed +system.cpu.iew.exec_branches 53733408 # Number of branches executed +system.cpu.iew.exec_stores 13766008 # Number of stores executed +system.cpu.iew.exec_rate 1.652154 # Inst execution rate +system.cpu.iew.wb_sent 242463171 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 241374286 # cumulative count of insts written-back +system.cpu.iew.wb_producers 150213875 # num instructions producing a value +system.cpu.iew.wb_consumers 271770811 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.615295 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.555466 # average fanout of values written-back +system.cpu.iew.wb_rate 1.629655 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.552723 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 140639228 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 145985060 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6126680 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 127385962 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.481096 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.186061 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6141058 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 126362524 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.493092 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.207919 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 57702305 45.30% 45.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 31675528 24.87% 70.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13782422 10.82% 80.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7634808 5.99% 86.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4379316 3.44% 90.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1319569 1.04% 91.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1705598 1.34% 92.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1313930 1.03% 93.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7872486 6.18% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 57333838 45.37% 45.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 31277146 24.75% 70.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13531640 10.71% 80.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7550408 5.98% 86.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4276360 3.38% 90.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1325331 1.05% 91.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1692872 1.34% 92.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1209518 0.96% 93.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 8165411 6.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 127385962 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 126362524 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317409 # Number of instructions committed system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -616,229 +619,237 @@ system.cpu.commit.op_class_0::MemWrite 12644634 6.70% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 188670891 # Class of committed instruction -system.cpu.commit.bw_lim_events 7872486 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 8165411 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 448818394 # The number of ROB reads -system.cpu.rob.rob_writes 679565858 # The number of ROB writes -system.cpu.timesIdled 2789 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 194714 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 452847863 # The number of ROB reads +system.cpu.rob.rob_writes 690972129 # The number of ROB writes +system.cpu.timesIdled 2844 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 206314 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303021 # Number of Instructions Simulated system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.861373 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.861373 # CPI: Total CPI of All Threads -system.cpu.ipc 1.160937 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.160937 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1079497274 # number of integer regfile reads -system.cpu.int_regfile_writes 384888160 # number of integer regfile writes -system.cpu.fp_regfile_reads 2912753 # number of floating regfile reads -system.cpu.fp_regfile_writes 2499155 # number of floating regfile writes -system.cpu.misc_regfile_reads 64874393 # number of misc regfile reads +system.cpu.cpi 0.859612 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.859612 # CPI: Total CPI of All Threads +system.cpu.ipc 1.163316 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.163316 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1087499674 # number of integer regfile reads +system.cpu.int_regfile_writes 386673292 # number of integer regfile writes +system.cpu.fp_regfile_reads 2922602 # number of floating regfile reads +system.cpu.fp_regfile_writes 2532629 # number of floating regfile writes +system.cpu.misc_regfile_reads 65625361 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.toL2Bus.throughput 5170292 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 4896 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 4895 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 19 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1081 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1081 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8239 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3733 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 11972 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 263616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.throughput 5184342 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 4900 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 4899 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1084 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1084 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8245 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3740 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 11985 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 263744 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 383680 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 383680 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 383808 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 383808 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 128 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 3017000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6548996 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6552747 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3099487 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3102991 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 2388 # number of replacements -system.cpu.icache.tags.tagsinuse 1346.753946 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 36845676 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4119 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8945.296431 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2387 # number of replacements +system.cpu.icache.tags.tagsinuse 1349.069671 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 37387126 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4121 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 9072.343121 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1346.753946 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.657595 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.657595 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1731 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1349.069671 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.658725 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.658725 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1734 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 541 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 30 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1037 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.845215 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 73706251 # Number of tag accesses -system.cpu.icache.tags.data_accesses 73706251 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 36845676 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 36845676 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 36845676 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 36845676 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 36845676 # number of overall hits -system.cpu.icache.overall_hits::total 36845676 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5390 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5390 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5390 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5390 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5390 # number of overall misses -system.cpu.icache.overall_misses::total 5390 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 228751995 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 228751995 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 228751995 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 228751995 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 228751995 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 228751995 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 36851066 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 36851066 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 36851066 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 36851066 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 36851066 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 36851066 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000146 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000146 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000146 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000146 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000146 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000146 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42440.073284 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42440.073284 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42440.073284 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42440.073284 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42440.073284 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42440.073284 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1596 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 547 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 28 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1033 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.846680 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 74789015 # Number of tag accesses +system.cpu.icache.tags.data_accesses 74789015 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 37387126 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 37387126 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 37387126 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 37387126 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 37387126 # number of overall hits +system.cpu.icache.overall_hits::total 37387126 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5320 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5320 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5320 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5320 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5320 # number of overall misses +system.cpu.icache.overall_misses::total 5320 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 224799997 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 224799997 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 224799997 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 224799997 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 224799997 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 224799997 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 37392446 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 37392446 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 37392446 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 37392446 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 37392446 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 37392446 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000142 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000142 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000142 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000142 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000142 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000142 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42255.638534 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42255.638534 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42255.638534 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42255.638534 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42255.638534 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42255.638534 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1071 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 84 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 59.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1270 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1270 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1270 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1270 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1270 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1270 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4120 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4120 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4120 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4120 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4120 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4120 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 167326504 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 167326504 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 167326504 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 167326504 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 167326504 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 167326504 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000112 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000112 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40613.229126 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40613.229126 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40613.229126 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 40613.229126 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40613.229126 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 40613.229126 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1196 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1196 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1196 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1196 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1196 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1196 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4124 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4124 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4124 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4124 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4124 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4124 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168596253 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 168596253 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168596253 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 168596253 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168596253 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 168596253 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000110 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000110 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000110 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000110 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000110 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000110 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40881.729631 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40881.729631 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40881.729631 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 40881.729631 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40881.729631 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 40881.729631 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 1966.490721 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2149 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2739 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.784593 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 1967.769315 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2148 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2745 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.782514 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 4.023907 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1424.627361 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 537.839452 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 4.017679 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1427.875766 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 535.875870 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000123 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043476 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.016414 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.060013 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 2739 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 607 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 29 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1969 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.083588 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 51788 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 51788 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2061 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 87 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2148 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 19 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 19 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 10 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 10 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2061 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 97 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2158 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2061 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 97 # number of overall hits -system.cpu.l2cache.overall_hits::total 2158 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2059 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 689 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 2748 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 1071 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1071 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2059 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1760 # 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average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56257.195915 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57167.515769 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57623.217342 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57376.966439 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57167.515769 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57623.217342 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57376.966439 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 60 # number of replacements -system.cpu.dcache.tags.tagsinuse 1407.063073 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 46801066 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1857 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 25202.512655 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 56 # number of replacements +system.cpu.dcache.tags.tagsinuse 1410.171492 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 47073011 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1860 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 25308.070430 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1407.063073 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.343521 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.343521 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1410.171492 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.344280 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.344280 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1804 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 354 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1378 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.438721 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 93623269 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 93623269 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 34399630 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 34399630 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12356556 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12356556 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22473 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22473 # number of LoadLockedReq hits +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1382 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.440430 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 94167216 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 94167216 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 34671591 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 34671591 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12356534 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12356534 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22477 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22477 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 46756186 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 46756186 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 46756186 # number of overall hits -system.cpu.dcache.overall_hits::total 46756186 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1907 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1907 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 7731 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 7731 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 47028125 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 47028125 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 47028125 # number of overall hits +system.cpu.dcache.overall_hits::total 47028125 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1914 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1914 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 7753 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 7753 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9638 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9638 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9638 # number of overall misses -system.cpu.dcache.overall_misses::total 9638 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 121525225 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 121525225 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 489452496 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 489452496 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9667 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9667 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9667 # number of overall misses +system.cpu.dcache.overall_misses::total 9667 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 120679977 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 120679977 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 501616998 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 501616998 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 142500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 610977721 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 610977721 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 610977721 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 610977721 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 34401537 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 34401537 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 622296975 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 622296975 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 622296975 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 622296975 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 34673505 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 34673505 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22475 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 22475 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22479 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22479 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46765824 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46765824 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46765824 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46765824 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 47037792 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 47037792 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 47037792 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 47037792 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000055 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000055 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000625 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000625 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000627 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000627 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63725.865233 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63725.865233 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63310.373302 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63310.373302 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63051.189655 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63051.189655 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64699.728879 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64699.728879 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63392.583627 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63392.583627 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63392.583627 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63392.583627 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 567 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 318 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 51.545455 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 79.500000 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64373.329368 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64373.329368 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64373.329368 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64373.329368 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 706 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 99 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 50.428571 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 99 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 19 # number of writebacks -system.cpu.dcache.writebacks::total 19 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1130 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1130 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6651 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6651 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 16 # number of writebacks +system.cpu.dcache.writebacks::total 16 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1137 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1137 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6668 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6668 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7781 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7781 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7781 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7781 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7805 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7805 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7805 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7805 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 777 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 777 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1080 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1080 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1857 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1857 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1857 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1857 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52119013 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 52119013 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 75404498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 75404498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 127523511 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 127523511 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 127523511 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 127523511 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000087 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1085 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1085 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1862 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1862 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1862 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1862 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51275761 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 51275761 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 75222996 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 75222996 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126498757 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 126498757 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126498757 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 126498757 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67077.236808 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67077.236808 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69818.979630 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69818.979630 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68671.788368 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68671.788368 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68671.788368 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68671.788368 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65991.970399 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65991.970399 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69329.950230 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69329.950230 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67937.033835 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67937.033835 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67937.033835 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67937.033835 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini index e8d7fb666..3c2ec0084 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -115,6 +116,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -632,7 +634,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/cpu2000/binaries/x86/linux/twolf +executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 @@ -661,9 +663,9 @@ master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_s slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -674,27 +676,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout index 1e66bd991..dda302f8a 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:10:34 -gem5 started Jan 22 2014 21:43:52 -gem5 executing on u200540-lin -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing +gem5 compiled Jun 21 2014 11:13:07 +gem5 started Jun 21 2014 22:44:43 +gem5 executing on phenom +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second @@ -24,4 +24,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 144463317000 because target called exit() +122 123 124 Exiting @ tick 145782984000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 8bb498da9..87a35ab50 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.144620 # Number of seconds simulated -sim_ticks 144620050000 # Number of ticks simulated -final_tick 144620050000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.145783 # Number of seconds simulated +sim_ticks 145782984000 # Number of ticks simulated +final_tick 145782984000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 65513 # Simulator instruction rate (inst/s) -host_op_rate 109805 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 71737347 # Simulator tick rate (ticks/s) -host_mem_usage 319696 # Number of bytes of host memory used -host_seconds 2015.97 # Real time elapsed on the host +host_inst_rate 75578 # Simulator instruction rate (inst/s) +host_op_rate 126676 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 83424852 # Simulator tick rate (ticks/s) +host_mem_usage 276072 # Number of bytes of host memory used +host_seconds 1747.48 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 217216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125440 # Number of bytes read from this memory -system.physmem.bytes_read::total 342656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 217216 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 217216 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3394 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1960 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5354 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1501977 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 867376 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2369353 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1501977 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1501977 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1501977 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 867376 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2369353 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5356 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 219712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125824 # Number of bytes read from this memory +system.physmem.bytes_read::total 345536 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 219712 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219712 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3433 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1966 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5399 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1507117 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 863091 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2370208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1507117 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1507117 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1507117 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 863091 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2370208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5399 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5356 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5399 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 342784 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 345536 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 342784 # Total read bytes from the system interface side +system.physmem.bytesReadSys 345536 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 131 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 288 # Per bank write bursts -system.physmem.perBankRdBursts::1 358 # Per bank write bursts -system.physmem.perBankRdBursts::2 449 # Per bank write bursts -system.physmem.perBankRdBursts::3 356 # Per bank write bursts -system.physmem.perBankRdBursts::4 330 # Per bank write bursts -system.physmem.perBankRdBursts::5 328 # Per bank write bursts -system.physmem.perBankRdBursts::6 400 # Per bank write bursts -system.physmem.perBankRdBursts::7 378 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 225 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 296 # Per bank write bursts +system.physmem.perBankRdBursts::1 360 # Per bank write bursts +system.physmem.perBankRdBursts::2 450 # Per bank write bursts +system.physmem.perBankRdBursts::3 362 # Per bank write bursts +system.physmem.perBankRdBursts::4 334 # Per bank write bursts +system.physmem.perBankRdBursts::5 327 # Per bank write bursts +system.physmem.perBankRdBursts::6 402 # Per bank write bursts +system.physmem.perBankRdBursts::7 379 # Per bank write bursts system.physmem.perBankRdBursts::8 340 # Per bank write bursts -system.physmem.perBankRdBursts::9 277 # Per bank write bursts -system.physmem.perBankRdBursts::10 231 # Per bank write bursts -system.physmem.perBankRdBursts::11 276 # Per bank write bursts -system.physmem.perBankRdBursts::12 208 # Per bank write bursts -system.physmem.perBankRdBursts::13 466 # Per bank write bursts -system.physmem.perBankRdBursts::14 385 # Per bank write bursts -system.physmem.perBankRdBursts::15 286 # Per bank write bursts +system.physmem.perBankRdBursts::9 280 # Per bank write bursts +system.physmem.perBankRdBursts::10 232 # Per bank write bursts +system.physmem.perBankRdBursts::11 283 # Per bank write bursts +system.physmem.perBankRdBursts::12 213 # Per bank write bursts +system.physmem.perBankRdBursts::13 468 # Per bank write bursts +system.physmem.perBankRdBursts::14 388 # Per bank write bursts +system.physmem.perBankRdBursts::15 285 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 144620007000 # Total gap between requests +system.physmem.totGap 145782934000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5356 # Read request sizes (log2) +system.physmem.readPktSize::6 5399 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,12 +90,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4298 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 873 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4350 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 862 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 162 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1043 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 326.933845 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 193.223116 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.208962 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 368 35.28% 35.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 248 23.78% 59.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 102 9.78% 68.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 58 5.56% 74.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 42 4.03% 78.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 59 5.66% 84.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 17 1.63% 85.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 23 2.21% 87.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 126 12.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1043 # Bytes accessed per row activation -system.physmem.totQLat 35519000 # Total ticks spent queuing -system.physmem.totMemAccLat 135944000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26780000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6631.63 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1099 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 313.768881 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.938334 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 327.481688 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 421 38.31% 38.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 241 21.93% 60.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 100 9.10% 69.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 65 5.91% 75.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 56 5.10% 80.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 54 4.91% 85.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 19 1.73% 86.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 20 1.82% 88.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 123 11.19% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1099 # Bytes accessed per row activation +system.physmem.totQLat 41267750 # Total ticks spent queuing +system.physmem.totMemAccLat 142499000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26995000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7643.59 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25381.63 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26393.59 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.37 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.37 # Average system read bandwidth in MiByte/s @@ -214,279 +214,280 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4304 # Number of row buffer hits during reads +system.physmem.readRowHits 4296 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.36 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.57 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 27001494.96 # Average gap between requests -system.physmem.pageHitRate 80.36 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 138334279250 # Time in different power states -system.physmem.memoryStateTime::REF 4828980000 # Time in different power states +system.physmem.avgGap 27001839.97 # Average gap between requests +system.physmem.pageHitRate 79.57 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 139294402000 # Time in different power states +system.physmem.memoryStateTime::REF 4867980000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1451861250 # Time in different power states +system.physmem.memoryStateTime::ACT 1619857750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 2368911 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 3823 # Transaction distribution -system.membus.trans_dist::ReadResp 3820 # Transaction distribution -system.membus.trans_dist::UpgradeReq 131 # Transaction distribution -system.membus.trans_dist::UpgradeResp 131 # Transaction distribution -system.membus.trans_dist::ReadExReq 1533 # Transaction distribution -system.membus.trans_dist::ReadExResp 1533 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10971 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 10971 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10971 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 342592 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 342592 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 342592 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 342592 # Total data (bytes) +system.membus.throughput 2370208 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3862 # Transaction distribution +system.membus.trans_dist::ReadResp 3862 # Transaction distribution +system.membus.trans_dist::UpgradeReq 225 # Transaction distribution +system.membus.trans_dist::UpgradeResp 225 # Transaction distribution +system.membus.trans_dist::ReadExReq 1537 # Transaction distribution +system.membus.trans_dist::ReadExResp 1537 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11248 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11248 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11248 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 345536 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 345536 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 345536 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 345536 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6960500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6776000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 50659869 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 50906775 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 18663045 # Number of BP lookups -system.cpu.branchPred.condPredicted 18663045 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1489785 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11444584 # Number of BTB lookups -system.cpu.branchPred.BTBHits 10797822 # Number of BTB hits +system.cpu.branchPred.lookups 19251245 # Number of BP lookups +system.cpu.branchPred.condPredicted 19251245 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1503864 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11794147 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11185323 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.348750 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1319901 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 22895 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.837914 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1363914 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 22896 # Number of incorrect RAS predictions. system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 289523031 # number of cpu cycles simulated +system.cpu.numCycles 291881234 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 23473938 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 206858197 # Number of instructions fetch has processed -system.cpu.fetch.Branches 18663045 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 12117723 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 54247835 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 15552938 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 178336695 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1340 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 7706 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 24 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22368694 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 223698 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 269869756 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.267902 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.756065 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 24212208 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 214052436 # Number of instructions fetch has processed +system.cpu.fetch.Branches 19251245 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 12549237 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 55985392 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 16840264 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 177008858 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1283 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 7024 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 65 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 23136044 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 282405 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 272277792 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.296795 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.780007 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 217061517 80.43% 80.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2847740 1.06% 81.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2315002 0.86% 82.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2640494 0.98% 83.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3217056 1.19% 84.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3387561 1.26% 85.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3839682 1.42% 87.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2560696 0.95% 88.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 32000008 11.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 217778926 79.98% 79.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2920418 1.07% 81.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2383762 0.88% 81.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2729411 1.00% 82.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3335214 1.22% 84.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3498463 1.28% 85.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4001053 1.47% 86.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2671434 0.98% 87.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 32959111 12.10% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 269869756 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.064461 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.714479 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36939117 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 167279649 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 41594778 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10253994 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 13802218 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 336245393 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 13802218 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 45020160 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 116775107 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 31642 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 42714880 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 51525749 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 329872428 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 11092 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 26167242 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22759273 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 382595093 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 918331708 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 606342575 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4133173 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 272277792 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.065956 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.733355 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35864450 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 167881983 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 44786392 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8682005 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 15062962 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 346567500 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 15062962 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 42671339 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 116778023 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 37081 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 45654825 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 52073562 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 340013592 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 22387 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 45742154 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 5966467 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 137065 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 393960742 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 945391670 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 624205941 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4453971 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 123165643 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2073 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2073 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 105277588 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 84554246 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 30134710 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 58533931 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 19035455 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 322937953 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4364 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 260608849 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 112553 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 101196304 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 210593531 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3119 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 269869756 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.965684 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.342187 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 134531292 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2243 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2238 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 90830827 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 87006444 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 31074157 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 61167406 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 20316475 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 332092429 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4572 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 263265541 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 182587 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 110344895 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 231927910 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3327 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 272277792 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.966901 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.357293 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 143519297 53.18% 53.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55647203 20.62% 73.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34229884 12.68% 86.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 19073202 7.07% 93.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10874136 4.03% 97.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4113724 1.52% 99.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1802263 0.67% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 476846 0.18% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 133201 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 146114169 53.66% 53.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 54798888 20.13% 73.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 34241976 12.58% 86.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18986540 6.97% 93.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 11181244 4.11% 97.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4283756 1.57% 99.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1956251 0.72% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 577925 0.21% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 137043 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 269869756 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 272277792 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 125646 4.63% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2288183 84.39% 89.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 297636 10.98% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 142962 5.08% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.08% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2337044 83.10% 88.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 332186 11.81% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1210826 0.46% 0.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 162119129 62.21% 62.67% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 788294 0.30% 62.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7035677 2.70% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1444684 0.55% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 65441941 25.11% 91.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 22568298 8.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1210901 0.46% 0.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 164273729 62.40% 62.86% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 789732 0.30% 63.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7035869 2.67% 65.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1461918 0.56% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 65849141 25.01% 91.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 22644251 8.60% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 260608849 # Type of FU issued -system.cpu.iq.rate 0.900132 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2711465 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010404 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 789025856 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 420800342 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 255248449 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4885616 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 3622403 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2349194 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 259650836 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2458652 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18874838 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 263265541 # Type of FU issued +system.cpu.iq.rate 0.901961 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2812192 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010682 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 796857032 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 438700759 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 257701720 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4946621 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4039797 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2377852 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 262377827 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2489005 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18800853 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 27904659 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 26471 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 289699 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 9618993 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 30356857 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 18134 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 304082 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10558440 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 50123 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 17 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 49872 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 13802218 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 85051562 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5443180 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 322942317 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 133815 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 84554246 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 30134710 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2043 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2682047 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 14716 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 289699 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 640019 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 900364 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1540383 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 258834349 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 64663337 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1774500 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 15062962 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 84436601 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5827541 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 332097001 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 93155 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 87006444 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 31074157 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2159 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2868922 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 287074 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 304082 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 649398 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 907392 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1556790 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 261390422 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 65051182 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1875119 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 87028906 # number of memory reference insts executed -system.cpu.iew.exec_branches 14271418 # Number of branches executed -system.cpu.iew.exec_stores 22365569 # Number of stores executed -system.cpu.iew.exec_rate 0.894003 # Inst execution rate -system.cpu.iew.wb_sent 258197839 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 257597643 # cumulative count of insts written-back -system.cpu.iew.wb_producers 206027195 # num instructions producing a value -system.cpu.iew.wb_consumers 369217293 # num instructions consuming a value +system.cpu.iew.exec_refs 87491108 # number of memory reference insts executed +system.cpu.iew.exec_branches 14410736 # Number of branches executed +system.cpu.iew.exec_stores 22439926 # Number of stores executed +system.cpu.iew.exec_rate 0.895537 # Inst execution rate +system.cpu.iew.wb_sent 260730148 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 260079572 # cumulative count of insts written-back +system.cpu.iew.wb_producers 208603284 # num instructions producing a value +system.cpu.iew.wb_consumers 373821854 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.889731 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.558011 # average fanout of values written-back +system.cpu.iew.wb_rate 0.891046 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.558029 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 101647922 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 110904752 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1490935 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 256067538 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.864473 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.651889 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1504927 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 257214830 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.860617 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.643182 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 156617936 61.16% 61.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57255270 22.36% 83.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14082261 5.50% 89.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12088609 4.72% 93.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4189643 1.64% 95.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2964480 1.16% 96.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 903129 0.35% 96.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1051661 0.41% 97.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6914549 2.70% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 157256344 61.14% 61.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57715541 22.44% 83.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14223073 5.53% 89.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12060500 4.69% 93.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4224463 1.64% 95.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2956145 1.15% 96.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 920096 0.36% 96.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1048300 0.41% 97.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6810368 2.65% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 256067538 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 257214830 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -532,241 +533,241 @@ system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction -system.cpu.commit.bw_lim_events 6914549 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6810368 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 572164295 # The number of ROB reads -system.cpu.rob.rob_writes 659850863 # The number of ROB writes -system.cpu.timesIdled 5930649 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19653275 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 582672598 # The number of ROB reads +system.cpu.rob.rob_writes 679632792 # The number of ROB writes +system.cpu.timesIdled 5976195 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19603442 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.192174 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.192174 # CPI: Total CPI of All Threads -system.cpu.ipc 0.456168 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.456168 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 451375343 # number of integer regfile reads -system.cpu.int_regfile_writes 234032598 # number of integer regfile writes -system.cpu.fp_regfile_reads 3213912 # number of floating regfile reads -system.cpu.fp_regfile_writes 2009037 # number of floating regfile writes -system.cpu.cc_regfile_reads 102846049 # number of cc regfile reads -system.cpu.cc_regfile_writes 59805449 # number of cc regfile writes -system.cpu.misc_regfile_reads 133386978 # number of misc regfile reads +system.cpu.cpi 2.210030 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.210030 # CPI: Total CPI of All Threads +system.cpu.ipc 0.452483 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.452483 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 453366407 # number of integer regfile reads +system.cpu.int_regfile_writes 236319036 # number of integer regfile writes +system.cpu.fp_regfile_reads 3248620 # number of floating regfile reads +system.cpu.fp_regfile_writes 2037591 # number of floating regfile writes +system.cpu.cc_regfile_reads 102911292 # number of cc regfile reads +system.cpu.cc_regfile_writes 59928663 # number of cc regfile writes +system.cpu.misc_regfile_reads 134914047 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.toL2Bus.throughput 3852301 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7156 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7153 # Transaction distribution +system.cpu.toL2Bus.throughput 4027905 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7620 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7618 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 13 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 132 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 132 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1539 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1539 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13245 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4286 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 17531 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 419584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 548608 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 548608 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 8512 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4433000 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::UpgradeReq 226 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 226 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1544 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1544 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14075 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4490 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 18565 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 443136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 572736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 572736 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 14464 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4714500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 10626750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 11320000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3450631 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3508475 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 4592 # number of replacements -system.cpu.icache.tags.tagsinuse 1628.049417 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22359876 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6557 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3410.077169 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 4955 # number of replacements +system.cpu.icache.tags.tagsinuse 1627.815791 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 23126816 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6924 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3340.094743 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1628.049417 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.794946 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.794946 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 165 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 773 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 124 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 810 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 44744077 # Number of tag accesses -system.cpu.icache.tags.data_accesses 44744077 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 22359876 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22359876 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22359876 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22359876 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22359876 # number of overall hits -system.cpu.icache.overall_hits::total 22359876 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8818 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8818 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8818 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8818 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8818 # number of overall misses -system.cpu.icache.overall_misses::total 8818 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 365022750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 365022750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 365022750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 365022750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 365022750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 365022750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22368694 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22368694 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22368694 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22368694 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22368694 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22368694 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000394 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000394 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000394 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000394 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000394 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000394 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41395.185983 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 41395.185983 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 41395.185983 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 41395.185983 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 41395.185983 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 41395.185983 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 701 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1627.815791 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.794832 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.794832 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1969 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 748 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 136 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 793 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.961426 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 46279236 # Number of tag accesses +system.cpu.icache.tags.data_accesses 46279236 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 23126816 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 23126816 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 23126816 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 23126816 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 23126816 # number of overall hits +system.cpu.icache.overall_hits::total 23126816 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 9227 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 9227 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 9227 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 9227 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 9227 # number of overall misses +system.cpu.icache.overall_misses::total 9227 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 376330999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 376330999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 376330999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 376330999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 376330999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 376330999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 23136043 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 23136043 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 23136043 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 23136043 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 23136043 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 23136043 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000399 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000399 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000399 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000399 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000399 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000399 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40785.845779 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 40785.845779 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 40785.845779 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 40785.845779 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 40785.845779 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 40785.845779 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1569 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 46.733333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 98.062500 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2129 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2129 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2129 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2129 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2129 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2129 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6689 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 6689 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 6689 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6689 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6689 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6689 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 269490250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 269490250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 269490250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 269490250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 269490250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 269490250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000299 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000299 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000299 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40288.570788 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40288.570788 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40288.570788 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 40288.570788 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40288.570788 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 40288.570788 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2076 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2076 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2076 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2076 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2076 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2076 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7151 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 7151 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 7151 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 7151 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 7151 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 7151 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 279771249 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 279771249 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 279771249 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 279771249 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 279771249 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 279771249 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000309 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000309 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000309 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000309 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000309 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000309 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39123.374213 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39123.374213 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39123.374213 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 39123.374213 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39123.374213 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 39123.374213 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2549.629926 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3205 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3824 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.838128 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2580.073748 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3536 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3865 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.914877 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1.731773 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2236.346523 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 311.551630 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000053 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.068248 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.009508 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.077809 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3824 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 169 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 895 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 142 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2568 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.116699 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 75020 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 75020 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 3162 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 38 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 3200 # number of ReadReq hits +system.cpu.l2cache.tags.occ_blocks::writebacks 1.848072 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2267.439437 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 310.786239 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000056 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069197 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.009484 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.078738 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3865 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 196 # 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average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55913.741598 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55532.410136 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56573.394495 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55913.741598 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55458.360442 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55458.360442 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56625.509610 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57552.390641 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56962.962963 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56625.509610 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57552.390641 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56962.962963 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 59 # number of replacements -system.cpu.dcache.tags.tagsinuse 1435.036669 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 66148000 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2003 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33024.463305 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 57 # number of replacements +system.cpu.dcache.tags.tagsinuse 1441.863444 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 66606870 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2012 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33104.806163 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1435.036669 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.350351 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.350351 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1944 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 35 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 71 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 430 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1390 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.474609 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 132302857 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 132302857 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 45633758 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 45633758 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20514059 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20514059 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 66147817 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 66147817 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 66147817 # number of overall hits -system.cpu.dcache.overall_hits::total 66147817 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 938 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 938 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1672 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1672 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2610 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2610 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2610 # number of overall misses -system.cpu.dcache.overall_misses::total 2610 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 59941301 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 59941301 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 112492631 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 112492631 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 172433932 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 172433932 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 172433932 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 172433932 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 45634696 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 45634696 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 1441.863444 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.352017 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.352017 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1955 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 432 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1402 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.477295 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 133220616 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 133220616 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 46092554 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 46092554 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513960 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513960 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 66606514 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 66606514 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 66606514 # number of overall hits +system.cpu.dcache.overall_hits::total 66606514 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1017 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1017 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1771 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1771 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2788 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2788 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2788 # number of overall misses +system.cpu.dcache.overall_misses::total 2788 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 61229380 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 61229380 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 115680725 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 115680725 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 176910105 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 176910105 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 176910105 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 176910105 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 46093571 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 46093571 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 66150427 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 66150427 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 66150427 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 66150427 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000081 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000081 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000039 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000039 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000039 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000039 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63903.305970 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63903.305970 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67280.281699 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 67280.281699 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66066.640613 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66066.640613 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66066.640613 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66066.640613 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 322 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 66609302 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 66609302 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 66609302 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 66609302 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000086 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000086 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60205.880039 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60205.880039 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65319.438171 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65319.438171 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63454.126614 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63454.126614 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63454.126614 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63454.126614 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 94 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 80.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 47 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 13 # number of writebacks system.cpu.dcache.writebacks::total 13 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 470 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 470 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 547 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 547 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 472 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 472 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 472 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 472 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 468 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 468 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1670 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1670 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2138 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2138 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2138 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32985750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 32985750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 108417619 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 108417619 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 141403369 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 141403369 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 141403369 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 141403369 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 549 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 549 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 549 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 549 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 470 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 470 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1769 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1769 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2239 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2239 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2239 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2239 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34113000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 34113000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 111361525 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 111361525 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 145474525 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 145474525 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 145474525 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 145474525 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000081 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000081 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70482.371795 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70482.371795 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64920.729940 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64920.729940 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66138.152011 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66138.152011 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66138.152011 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66138.152011 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000086 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000086 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72580.851064 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72580.851064 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62951.681741 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62951.681741 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64972.990174 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 64972.990174 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64972.990174 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 64972.990174 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |