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authorNilay Vaish <nilay@cs.wisc.edu>2013-01-24 12:29:00 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2013-01-24 12:29:00 -0600
commit9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b (patch)
tree64b85031cb791a21af6059778384d358d992b817 /tests/long/se/70.twolf/ref
parentdbeabedaf0f8d9ec0ea3331db2e44b1add53f79f (diff)
downloadgem5-9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b.tar.xz
regressions: update stats due to branch predictor changes
The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
Diffstat (limited to 'tests/long/se/70.twolf/ref')
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini57
-rwxr-xr-xtests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout10
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt27
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini57
-rwxr-xr-xtests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout10
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt27
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini21
-rwxr-xr-xtests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout8
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt10
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini68
-rwxr-xr-xtests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout16
-rw-r--r--tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt210
-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini37
-rwxr-xr-xtests/long/se/70.twolf/ref/arm/linux/o3-timing/simout12
-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt27
-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini34
-rwxr-xr-xtests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout8
-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt10
-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini87
-rwxr-xr-xtests/long/se/70.twolf/ref/arm/linux/simple-timing/simout10
-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt226
-rw-r--r--tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini17
-rwxr-xr-xtests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout8
-rw-r--r--tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt10
-rw-r--r--tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini64
-rwxr-xr-xtests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout10
-rw-r--r--tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt250
-rw-r--r--tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini37
-rwxr-xr-xtests/long/se/70.twolf/ref/x86/linux/o3-timing/simout10
-rw-r--r--tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt27
-rw-r--r--tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini10
-rwxr-xr-xtests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout4
-rw-r--r--tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt10
-rw-r--r--tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini27
-rwxr-xr-xtests/long/se/70.twolf/ref/x86/linux/simple-timing/simout4
-rw-r--r--tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt210
36 files changed, 863 insertions, 807 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
index 402c5cbcd..8d2d15293 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
@@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,18 +31,13 @@ system_port=system.membus.slave[0]
[system.cpu]
type=InOrderCPU
-children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
+children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
activity=0
+branchPred=system.cpu.branchPred
cachePorts=2
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
cpu_id=0
-defer_registration=false
div16Latency=1
div16RepeatRate=1
div24Latency=1
@@ -57,17 +53,9 @@ dtb=system.cpu.dtb
fetchBuffSize=4
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -76,11 +64,11 @@ memBlockSize=64
multLatency=1
multRepeatRate=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
stageTracing=false
stageWidth=4
+switched_out=false
system=system
threadModel=SMT
tracer=system.cpu.tracer
@@ -88,6 +76,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -95,21 +101,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -126,21 +127,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -163,21 +159,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -204,7 +195,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout
index 483ce54bf..a97feb72b 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout
@@ -1,10 +1,14 @@
+Redirecting stdout to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:02:14
-gem5 started Oct 30 2012 13:10:16
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:29:27
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing
+Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sav
+Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
index 7f70f56b6..2877a6d58 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.041615 # Nu
sim_ticks 41615049000 # Number of ticks simulated
final_tick 41615049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 117678 # Simulator instruction rate (inst/s)
-host_op_rate 117678 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 53286406 # Simulator tick rate (ticks/s)
-host_mem_usage 217828 # Number of bytes of host memory used
-host_seconds 780.97 # Real time elapsed on the host
+host_inst_rate 92405 # Simulator instruction rate (inst/s)
+host_op_rate 92405 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 41842312 # Simulator tick rate (ticks/s)
+host_mem_usage 276220 # Number of bytes of host memory used
+host_seconds 994.57 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
sim_ops 91903056 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory
@@ -185,6 +185,15 @@ system.physmem.writeRowHits 0 # Nu
system.physmem.readRowHitRate 90.26 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 8427500.41 # Average gap between requests
+system.cpu.branchPred.lookups 13412629 # Number of BP lookups
+system.cpu.branchPred.condPredicted 9650146 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 4269214 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 7424481 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 3768497 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 50.757716 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1029619 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 126 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
@@ -221,14 +230,6 @@ system.cpu.workload.num_syscalls 389 # Nu
system.cpu.numCycles 83230099 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.lookups 13412629 # Number of BP lookups
-system.cpu.branch_predictor.condPredicted 9650146 # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect 4269214 # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups 7424481 # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits 3768497 # Number of BTB hits
-system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target.
-system.cpu.branch_predictor.RASInCorrect 126 # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct 50.757716 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 5905664 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 7506965 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 73570547 # Number of Reads from Int. Register File
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
index 231709206..5ab85236e 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
@@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,22 +31,18 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
@@ -56,7 +53,6 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@@ -69,23 +65,15 @@ forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -97,7 +85,6 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
@@ -116,6 +103,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
@@ -125,6 +113,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -132,21 +138,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -426,21 +427,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -463,21 +459,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -504,7 +495,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
index 4f948ec38..be65140ac 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
@@ -1,10 +1,14 @@
+Redirecting stdout to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:02:14
-gem5 started Oct 30 2012 13:23:29
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:04:24
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing
+Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav
+Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
index 91f902e42..32c2b95d3 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.023378 # Nu
sim_ticks 23378067000 # Number of ticks simulated
final_tick 23378067000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 166789 # Simulator instruction rate (inst/s)
-host_op_rate 166789 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 46320112 # Simulator tick rate (ticks/s)
-host_mem_usage 219224 # Number of bytes of host memory used
-host_seconds 504.71 # Real time elapsed on the host
+host_inst_rate 125836 # Simulator instruction rate (inst/s)
+host_op_rate 125836 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 34946651 # Simulator tick rate (ticks/s)
+host_mem_usage 277248 # Number of bytes of host memory used
+host_seconds 668.96 # Real time elapsed on the host
sim_insts 84179709 # Number of instructions simulated
sim_ops 84179709 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 196096 # Number of bytes read from this memory
@@ -185,6 +185,15 @@ system.physmem.writeRowHits 0 # Nu
system.physmem.readRowHitRate 89.46 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 4471683.44 # Average gap between requests
+system.cpu.branchPred.lookups 14833517 # Number of BP lookups
+system.cpu.branchPred.condPredicted 10762267 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 917019 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 8075874 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 6944735 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 85.993603 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1466052 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 3147 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
@@ -221,14 +230,6 @@ system.cpu.workload.num_syscalls 389 # Nu
system.cpu.numCycles 46756135 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 14833517 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 10762267 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 917019 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 8075874 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 6944735 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1466052 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 3147 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 15430530 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 126815242 # Number of instructions fetch has processed
system.cpu.fetch.Branches 14833517 # Number of branches that fetch encountered
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
index 418ddecee..27f048879 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
@@ -10,10 +10,12 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -29,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -42,17 +44,18 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
@@ -67,6 +70,9 @@ size=64
[system.cpu.interrupts]
type=AlphaInterrupts
+[system.cpu.isa]
+type=AlphaISA
+
[system.cpu.itb]
type=AlphaTLB
size=48
@@ -82,7 +88,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
max_stack_size=67108864
@@ -99,14 +105,15 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
-width=64
-master=system.physmem.port[0]
+width=8
+master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout
index fbcfa0aae..b0e6a9854 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 4 2012 11:50:11
-gem5 started Jun 4 2012 13:46:55
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:46:14
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic
Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/smred.sav
Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/smred.sv2
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
index 4c4ae20f6..e64f41702 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.045952 # Nu
sim_ticks 45951567500 # Number of ticks simulated
final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3561938 # Simulator instruction rate (inst/s)
-host_op_rate 3561935 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1780967913 # Simulator tick rate (ticks/s)
-host_mem_usage 209744 # Number of bytes of host memory used
-host_seconds 25.80 # Real time elapsed on the host
+host_inst_rate 1141309 # Simulator instruction rate (inst/s)
+host_op_rate 1141309 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 570654979 # Simulator tick rate (ticks/s)
+host_mem_usage 267644 # Number of bytes of host memory used
+host_seconds 80.52 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
sim_ops 91903056 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 367612356 # Number of bytes read from this memory
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
index 218e77206..8de838008 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
@@ -10,10 +10,12 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -29,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -41,15 +43,16 @@ dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -61,21 +64,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -90,21 +90,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -113,6 +110,9 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=AlphaInterrupts
+[system.cpu.isa]
+type=AlphaISA
+
[system.cpu.itb]
type=AlphaTLB
size=48
@@ -120,23 +120,20 @@ size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=20
is_top_level=false
-latency=10000
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -145,10 +142,10 @@ mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
@@ -158,12 +155,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing
+cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
max_stack_size=67108864
@@ -181,13 +178,14 @@ clock=1000
header_cycles=1
use_default_range=false
width=8
-master=system.physmem.port[0]
+master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout
index 86e423df3..e6fe2a9db 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout
@@ -1,12 +1,14 @@
+Redirecting stdout to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 2 2012 08:30:56
-gem5 started Jul 2 2012 10:59:12
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing
-Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing/smred.sav
-Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing/smred.sv2
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:17:33
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing
+Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/smred.sav
+Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
@@ -23,4 +25,4 @@ Authors: Carl Sechen, Bill Swartz
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 118779533000 because target called exit()
+122 123 124 Exiting @ tick 118729316000 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
index 220e3a05f..aead393ef 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.118729 # Nu
sim_ticks 118729316000 # Number of ticks simulated
final_tick 118729316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 979371 # Simulator instruction rate (inst/s)
-host_op_rate 979371 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1265246648 # Simulator tick rate (ticks/s)
-host_mem_usage 223148 # Number of bytes of host memory used
-host_seconds 93.84 # Real time elapsed on the host
+host_inst_rate 1044383 # Simulator instruction rate (inst/s)
+host_op_rate 1044383 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1349235521 # Simulator tick rate (ticks/s)
+host_mem_usage 276220 # Number of bytes of host memory used
+host_seconds 88.00 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
sim_ops 91903056 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 167744 # Number of bytes read from this memory
@@ -160,106 +160,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 23935.605170
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 157 # number of replacements
-system.cpu.dcache.tagsinuse 1442.043392 # Cycle average of tags in use
-system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 1442.043392 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.352061 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 6499355 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 26495078 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 26495078 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 26495078 # number of overall hits
-system.cpu.dcache.overall_hits::total 26495078 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 475 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 475 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1748 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1748 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 2223 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses
-system.cpu.dcache.overall_misses::total 2223 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 23899000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 23899000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 95048000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 95048000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 118947000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 118947000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 118947000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 118947000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000269 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50313.684211 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 50313.684211 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54375.286041 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 54375.286041 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 53507.422402 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 53507.422402 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
-system.cpu.dcache.writebacks::total 107 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22949000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 22949000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 91552000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 91552000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114501000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 114501000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114501000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 114501000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48313.684211 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48313.684211 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52375.286041 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52375.286041 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 2074.070560 # Cycle average of tags in use
system.cpu.l2cache.total_refs 5956 # Total number of references to valid blocks.
@@ -396,5 +296,105 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 157 # number of replacements
+system.cpu.dcache.tagsinuse 1442.043392 # Cycle average of tags in use
+system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 1442.043392 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.352061 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 6499355 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 26495078 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 26495078 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 26495078 # number of overall hits
+system.cpu.dcache.overall_hits::total 26495078 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 475 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 475 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1748 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1748 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 2223 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses
+system.cpu.dcache.overall_misses::total 2223 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 23899000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 23899000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 95048000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 95048000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 118947000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 118947000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 118947000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 118947000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000269 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50313.684211 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 50313.684211 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54375.286041 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 54375.286041 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 53507.422402 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 53507.422402 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
+system.cpu.dcache.writebacks::total 107 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22949000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 22949000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 91552000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 91552000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114501000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 114501000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114501000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 114501000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48313.684211 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48313.684211 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52375.286041 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52375.286041 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
index 27d1e0868..6de3cd63e 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
@@ -31,22 +31,18 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
@@ -69,23 +65,15 @@ forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -97,7 +85,6 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
@@ -126,6 +113,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -522,7 +527,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/gem5/dist/cpu2000/binaries/arm/linux/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
index 1d7c1b114..0a969e442 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
@@ -1,10 +1,14 @@
+Redirecting stdout to build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:17:24
-gem5 started Jan 5 2013 01:10:37
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 21:30:01
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
+Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav
+Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -21,4 +25,4 @@ info: Increasing stack size by one page.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 74245032000 because target called exit()
+122 123 124 Exiting @ tick 74148853000 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
index 8c8f70dab..b23c244b9 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.074149 # Nu
sim_ticks 74148853000 # Number of ticks simulated
final_tick 74148853000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 112590 # Simulator instruction rate (inst/s)
-host_op_rate 123276 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 48451809 # Simulator tick rate (ticks/s)
-host_mem_usage 247684 # Number of bytes of host memory used
-host_seconds 1530.36 # Real time elapsed on the host
+host_inst_rate 87257 # Simulator instruction rate (inst/s)
+host_op_rate 95539 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 37550131 # Simulator tick rate (ticks/s)
+host_mem_usage 292636 # Number of bytes of host memory used
+host_seconds 1974.66 # Real time elapsed on the host
sim_insts 172303021 # Number of instructions simulated
sim_ops 188656503 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 131648 # Number of bytes read from this memory
@@ -185,6 +185,15 @@ system.physmem.writeRowHits 0 # Nu
system.physmem.readRowHitRate 86.91 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 19492332.94 # Average gap between requests
+system.cpu.branchPred.lookups 94799058 # Number of BP lookups
+system.cpu.branchPred.condPredicted 74801869 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 6279291 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 44724397 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 43048437 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 96.252694 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 4355507 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 88338 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@@ -231,14 +240,6 @@ system.cpu.workload.num_syscalls 400 # Nu
system.cpu.numCycles 148297707 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 94799058 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 74801869 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 6279291 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 44724397 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 43048437 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 4355507 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 88338 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 39650853 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 380235632 # Number of instructions fetch has processed
system.cpu.fetch.Branches 94799058 # Number of branches that fetch encountered
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
index 0be27d977..19646e5c5 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
@@ -10,11 +10,12 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -43,6 +44,7 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -53,6 +55,7 @@ profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
@@ -68,7 +71,7 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.membus.slave[4]
@@ -76,6 +79,23 @@ port=system.membus.slave[4]
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
@@ -84,7 +104,7 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.membus.slave[3]
@@ -100,7 +120,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf
gid=100
input=cin
max_stack_size=67108864
@@ -124,7 +144,7 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout
index 9558000b2..0d1d50648 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 12:39:32
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 21:36:32
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sav
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sv2
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
index 15db555ed..b26eb976b 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.103107 # Nu
sim_ticks 103106766000 # Number of ticks simulated
final_tick 103106766000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2085648 # Simulator instruction rate (inst/s)
-host_op_rate 2283582 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1247954818 # Simulator tick rate (ticks/s)
-host_mem_usage 222132 # Number of bytes of host memory used
-host_seconds 82.62 # Real time elapsed on the host
+host_inst_rate 1465257 # Simulator instruction rate (inst/s)
+host_op_rate 1604314 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 876741604 # Simulator tick rate (ticks/s)
+host_mem_usage 282008 # Number of bytes of host memory used
+host_seconds 117.60 # Real time elapsed on the host
sim_insts 172317409 # Number of instructions simulated
sim_ops 188670891 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 759440204 # Number of bytes read from this memory
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
index a0628b862..4b7535a34 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
@@ -10,11 +10,12 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -42,6 +43,7 @@ dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -50,6 +52,7 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -61,23 +64,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -91,7 +89,7 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
@@ -101,23 +99,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -126,6 +119,23 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
@@ -134,7 +144,7 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
@@ -142,25 +152,20 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=10000
+hit_latency=20
is_top_level=false
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=10000
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -169,10 +174,10 @@ mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@@ -187,7 +192,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf
gid=100
input=cin
max_stack_size=67108864
@@ -211,7 +216,7 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
index 6bb4ad05f..a57db40a7 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 12:07:48
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 21:38:40
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sav
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sv2
@@ -23,4 +25,4 @@ info: Increasing stack size by one page.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 232089948000 because target called exit()
+122 123 124 Exiting @ tick 232072304000 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
index fea3635fb..b91e59a80 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.232072 # Nu
sim_ticks 232072304000 # Number of ticks simulated
final_tick 232072304000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 603492 # Simulator instruction rate (inst/s)
-host_op_rate 660888 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 815011792 # Simulator tick rate (ticks/s)
-host_mem_usage 237088 # Number of bytes of host memory used
-host_seconds 284.75 # Real time elapsed on the host
+host_inst_rate 817822 # Simulator instruction rate (inst/s)
+host_op_rate 895603 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1104464333 # Simulator tick rate (ticks/s)
+host_mem_usage 290584 # Number of bytes of host memory used
+host_seconds 210.12 # Real time elapsed on the host
sim_insts 171842483 # Number of instructions simulated
sim_ops 188185920 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory
@@ -170,114 +170,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 34801.376598
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34801.376598 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 34801.376598 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 40 # number of replacements
-system.cpu.dcache.tagsinuse 1363.611259 # Cycle average of tags in use
-system.cpu.dcache.total_refs 42007358 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1789 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 23480.915595 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 1363.611259 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.332913 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.332913 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 29599357 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 29599357 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 12363187 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 41962544 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 41962544 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 41962544 # number of overall hits
-system.cpu.dcache.overall_hits::total 41962544 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 689 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 689 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1100 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1100 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 1789 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1789 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses
-system.cpu.dcache.overall_misses::total 1789 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 35501000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 35501000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 60164000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 60164000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 95665000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 95665000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 95665000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 95665000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 29600046 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 29600046 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 41964333 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 41964333 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 41964333 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 41964333 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51525.399129 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 51525.399129 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54694.545455 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 54694.545455 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 53474.007826 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 53474.007826 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 53474.007826 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 53474.007826 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 16 # number of writebacks
-system.cpu.dcache.writebacks::total 16 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 689 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 689 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1100 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1100 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1789 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1789 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34123000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 34123000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57964000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 57964000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92087000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 92087000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92087000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 92087000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.000043 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.000043 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49525.399129 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49525.399129 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52694.545455 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52694.545455 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 1675.655740 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1380 # Total number of references to valid blocks.
@@ -414,5 +306,113 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 40 # number of replacements
+system.cpu.dcache.tagsinuse 1363.611259 # Cycle average of tags in use
+system.cpu.dcache.total_refs 42007358 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 1789 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 23480.915595 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 1363.611259 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.332913 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.332913 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 29599357 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 29599357 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 12363187 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 41962544 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 41962544 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 41962544 # number of overall hits
+system.cpu.dcache.overall_hits::total 41962544 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 689 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 689 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1100 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1100 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 1789 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 1789 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses
+system.cpu.dcache.overall_misses::total 1789 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 35501000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 35501000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 60164000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 60164000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 95665000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 95665000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 95665000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 95665000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 29600046 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 29600046 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 41964333 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 41964333 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 41964333 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 41964333 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51525.399129 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 51525.399129 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54694.545455 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 54694.545455 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 53474.007826 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 53474.007826 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 53474.007826 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 53474.007826 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 16 # number of writebacks
+system.cpu.dcache.writebacks::total 16 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 689 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 689 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1100 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1100 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1789 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1789 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34123000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 34123000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57964000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 57964000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92087000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 92087000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92087000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 92087000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.000043 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.000043 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49525.399129 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49525.399129 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52694.545455 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52694.545455 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
index 48cbbbbde..561079b2c 100644
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
@@ -10,10 +10,12 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -29,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -42,17 +44,18 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
@@ -67,6 +70,9 @@ size=64
[system.cpu.interrupts]
type=SparcInterrupts
+[system.cpu.isa]
+type=SparcISA
+
[system.cpu.itb]
type=SparcTLB
size=64
@@ -82,7 +88,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/twolf
gid=100
input=cin
max_stack_size=67108864
@@ -105,8 +111,9 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout
index a6bbf65c9..3551a28b3 100755
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/simout
+Redirecting stderr to build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 13 2012 17:04:37
-gem5 started Aug 13 2012 18:21:10
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 15:49:57
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic
Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sav
Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sv2
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
index fd4974069..8a8554f1f 100644
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.096723 # Nu
sim_ticks 96722945000 # Number of ticks simulated
final_tick 96722945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2917410 # Simulator instruction rate (inst/s)
-host_op_rate 2917413 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1458714810 # Simulator tick rate (ticks/s)
-host_mem_usage 226640 # Number of bytes of host memory used
-host_seconds 66.31 # Real time elapsed on the host
+host_inst_rate 1868868 # Simulator instruction rate (inst/s)
+host_op_rate 1868870 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 934440193 # Simulator tick rate (ticks/s)
+host_mem_usage 277724 # Number of bytes of host memory used
+host_seconds 103.51 # Real time elapsed on the host
sim_insts 193444518 # Number of instructions simulated
sim_ops 193444756 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 773782140 # Number of bytes read from this memory
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
index 27af806dd..5a2c83658 100644
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
@@ -10,10 +10,12 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -29,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -41,15 +43,16 @@ dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -61,21 +64,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -90,21 +90,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -113,6 +110,9 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=SparcInterrupts
+[system.cpu.isa]
+type=SparcISA
+
[system.cpu.itb]
type=SparcTLB
size=64
@@ -120,23 +120,20 @@ size=64
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=20
is_top_level=false
-latency=10000
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -145,10 +142,10 @@ mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
@@ -163,7 +160,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/twolf
gid=100
input=cin
max_stack_size=67108864
@@ -186,8 +183,9 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout
index d049db054..e4c331210 100755
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/simout
+Redirecting stderr to build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 13 2012 17:04:37
-gem5 started Aug 13 2012 18:21:48
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 16:12:46
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing
Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sav
Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sv2
@@ -23,4 +25,4 @@ Authors: Carl Sechen, Bill Swartz
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
info: Increasing stack size by one page.
-122 123 124 Exiting @ tick 270628667000 because target called exit()
+122 123 124 Exiting @ tick 270563082000 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
index 5837aae11..75edc6876 100644
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.270563 # Nu
sim_ticks 270563082000 # Number of ticks simulated
final_tick 270563082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 662631 # Simulator instruction rate (inst/s)
-host_op_rate 662631 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 926794797 # Simulator tick rate (ticks/s)
-host_mem_usage 226156 # Number of bytes of host memory used
-host_seconds 291.93 # Real time elapsed on the host
+host_inst_rate 1012263 # Simulator instruction rate (inst/s)
+host_op_rate 1012264 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1415810765 # Simulator tick rate (ticks/s)
+host_mem_usage 286308 # Number of bytes of host memory used
+host_seconds 191.10 # Real time elapsed on the host
sim_insts 193444518 # Number of instructions simulated
sim_ops 193444756 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory
@@ -128,126 +128,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 23294.433594
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23294.433594 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 2 # number of replacements
-system.cpu.dcache.tagsinuse 1237.203941 # Cycle average of tags in use
-system.cpu.dcache.total_refs 76732337 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1576 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 48688.031091 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 1237.203941 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.302052 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits
-system.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits
-system.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits
-system.cpu.dcache.demand_hits::cpu.data 76709932 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 76709932 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 76709932 # number of overall hits
-system.cpu.dcache.overall_hits::total 76709932 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 498 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 498 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1077 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1077 # number of WriteReq misses
-system.cpu.dcache.SwapReq_misses::cpu.data 1 # number of SwapReq misses
-system.cpu.dcache.SwapReq_misses::total 1 # number of SwapReq misses
-system.cpu.dcache.demand_misses::cpu.data 1575 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses
-system.cpu.dcache.overall_misses::total 1575 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 27390000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 27390000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 59235000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 59235000 # number of WriteReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::cpu.data 55000 # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::total 55000 # number of SwapReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 86625000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 86625000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 86625000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 86625000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 18976439 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses::cpu.data 22406 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses::total 22406 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 76711507 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 76711507 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 76711507 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 76711507 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000009 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000057 # miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000045 # miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_miss_rate::total 0.000045 # miss rate for SwapReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 55000 # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency::total 55000 # average SwapReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 2 # number of writebacks
-system.cpu.dcache.writebacks::total 2 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses
-system.cpu.dcache.SwapReq_mshr_misses::cpu.data 1 # number of SwapReq MSHR misses
-system.cpu.dcache.SwapReq_mshr_misses::total 1 # number of SwapReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1575 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1575 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1575 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1575 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26394000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 26394000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57081000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 57081000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 53000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::total 53000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 83475000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 83475000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 83475000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 83475000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000057 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000045 # mshr miss rate for SwapReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 53000 # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 53000 # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 2678.340865 # Cycle average of tags in use
system.cpu.l2cache.total_refs 8691 # Total number of references to valid blocks.
@@ -379,5 +259,125 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 2 # number of replacements
+system.cpu.dcache.tagsinuse 1237.203941 # Cycle average of tags in use
+system.cpu.dcache.total_refs 76732337 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 1576 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 48688.031091 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 1237.203941 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.302052 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits
+system.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits
+system.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits
+system.cpu.dcache.demand_hits::cpu.data 76709932 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 76709932 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 76709932 # number of overall hits
+system.cpu.dcache.overall_hits::total 76709932 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 498 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 498 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1077 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1077 # number of WriteReq misses
+system.cpu.dcache.SwapReq_misses::cpu.data 1 # number of SwapReq misses
+system.cpu.dcache.SwapReq_misses::total 1 # number of SwapReq misses
+system.cpu.dcache.demand_misses::cpu.data 1575 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses
+system.cpu.dcache.overall_misses::total 1575 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 27390000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 27390000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 59235000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 59235000 # number of WriteReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::cpu.data 55000 # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::total 55000 # number of SwapReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 86625000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 86625000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 86625000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 86625000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 18976439 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::cpu.data 22406 # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::total 22406 # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 76711507 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 76711507 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 76711507 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 76711507 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000009 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000057 # miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000045 # miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_miss_rate::total 0.000045 # miss rate for SwapReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 55000 # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::total 55000 # average SwapReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 2 # number of writebacks
+system.cpu.dcache.writebacks::total 2 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses::cpu.data 1 # number of SwapReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses::total 1 # number of SwapReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1575 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1575 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1575 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1575 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26394000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 26394000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57081000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 57081000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 53000 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::total 53000 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 83475000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 83475000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 83475000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 83475000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000057 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000045 # mshr miss rate for SwapReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 53000 # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 53000 # average SwapReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
index 0c6ed2a4b..c97d77597 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
@@ -31,22 +31,18 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
@@ -69,23 +65,15 @@ forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -97,7 +85,6 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
@@ -126,6 +113,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -514,7 +519,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/gem5/dist/cpu2000/binaries/x86/linux/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
index e62279342..617f03c25 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
@@ -1,10 +1,14 @@
+Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:20:54
-gem5 started Jan 4 2013 23:04:52
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 19:08:30
+gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
+Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav
+Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
index 8854dc0e6..daaac056b 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.082648 # Nu
sim_ticks 82648140000 # Number of ticks simulated
final_tick 82648140000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 100436 # Simulator instruction rate (inst/s)
-host_op_rate 168340 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 62851400 # Simulator tick rate (ticks/s)
-host_mem_usage 270508 # Number of bytes of host memory used
-host_seconds 1314.98 # Real time elapsed on the host
+host_inst_rate 59257 # Simulator instruction rate (inst/s)
+host_op_rate 99320 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 37082179 # Simulator tick rate (ticks/s)
+host_mem_usage 321776 # Number of bytes of host memory used
+host_seconds 2228.78 # Real time elapsed on the host
sim_insts 132071192 # Number of instructions simulated
sim_ops 221362961 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 217728 # Number of bytes read from this memory
@@ -185,18 +185,19 @@ system.physmem.writeRowHits 0 # Nu
system.physmem.readRowHitRate 88.67 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 15454021.88 # Average gap between requests
+system.cpu.branchPred.lookups 19953215 # Number of BP lookups
+system.cpu.branchPred.condPredicted 19953215 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 2011335 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 13840594 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 13098591 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 94.638937 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 165296281 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 19953215 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 19953215 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 2011335 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 13840594 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 13098591 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 25831000 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 218891152 # Number of instructions fetch has processed
system.cpu.fetch.Branches 19953215 # Number of branches that fetch encountered
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
index b8455592d..222b14efd 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
@@ -15,6 +15,7 @@ init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -43,6 +44,7 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -53,6 +55,7 @@ profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
@@ -83,6 +86,9 @@ int_master=system.membus.slave[5]
int_slave=system.membus.master[2]
pio=system.membus.master[1]
+[system.cpu.isa]
+type=X86ISA
+
[system.cpu.itb]
type=X86TLB
children=walker
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout
index 82f0dcff5..7bcffd6bf 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout
@@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atom
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 30 2012 00:35:18
-gem5 started Dec 30 2012 00:50:19
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 18:05:52
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sav
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
index c5a1b588f..4c14b976b 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.131393 # Nu
sim_ticks 131393067500 # Number of ticks simulated
final_tick 131393067500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 889897 # Simulator instruction rate (inst/s)
-host_op_rate 1491546 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 885328041 # Simulator tick rate (ticks/s)
-host_mem_usage 275216 # Number of bytes of host memory used
-host_seconds 148.41 # Real time elapsed on the host
+host_inst_rate 897941 # Simulator instruction rate (inst/s)
+host_op_rate 1505028 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 893330062 # Simulator tick rate (ticks/s)
+host_mem_usage 308196 # Number of bytes of host memory used
+host_seconds 147.08 # Real time elapsed on the host
sim_insts 132071193 # Number of instructions simulated
sim_ops 221362962 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 1387954936 # Number of bytes read from this memory
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
index c487d8f46..368cbf930 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
@@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -42,6 +43,7 @@ dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -50,6 +52,7 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -63,21 +66,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -102,21 +100,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -133,6 +126,9 @@ int_master=system.membus.slave[2]
int_slave=system.membus.master[2]
pio=system.membus.master[1]
+[system.cpu.isa]
+type=X86ISA
+
[system.cpu.itb]
type=X86TLB
children=walker
@@ -152,21 +148,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
index ea7ae2fe0..ff40493ec 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
@@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timi
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 30 2012 00:35:18
-gem5 started Dec 30 2012 01:16:52
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 16:30:54
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sav
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
index 37f9d1943..004f7b9ea 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.250954 # Nu
sim_ticks 250953956000 # Number of ticks simulated
final_tick 250953956000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 472281 # Simulator instruction rate (inst/s)
-host_op_rate 791585 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 897401473 # Simulator tick rate (ticks/s)
-host_mem_usage 283668 # Number of bytes of host memory used
-host_seconds 279.65 # Real time elapsed on the host
+host_inst_rate 580885 # Simulator instruction rate (inst/s)
+host_op_rate 973614 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1103763503 # Simulator tick rate (ticks/s)
+host_mem_usage 316652 # Number of bytes of host memory used
+host_seconds 227.36 # Real time elapsed on the host
sim_insts 132071193 # Number of instructions simulated
sim_ops 221362962 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory
@@ -128,106 +128,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 36414.784832
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.784832 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.784832 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 41 # number of replacements
-system.cpu.dcache.tagsinuse 1363.457576 # Cycle average of tags in use
-system.cpu.dcache.total_refs 77195830 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 40522.745407 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 1363.457576 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.332875 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 56681677 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 56681677 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 20514153 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 77195830 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 77195830 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 77195830 # number of overall hits
-system.cpu.dcache.overall_hits::total 77195830 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1578 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 1905 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses
-system.cpu.dcache.overall_misses::total 1905 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 17692500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 17692500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 86664000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 86664000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 104356500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 104356500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 104356500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 104356500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 56682004 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 56682004 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 77197735 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 77197735 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 77197735 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 77197735 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000077 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54105.504587 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 54105.504587 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54920.152091 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 54920.152091 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 54780.314961 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 54780.314961 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 7 # number of writebacks
-system.cpu.dcache.writebacks::total 7 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 327 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 327 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1578 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1578 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1905 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17038500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 17038500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83508000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 83508000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 100546500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 100546500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 100546500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 100546500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000077 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52105.504587 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52105.504587 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52920.152091 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52920.152091 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 2058.178694 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1862 # Total number of references to valid blocks.
@@ -364,5 +264,105 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 41 # number of replacements
+system.cpu.dcache.tagsinuse 1363.457576 # Cycle average of tags in use
+system.cpu.dcache.total_refs 77195830 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 40522.745407 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 1363.457576 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.332875 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 56681677 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 56681677 # number of ReadReq hits
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+system.cpu.dcache.WriteReq_hits::total 20514153 # number of WriteReq hits
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+system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1578 # number of WriteReq misses
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+system.cpu.dcache.overall_misses::total 1905 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 17692500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 17692500 # number of ReadReq miss cycles
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+system.cpu.dcache.WriteReq_miss_latency::total 86664000 # number of WriteReq miss cycles
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+system.cpu.dcache.demand_miss_latency::total 104356500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 104356500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 104356500 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 56682004 # number of ReadReq accesses(hits+misses)
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+system.cpu.dcache.demand_accesses::cpu.data 77197735 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 77197735 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 77197735 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 77197735 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000077 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
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+system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54105.504587 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 54105.504587 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54920.152091 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 54920.152091 # average WriteReq miss latency
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+system.cpu.dcache.demand_avg_miss_latency::total 54780.314961 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 54780.314961 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 7 # number of writebacks
+system.cpu.dcache.writebacks::total 7 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 327 # number of ReadReq MSHR misses
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+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17038500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 17038500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83508000 # number of WriteReq MSHR miss cycles
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+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 100546500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 100546500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 100546500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 100546500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000077 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52105.504587 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52105.504587 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52920.152091 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52920.152091 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------