diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-11-26 17:05:25 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-11-26 17:05:25 -0600 |
| commit | 2823982a3cbd60a1b21db1a73b78440468df158a (patch) | |
| tree | b955647023da451506138be5a325dfaa2bfd8ee5 /tests/long/se/70.twolf | |
| parent | 9fb93e5cd226ca928ef9cd45bcefcbd94649f4ea (diff) | |
| download | gem5-2823982a3cbd60a1b21db1a73b78440468df158a.tar.xz | |
stats: updates due to changes to ticksToCycles()
Diffstat (limited to 'tests/long/se/70.twolf')
8 files changed, 942 insertions, 698 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini index c08f958c6..8a347565f 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -56,6 +60,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fetchBuffSize=4 function_trace=false function_trace_start=0 @@ -90,6 +95,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -105,6 +111,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -127,11 +134,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.icache] @@ -140,6 +149,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -162,17 +172,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -181,6 +195,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -203,12 +218,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -218,6 +235,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -227,7 +245,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 @@ -241,11 +260,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -265,6 +286,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -276,17 +298,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index d049654a9..5f89f07e5 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.041680 # Nu sim_ticks 41680207000 # Number of ticks simulated final_tick 41680207000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 118687 # Simulator instruction rate (inst/s) -host_op_rate 118687 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53827332 # Simulator tick rate (ticks/s) -host_mem_usage 260144 # Number of bytes of host memory used -host_seconds 774.33 # Real time elapsed on the host +host_inst_rate 93645 # Simulator instruction rate (inst/s) +host_op_rate 93645 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42470141 # Simulator tick rate (ticks/s) +host_mem_usage 279708 # Number of bytes of host memory used +host_seconds 981.40 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory @@ -203,14 +203,14 @@ system.physmem.bytesPerActivate::8064-8065 1 0.13% 99.73% # system.physmem.bytesPerActivate::8128-8129 1 0.13% 99.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 1 0.13% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 743 # Bytes accessed per row activation -system.physmem.totQLat 34068750 # Total ticks spent queuing -system.physmem.totMemAccLat 126422500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 34070750 # Total ticks spent queuing +system.physmem.totMemAccLat 126424500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 24690000 # Total ticks spent in databus transfers system.physmem.totBankLat 67663750 # Total ticks spent accessing banks -system.physmem.avgQLat 6899.30 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6899.71 # Average queueing delay per DRAM burst system.physmem.avgBankLat 13702.66 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25601.96 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25602.37 # Average memory access latency per DRAM burst system.physmem.avgRdBW 7.58 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 7.58 # Average system read bandwidth in MiByte/s @@ -239,9 +239,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 316032 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 316032 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 5776500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 5775000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 45976500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 45973500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu.branchPred.lookups 13412627 # Number of BP lookups system.cpu.branchPred.condPredicted 9650146 # Number of conditional branches predicted @@ -310,9 +310,9 @@ system.cpu.contextSwitches 1 # Nu system.cpu.threadCycles 82971123 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 10519 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7752656 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 75607759 # Number of cycles cpu stages are processed. -system.cpu.activity 90.699835 # Percentage of cycles cpu is active +system.cpu.idleCycles 7752655 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 75607760 # Number of cycles cpu stages are processed. +system.cpu.activity 90.699836 # Percentage of cycles cpu is active system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed @@ -342,9 +342,9 @@ system.cpu.stage2.utilization 59.802183 # Pe system.cpu.stage3.idleCycles 65333914 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 18026501 # Number of cycles 1+ instructions are processed. system.cpu.stage3.utilization 21.624774 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 29500659 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 53859756 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.610710 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 29500658 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 53859757 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.610711 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 7635 # number of replacements system.cpu.icache.tags.tagsinuse 1492.182806 # Cycle average of tags in use system.cpu.icache.tags.total_refs 9945551 # Total number of references to valid blocks. @@ -366,12 +366,12 @@ system.cpu.icache.demand_misses::cpu.inst 11399 # n system.cpu.icache.demand_misses::total 11399 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 11399 # number of overall misses system.cpu.icache.overall_misses::total 11399 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 325867750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 325867750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 325867750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 325867750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 325867750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 325867750 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 325866750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 325866750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 325866750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 325866750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 325866750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 325866750 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 9956950 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 9956950 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 9956950 # number of demand (read+write) accesses @@ -384,12 +384,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001145 system.cpu.icache.demand_miss_rate::total 0.001145 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001145 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001145 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28587.398017 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28587.398017 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28587.398017 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28587.398017 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28587.398017 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28587.398017 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28587.310290 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28587.310290 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28587.310290 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28587.310290 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28587.310290 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28587.310290 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -410,24 +410,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 9520 system.cpu.icache.demand_mshr_misses::total 9520 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 9520 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 9520 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 266340500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 266340500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 266340500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 266340500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 266340500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 266340500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 266339500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 266339500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 266339500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 266339500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 266339500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 266339500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000956 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000956 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27976.943277 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27976.943277 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27976.943277 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 27976.943277 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27976.943277 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 27976.943277 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27976.838235 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27976.838235 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27976.838235 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 27976.838235 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27976.838235 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 27976.838235 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.throughput 18195687 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 9995 # Transaction distribution @@ -486,17 +486,17 @@ system.cpu.l2cache.demand_misses::total 4938 # nu system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4938 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 189283000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 189282000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32395250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 221678250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 122427250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 122427250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 189283000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 154822500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 344105500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 189283000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 154822500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 344105500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 221677250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 122425750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 122425750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 189282000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 154821000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 344103000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 189282000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 154821000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 344103000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 9520 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 9995 # number of ReadReq accesses(hits+misses) @@ -521,17 +521,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.420506 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293487 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.420506 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67746.241947 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67745.884037 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76765.995261 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68929.804104 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71095.963995 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71095.963995 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67746.241947 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72211.986940 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69685.196436 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67746.241947 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72211.986940 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69685.196436 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68929.493159 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71095.092915 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71095.092915 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67745.884037 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72211.287313 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69684.690158 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67745.884037 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72211.287313 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69684.690158 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -554,14 +554,14 @@ system.cpu.l2cache.overall_mshr_misses::total 4938 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 154136500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27132250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 181268750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 101289250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 101289250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 101289750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 101289750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 154136500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 128421500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 282558000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 128422000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 282558500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 154136500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 128421500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 282558000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 128422000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 282558500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321761 # mshr miss rate for ReadReq accesses @@ -576,22 +576,22 @@ system.cpu.l2cache.overall_mshr_miss_rate::total 0.420506 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55166.964925 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64294.431280 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56364.661070 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58820.702671 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58820.702671 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58820.993031 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58820.993031 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55166.964925 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59898.087687 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57221.142163 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59898.320896 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57221.243418 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55166.964925 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59898.087687 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57221.142163 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59898.320896 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57221.243418 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1441.367779 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1441.367780 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26488450 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11915.632029 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1441.367779 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1441.367780 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.351896 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.351896 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 19995621 # number of ReadReq hits @@ -610,14 +610,14 @@ system.cpu.dcache.demand_misses::cpu.data 8851 # n system.cpu.dcache.demand_misses::total 8851 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 8851 # number of overall misses system.cpu.dcache.overall_misses::total 8851 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 41022750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 41022750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 492651500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 492651500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 533674250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 533674250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 533674250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 533674250 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 41023250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 41023250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 492650500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 492650500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 533673750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 533673750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 533673750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 533673750 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -634,19 +634,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000334 system.cpu.dcache.demand_miss_rate::total 0.000334 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000334 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000334 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71096.620451 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 71096.620451 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59542.119894 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59542.119894 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60295.362106 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60295.362106 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60295.362106 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60295.362106 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 23885 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71097.487002 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71097.487002 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59541.999033 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59541.999033 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60295.305615 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60295.305615 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60295.305615 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60295.305615 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 23884 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 841 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.400713 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.399524 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -670,12 +670,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 2223 system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33418750 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 33418750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 124444750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 124444750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 157863500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 157863500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 157863500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 157863500 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 124443250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 124443250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 157862000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 157862000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 157862000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 157862000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -686,12 +686,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70355.263158 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70355.263158 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71192.648741 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71192.648741 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71013.720198 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71013.720198 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71013.720198 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71013.720198 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71191.790618 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71191.790618 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71013.045434 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71013.045434 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71013.045434 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71013.045434 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini index b1f130dee..201e62f46 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,26 +173,31 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -193,16 +206,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -211,22 +227,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -235,22 +255,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -259,10 +283,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -271,124 +297,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -397,10 +444,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -409,16 +458,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -427,10 +479,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -441,6 +495,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -463,17 +518,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -482,6 +541,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -504,12 +564,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -519,6 +581,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -528,7 +591,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 @@ -542,11 +606,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -566,6 +632,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -577,17 +644,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 1aa820757..445692444 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.023462 # Nu sim_ticks 23461709500 # Number of ticks simulated final_tick 23461709500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 165875 # Simulator instruction rate (inst/s) -host_op_rate 165875 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46230980 # Simulator tick rate (ticks/s) -host_mem_usage 261164 # Number of bytes of host memory used -host_seconds 507.49 # Real time elapsed on the host +host_inst_rate 127245 # Simulator instruction rate (inst/s) +host_op_rate 127245 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35464472 # Simulator tick rate (ticks/s) +host_mem_usage 280732 # Number of bytes of host memory used +host_seconds 661.56 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 195968 # Number of bytes read from this memory @@ -204,14 +204,14 @@ system.physmem.bytesPerActivate::8000-8001 1 0.13% 99.60% # system.physmem.bytesPerActivate::8128-8129 2 0.27% 99.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 1 0.13% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 750 # Bytes accessed per row activation -system.physmem.totQLat 37518250 # Total ticks spent queuing -system.physmem.totMemAccLat 134402000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 37518750 # Total ticks spent queuing +system.physmem.totMemAccLat 134402500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26140000 # Total ticks spent in databus transfers system.physmem.totBankLat 70743750 # Total ticks spent accessing banks -system.physmem.avgQLat 7176.41 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7176.50 # Average queueing delay per DRAM burst system.physmem.avgBankLat 13531.70 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25708.11 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25708.21 # Average memory access latency per DRAM burst system.physmem.avgRdBW 14.26 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 14.26 # Average system read bandwidth in MiByte/s @@ -240,17 +240,17 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 334592 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 334592 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6832000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6831000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 49013750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 49012250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu.branchPred.lookups 14847721 # Number of BP lookups system.cpu.branchPred.condPredicted 10774921 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 922205 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 8301784 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6957683 # Number of BTB hits +system.cpu.branchPred.BTBHits 6957680 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.809492 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 83.809456 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1467978 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 3097 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits @@ -289,93 +289,93 @@ system.cpu.workload.num_syscalls 389 # Nu system.cpu.numCycles 46923420 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15463377 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 126961895 # Number of instructions fetch has processed +system.cpu.fetch.icacheStallCycles 15463381 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 126961894 # Number of instructions fetch has processed system.cpu.fetch.Branches 14847721 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 8425661 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22130057 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4473004 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5559399 # Number of cycles fetch has spent blocked +system.cpu.fetch.predictedBranches 8425658 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22130056 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4473003 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5559398 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 52 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 2205 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 25 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 14734161 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 324640 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46671602 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheSquashes 324644 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46671603 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.720324 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.376096 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24541545 52.58% 52.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24541547 52.58% 52.58% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 2361252 5.06% 57.64% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 1192515 2.56% 60.20% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 1742111 3.73% 63.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2755702 5.90% 69.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2755701 5.90% 69.84% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 1149393 2.46% 72.30% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 1220691 2.62% 74.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 771783 1.65% 76.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10936610 23.43% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 771780 1.65% 76.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10936613 23.43% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46671602 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 46671603 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.316425 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.705726 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17289391 # Number of cycles decode is idle +system.cpu.fetch.rate 2.705725 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17289395 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 4257221 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20524695 # Number of cycles decode is running +system.cpu.decode.RunCycles 20524693 # Number of cycles decode is running system.cpu.decode.UnblockCycles 1095542 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3504753 # Number of cycles decode is squashing +system.cpu.decode.SquashCycles 3504752 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 2511898 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12165 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 123979131 # Number of instructions handled by decode +system.cpu.decode.BranchMispred 12167 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 123979126 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 31595 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3504753 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18431775 # Number of cycles rename is idle +system.cpu.rename.SquashCycles 3504752 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18431780 # Number of cycles rename is idle system.cpu.rename.BlockCycles 963421 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 7928 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20455401 # Number of cycles rename is running +system.cpu.rename.RunCycles 20455398 # Number of cycles rename is running system.cpu.rename.UnblockCycles 3308324 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 121154586 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 121154570 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 87 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 400162 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 2430153 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 88974234 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 157440436 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 150394666 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 88974225 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 157440425 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 150394655 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 7045769 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 20546873 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 20546864 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 749 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 744 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 8783261 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 25363135 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8241350 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 25363133 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8241349 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 2569635 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 893782 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 105438340 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 105438334 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 961 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 96565073 # Number of instructions issued +system.cpu.iq.iqInstsIssued 96565072 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 178504 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 20784584 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15622472 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 20784578 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15622466 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 572 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46671602 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 46671603 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.069033 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.876517 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12133901 26.00% 26.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 9340973 20.01% 46.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12133902 26.00% 26.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9340972 20.01% 46.01% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 8404137 18.01% 64.02% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 6285068 13.47% 77.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4921134 10.54% 88.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2853572 6.11% 94.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4921137 10.54% 88.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2853571 6.11% 94.14% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 1727806 3.70% 97.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 798698 1.71% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 798697 1.71% 99.56% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 206313 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46671602 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46671603 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 187905 11.99% 11.99% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 11.99% # attempts to use FU when none available @@ -411,7 +411,7 @@ system.cpu.iq.fu_full::MemWrite 78699 5.02% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58732394 60.82% 60.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58732393 60.82% 60.82% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 479878 0.50% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2798409 2.90% 64.22% # Type of FU issued @@ -444,36 +444,36 @@ system.cpu.iq.FU_type_0::MemRead 23829441 24.68% 92.59% # Ty system.cpu.iq.FU_type_0::MemWrite 7151262 7.41% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 96565073 # Type of FU issued +system.cpu.iq.FU_type_0::total 96565072 # Type of FU issued system.cpu.iq.rate 2.057929 # Inst issue rate system.cpu.iq.fu_busy_cnt 1566710 # FU busy when requested system.cpu.iq.fu_busy_rate 0.016224 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 226434514 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 117518312 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_reads 226434513 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 117518300 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 87069210 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 15112448 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 8740080 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 7062492 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90145383 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 90145382 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7986393 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 1518186 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5366937 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 5366935 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 18425 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 34629 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1740247 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 1740246 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 10551 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 2023 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3504753 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 3504752 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 133474 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 18356 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 115674273 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 115674265 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 366324 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 25363135 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8241350 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 25363133 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8241349 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 961 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2994 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 35 # Number of times the LSQ has become full, causing a stall @@ -483,41 +483,41 @@ system.cpu.iew.predictedNotTakenIncorrect 494157 # N system.cpu.iew.branchMispredicts 1029364 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 95337689 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 23310553 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1227384 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 1227383 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10234972 # number of nop insts executed +system.cpu.iew.exec_nop 10234970 # number of nop insts executed system.cpu.iew.exec_refs 30380075 # number of memory reference insts executed system.cpu.iew.exec_branches 12022158 # Number of branches executed system.cpu.iew.exec_stores 7069522 # Number of stores executed system.cpu.iew.exec_rate 2.031772 # Inst execution rate -system.cpu.iew.wb_sent 94652013 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent 94652012 # cumulative count of insts sent to commit system.cpu.iew.wb_count 94131702 # cumulative count of insts written-back -system.cpu.iew.wb_producers 64474348 # num instructions producing a value -system.cpu.iew.wb_consumers 89850693 # num instructions consuming a value +system.cpu.iew.wb_producers 64474346 # num instructions producing a value +system.cpu.iew.wb_consumers 89850691 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 2.006071 # insts written-back per cycle system.cpu.iew.wb_fanout 0.717572 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23772324 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 23772316 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 910471 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43166849 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 43166851 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 2.129019 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.746086 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16723467 38.74% 38.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9908467 22.95% 61.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16723468 38.74% 38.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9908468 22.95% 61.70% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 4486822 10.39% 72.09% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 2263317 5.24% 77.33% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 1605459 3.72% 81.05% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 1122723 2.60% 83.65% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 719573 1.67% 85.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 818064 1.90% 87.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5518957 12.79% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 818065 1.90% 87.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5518956 12.79% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43166849 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43166851 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -528,12 +528,12 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5518957 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5518956 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 153322231 # The number of ROB reads -system.cpu.rob.rob_writes 234879486 # The number of ROB writes +system.cpu.rob.rob_reads 153322226 # The number of ROB reads +system.cpu.rob.rob_writes 234879469 # The number of ROB writes system.cpu.timesIdled 5401 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 251818 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 251817 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated @@ -542,7 +542,7 @@ system.cpu.cpi_total 0.557420 # CP system.cpu.ipc 1.793981 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.793981 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 129048096 # number of integer regfile reads -system.cpu.int_regfile_writes 70519804 # number of integer regfile writes +system.cpu.int_regfile_writes 70519803 # number of integer regfile writes system.cpu.fp_regfile_reads 6188545 # number of floating regfile reads system.cpu.fp_regfile_writes 6044303 # number of floating regfile writes system.cpu.misc_regfile_reads 714547 # number of misc regfile reads @@ -568,32 +568,32 @@ system.cpu.toL2Bus.respLayer0.utilization 0.1 # L system.cpu.toL2Bus.respLayer1.occupancy 3547000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.icache.tags.replacements 9576 # number of replacements -system.cpu.icache.tags.tagsinuse 1596.482982 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 14719875 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1596.482984 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 14719872 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 11510 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1278.877063 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1278.876803 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1596.482982 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1596.482984 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.779533 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.779533 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14719875 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14719875 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14719875 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14719875 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14719875 # number of overall hits -system.cpu.icache.overall_hits::total 14719875 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14285 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14285 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14285 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14285 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14285 # number of overall misses -system.cpu.icache.overall_misses::total 14285 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 413142250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 413142250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 413142250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 413142250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 413142250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 413142250 # number of overall miss cycles +system.cpu.icache.ReadReq_hits::cpu.inst 14719872 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14719872 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14719872 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14719872 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14719872 # number of overall hits +system.cpu.icache.overall_hits::total 14719872 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14288 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14288 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14288 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14288 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14288 # number of overall misses +system.cpu.icache.overall_misses::total 14288 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 413271500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 413271500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 413271500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 413271500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 413271500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 413271500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 14734160 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 14734160 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 14734160 # number of demand (read+write) accesses @@ -606,12 +606,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000970 system.cpu.icache.demand_miss_rate::total 0.000970 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000970 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000970 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28921.403570 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28921.403570 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28921.403570 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28921.403570 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28921.403570 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28921.403570 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28924.377100 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28924.377100 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28924.377100 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28924.377100 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28924.377100 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28924.377100 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 548 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked @@ -620,45 +620,45 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 68.500000 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2775 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2775 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2775 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2775 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2775 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2775 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2778 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2778 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2778 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2778 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2778 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2778 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11510 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 11510 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 11510 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 11510 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 11510 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 11510 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 303669750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 303669750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 303669750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 303669750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 303669750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 303669750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 303668250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 303668250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 303668250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 303668250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 303668250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 303668250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000781 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000781 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000781 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000781 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000781 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000781 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26383.123371 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26383.123371 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26383.123371 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 26383.123371 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26383.123371 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 26383.123371 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26382.993050 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26382.993050 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26382.993050 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 26382.993050 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26382.993050 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 26382.993050 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2409.583503 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2409.583505 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 8517 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3590 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 2.372423 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 17.678720 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2010.447961 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2010.447963 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 381.456822 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000540 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061354 # Average percentage of cache occupancy @@ -688,17 +688,17 @@ system.cpu.l2cache.demand_misses::total 5228 # nu system.cpu.l2cache.overall_misses::cpu.inst 3062 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2166 # number of overall misses system.cpu.l2cache.overall_misses::total 5228 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 207669750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 34561250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 242231000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 124309250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 124309250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 207669750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 158870500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 366540250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 207669750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 158870500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 366540250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 207668250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 34560750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 242229000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 124310250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 124310250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 207668250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 158871000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 366539250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 207668250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 158871000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 366539250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 11510 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 516 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 12026 # number of ReadReq accesses(hits+misses) @@ -723,17 +723,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.380025 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.266030 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.963952 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.380025 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67821.603527 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74970.173536 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68757.025263 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72908.651026 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72908.651026 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67821.603527 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73347.414589 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70110.988906 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67821.603527 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73347.414589 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70110.988906 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67821.113651 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74969.088937 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68756.457565 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72909.237537 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72909.237537 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67821.113651 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73347.645429 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70110.797628 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67821.113651 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73347.645429 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70110.797628 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -753,17 +753,17 @@ system.cpu.l2cache.demand_mshr_misses::total 5228 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3062 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2166 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5228 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 168835250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 168834750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 28858250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 197693500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 103389750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 103389750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 168835250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 132248000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 301083250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 168835250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 132248000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 301083250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 197693000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 103390750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 103390750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 168834750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 132249000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 301083750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 168834750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 132249000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 301083750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.266030 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.893411 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.292949 # mshr miss rate for ReadReq accesses @@ -775,25 +775,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.380025 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.266030 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963952 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.380025 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55138.879817 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55138.716525 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62599.240781 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56115.100766 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60639.149560 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60639.149560 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55138.879817 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61056.325023 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57590.522188 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55138.879817 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61056.325023 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57590.522188 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56114.958842 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60639.736070 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60639.736070 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55138.716525 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61056.786704 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57590.617827 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55138.716525 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61056.786704 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57590.617827 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 159 # number of replacements -system.cpu.dcache.tags.tagsinuse 1459.152637 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1459.152638 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 28079168 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2247 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 12496.291945 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1459.152637 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1459.152638 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.356238 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.356238 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 21586035 # number of ReadReq hits @@ -816,16 +816,16 @@ system.cpu.dcache.demand_misses::cpu.data 9208 # n system.cpu.dcache.demand_misses::total 9208 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9208 # number of overall misses system.cpu.dcache.overall_misses::total 9208 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 58289750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 58289750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 505815795 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 505815795 # number of WriteReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 58289250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 58289250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 505816795 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 505816795 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 564105545 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 564105545 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 564105545 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 564105545 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 564106045 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 564106045 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 564106045 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 564106045 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 21587009 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 21587009 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -846,16 +846,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000328 system.cpu.dcache.demand_miss_rate::total 0.000328 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000328 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000328 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59845.739220 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59845.739220 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61430.142701 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61430.142701 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59845.225873 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59845.225873 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61430.264149 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61430.264149 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61262.548328 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61262.548328 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61262.548328 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61262.548328 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61262.602628 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61262.602628 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61262.602628 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61262.602628 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 24052 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 336 # number of cycles access was blocked @@ -884,16 +884,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2246 system.cpu.dcache.demand_mshr_misses::total 2246 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2246 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2246 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 35552500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 35552500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 126440497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 126440497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 35552000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 35552000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 126441497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 126441497 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161992997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 161992997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161992997 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 161992997 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161993497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 161993497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161993497 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 161993497 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses @@ -904,16 +904,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000080 system.cpu.dcache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69033.980583 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69033.980583 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73044.770075 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73044.770075 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69033.009709 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69033.009709 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73045.347776 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73045.347776 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72125.109973 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72125.109973 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72125.109973 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72125.109973 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72125.332591 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72125.332591 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72125.332591 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72125.332591 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini index d981a43f0..90382fb26 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,18 +173,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -185,15 +196,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -202,16 +216,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -220,22 +237,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -244,22 +265,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -268,10 +293,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -280,124 +307,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -406,10 +454,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -418,16 +468,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -436,10 +489,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -450,6 +505,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -472,14 +528,17 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -498,12 +557,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -514,6 +575,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -536,12 +598,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -551,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -560,7 +625,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/twolf +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 @@ -574,11 +640,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -598,6 +666,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -609,17 +678,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 4425c72f1..ac21abc99 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.074220 # Nu sim_ticks 74219948500 # Number of ticks simulated final_tick 74219948500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 110839 # Simulator instruction rate (inst/s) -host_op_rate 121359 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47744278 # Simulator tick rate (ticks/s) -host_mem_usage 278976 # Number of bytes of host memory used -host_seconds 1554.53 # Real time elapsed on the host +host_inst_rate 84730 # Simulator instruction rate (inst/s) +host_op_rate 92772 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36497737 # Simulator tick rate (ticks/s) +host_mem_usage 298520 # Number of bytes of host memory used +host_seconds 2033.55 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 188656503 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 131072 # Number of bytes read from this memory @@ -197,14 +197,14 @@ system.physmem.bytesPerActivate::3712-3713 1 0.14% 99.72% # system.physmem.bytesPerActivate::6656-6657 1 0.14% 99.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 1 0.14% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 717 # Bytes accessed per row activation -system.physmem.totQLat 25205500 # Total ticks spent queuing -system.physmem.totMemAccLat 100715500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 25203500 # Total ticks spent queuing +system.physmem.totMemAccLat 100713500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 18970000 # Total ticks spent in databus transfers system.physmem.totBankLat 56540000 # Total ticks spent accessing banks -system.physmem.avgQLat 6643.52 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6642.99 # Average queueing delay per DRAM burst system.physmem.avgBankLat 14902.48 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26545.99 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26545.47 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.27 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.27 # Average system read bandwidth in MiByte/s @@ -233,18 +233,18 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 242752 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 242752 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 4683500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4682500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 35533250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 35532750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 94784279 # Number of BP lookups -system.cpu.branchPred.condPredicted 74784012 # Number of conditional branches predicted +system.cpu.branchPred.lookups 94784274 # Number of BP lookups +system.cpu.branchPred.condPredicted 74784006 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 6281562 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 44678427 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 44678423 # Number of BTB lookups system.cpu.branchPred.BTBHits 43050018 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 96.355268 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 4356637 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 96.355276 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 4356639 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 88400 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses @@ -292,95 +292,95 @@ system.cpu.workload.num_syscalls 400 # Nu system.cpu.numCycles 148439898 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 39656913 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 380179952 # Number of instructions fetch has processed -system.cpu.fetch.Branches 94784279 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 47406655 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80370667 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 27283129 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7220970 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 39656921 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 380179930 # Number of instructions fetch has processed +system.cpu.fetch.Branches 94784274 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 47406657 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80370665 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 27283127 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7220968 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 44 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 6188 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.IcacheWaitRetryStallCycles 50 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 36850892 # Number of cache lines fetched +system.cpu.fetch.CacheLines 36850894 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 1831983 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 148240575 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 148240577 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.801601 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.152871 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68038754 45.90% 45.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68038757 45.90% 45.90% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 5265463 3.55% 49.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10540667 7.11% 56.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10540668 7.11% 56.56% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 10285704 6.94% 63.50% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 8660470 5.84% 69.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6545128 4.42% 73.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6545129 4.42% 73.76% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 6246382 4.21% 77.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8002829 5.40% 83.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 24655178 16.63% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8002830 5.40% 83.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 24655174 16.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 148240575 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 148240577 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.638536 # Number of branch fetches per cycle system.cpu.fetch.rate 2.561171 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45513789 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5886753 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74804125 # Number of cycles decode is running +system.cpu.decode.IdleCycles 45513795 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5886752 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74804124 # Number of cycles decode is running system.cpu.decode.UnblockCycles 1203493 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 20832415 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14327913 # Number of times decode resolved a branch +system.cpu.decode.SquashCycles 20832413 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14327914 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 164349 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 392779898 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 392779880 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 733794 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 20832415 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 50900742 # Number of cycles rename is idle +system.cpu.rename.SquashCycles 20832413 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50900748 # Number of cycles rename is idle system.cpu.rename.BlockCycles 730699 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 603190 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 70558310 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4615219 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 371308094 # Number of instructions processed by rename +system.cpu.rename.serializeStallCycles 603191 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 70558309 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4615217 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 371308082 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 339277 # Number of times rename has blocked due to IQ full +system.cpu.rename.IQFullEvents 339275 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 3661219 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 233 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 631703486 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1581699955 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1506871299 # Number of integer rename lookups +system.cpu.rename.FullRegisterEvents 231 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 631703471 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1581699910 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1506871257 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 3203425 # Number of floating rename lookups system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 333659347 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 333659332 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 25072 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 25068 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 13010245 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 43012685 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 43012682 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 16416405 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 5733542 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 3666500 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 329190158 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 329190147 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 47154 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 249456619 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 789371 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 139503403 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 362002811 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 249456617 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 789368 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 139503392 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 362002773 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1938 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 148240575 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 148240577 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 1.682782 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.761427 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56059831 37.82% 37.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56059832 37.82% 37.82% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 22638796 15.27% 53.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 24824163 16.75% 69.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24824164 16.75% 69.83% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 20343400 13.72% 83.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12534795 8.46% 92.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12534797 8.46% 92.01% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 6516114 4.40% 96.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4026097 2.72% 99.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4026095 2.72% 99.12% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 1116067 0.75% 99.88% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 181312 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 148240575 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 148240577 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 965215 38.57% 38.57% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 5593 0.22% 38.79% # attempts to use FU when none available @@ -416,7 +416,7 @@ system.cpu.iq.fu_full::MemWrite 372730 14.89% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 194899965 78.13% 78.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 194899963 78.13% 78.13% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 979613 0.39% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued @@ -449,21 +449,21 @@ system.cpu.iq.FU_type_0::MemRead 38355278 15.38% 94.41% # Ty system.cpu.iq.FU_type_0::MemWrite 13948063 5.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 249456619 # Type of FU issued +system.cpu.iq.FU_type_0::total 249456617 # Type of FU issued system.cpu.iq.rate 1.680523 # Inst issue rate system.cpu.iq.fu_busy_cnt 2502654 # FU busy when requested system.cpu.iq.fu_busy_rate 0.010032 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 646705831 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 466563436 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_reads 646705826 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 466563414 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 237885445 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 3740007 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2195697 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 1842613 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 250082854 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 250082852 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 1876419 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 2013198 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13163201 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 13163198 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 11604 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 18881 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 3771771 # Number of stores squashed @@ -472,12 +472,12 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 18 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 107 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 20832415 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 20832413 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 18550 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 893 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 329254508 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 329254497 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 785294 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 43012685 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 43012682 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 16416405 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 24746 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 188 # Number of times the IQ has become full, causing a stall @@ -488,7 +488,7 @@ system.cpu.iew.predictedNotTakenIncorrect 3760086 # N system.cpu.iew.branchMispredicts 7650044 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 242960519 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 36851938 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6496100 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 6496098 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 17196 # number of nop insts executed system.cpu.iew.exec_refs 50500394 # number of memory reference insts executed @@ -497,23 +497,23 @@ system.cpu.iew.exec_stores 13648456 # Nu system.cpu.iew.exec_rate 1.636760 # Inst execution rate system.cpu.iew.wb_sent 240785663 # cumulative count of insts sent to commit system.cpu.iew.wb_count 239728058 # cumulative count of insts written-back -system.cpu.iew.wb_producers 148474079 # num instructions producing a value -system.cpu.iew.wb_consumers 267261472 # num instructions consuming a value +system.cpu.iew.wb_producers 148474078 # num instructions producing a value +system.cpu.iew.wb_consumers 267261470 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 1.614984 # insts written-back per cycle system.cpu.iew.wb_fanout 0.555539 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 140583620 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 140583609 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 6128235 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 127408160 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 127408164 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 1.480838 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.185451 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 57701826 45.29% 45.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 31696936 24.88% 70.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13777779 10.81% 80.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7640619 6.00% 86.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 57701829 45.29% 45.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 31696937 24.88% 70.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13777780 10.81% 80.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7640618 6.00% 86.98% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 4387787 3.44% 90.42% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 1321958 1.04% 91.46% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 1703212 1.34% 92.80% # Number of insts commited each cycle @@ -522,7 +522,7 @@ system.cpu.commit.committed_per_cycle::8 7870029 6.18% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 127408160 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 127408164 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317409 # Number of instructions committed system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -535,10 +535,10 @@ system.cpu.commit.int_insts 150106217 # Nu system.cpu.commit.function_calls 1848934 # Number of function calls committed. system.cpu.commit.bw_lim_events 7870029 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 448787441 # The number of ROB reads -system.cpu.rob.rob_writes 679451137 # The number of ROB writes +system.cpu.rob.rob_reads 448787434 # The number of ROB reads +system.cpu.rob.rob_writes 679451113 # The number of ROB writes system.cpu.timesIdled 2805 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 199323 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 199321 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303021 # Number of Instructions Simulated system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated @@ -574,49 +574,49 @@ system.cpu.toL2Bus.respLayer1.occupancy 3047739 # La system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.icache.tags.replacements 2394 # number of replacements system.cpu.icache.tags.tagsinuse 1347.740549 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 36845555 # Total number of references to valid blocks. +system.cpu.icache.tags.total_refs 36845557 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4125 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8932.255758 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 8932.256242 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 1347.740549 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.658076 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.658076 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 36845555 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 36845555 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 36845555 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 36845555 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 36845555 # number of overall hits -system.cpu.icache.overall_hits::total 36845555 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 36845557 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 36845557 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 36845557 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 36845557 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 36845557 # number of overall hits +system.cpu.icache.overall_hits::total 36845557 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 5337 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 5337 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 5337 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 5337 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 5337 # number of overall misses system.cpu.icache.overall_misses::total 5337 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 225944745 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 225944745 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 225944745 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 225944745 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 225944745 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 225944745 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 36850892 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 36850892 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 36850892 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 36850892 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 36850892 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 36850892 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 225938245 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 225938245 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 225938245 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 225938245 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 225938245 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 225938245 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 36850894 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 36850894 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 36850894 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 36850894 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 36850894 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 36850894 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000145 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000145 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000145 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000145 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000145 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000145 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42335.534008 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42335.534008 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42335.534008 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42335.534008 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42335.534008 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42335.534008 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42334.316095 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42334.316095 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42334.316095 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42334.316095 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42334.316095 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42334.316095 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 1128 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked @@ -637,33 +637,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4126 system.cpu.icache.demand_mshr_misses::total 4126 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4126 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4126 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168091004 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 168091004 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168091004 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 168091004 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168091004 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 168091004 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168088504 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 168088504 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168088504 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 168088504 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168088504 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 168088504 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000112 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000112 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40739.458071 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40739.458071 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40739.458071 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 40739.458071 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40739.458071 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 40739.458071 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40738.852157 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40738.852157 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40738.852157 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 40738.852157 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40738.852157 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 40738.852157 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 1967.449765 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 1967.449764 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2162 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2732 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.791362 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 4.994098 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1425.569688 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1425.569687 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 536.885979 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043505 # Average percentage of cache occupancy @@ -693,17 +693,17 @@ system.cpu.l2cache.demand_misses::total 3809 # nu system.cpu.l2cache.overall_misses::cpu.inst 2053 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1756 # number of overall misses system.cpu.l2cache.overall_misses::total 3809 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 143228000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51384000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 194612000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 72291750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 72291750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 143228000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 123675750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 266903750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 143228000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 123675750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 266903750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 143225500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51383000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 194608500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 72292250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 72292250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 143225500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 123675250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 266900750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 143225500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 123675250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 266900750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 4126 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 773 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 4899 # number of ReadReq accesses(hits+misses) @@ -728,17 +728,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.637170 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.497576 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.948164 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.637170 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69765.221627 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75013.138686 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71078.159240 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67499.299720 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67499.299720 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69765.221627 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70430.381549 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70071.869257 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69765.221627 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70430.381549 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70071.869257 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69764.003897 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75011.678832 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71076.880935 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67499.766573 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67499.766573 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69764.003897 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70430.096811 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70071.081649 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69764.003897 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70430.096811 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70071.081649 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -767,17 +767,17 @@ system.cpu.l2cache.demand_mshr_misses::total 3794 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2049 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1745 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3794 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117254500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42298000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159552500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117253000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42297000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159550000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 58841750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 58841750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117254500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101139750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 218394250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117254500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101139750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 218394250 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117253000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101138750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 218391750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117253000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101138750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 218391750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871928 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.555828 # mshr miss rate for ReadReq accesses @@ -789,17 +789,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.634660 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942225 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.634660 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57225.231820 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62756.676558 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58594.381197 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57224.499756 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62755.192878 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58593.463092 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54940.943044 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54940.943044 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57225.231820 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57959.742120 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57563.060095 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57225.231820 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57959.742120 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57563.060095 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57224.499756 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57959.169054 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57562.401160 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57224.499756 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57959.169054 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57562.401160 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 57 # number of replacements system.cpu.dcache.tags.tagsinuse 1406.103135 # Cycle average of tags in use @@ -832,16 +832,16 @@ system.cpu.dcache.demand_misses::cpu.data 9625 # n system.cpu.dcache.demand_misses::total 9625 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9625 # number of overall misses system.cpu.dcache.overall_misses::total 9625 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 121870727 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 121870727 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 465623246 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 465623246 # number of WriteReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 121862727 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 121862727 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 465623746 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 465623746 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 142500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 587493973 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 587493973 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 587493973 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 587493973 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 587486473 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 587486473 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 587486473 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 587486473 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 34386613 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 34386613 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) @@ -864,16 +864,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64075.040484 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 64075.040484 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60290.463033 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60290.463033 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64070.834385 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 64070.834385 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60290.527774 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60290.527774 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61038.334857 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61038.334857 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61038.334857 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61038.334857 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61037.555636 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61037.555636 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61037.555636 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61037.555636 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 592 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 314 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked @@ -902,14 +902,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1852 system.cpu.dcache.demand_mshr_misses::total 1852 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1852 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1852 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53114761 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 53114761 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73392998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 73392998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126507759 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 126507759 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126507759 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 126507759 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53113761 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 53113761 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73393498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 73393498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126507259 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 126507259 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126507259 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 126507259 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses @@ -918,14 +918,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68623.722222 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68623.722222 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68082.558442 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68082.558442 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68308.725162 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68308.725162 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68308.725162 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68308.725162 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68622.430233 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68622.430233 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68083.022263 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68083.022263 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68308.455184 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68308.455184 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68308.455184 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68308.455184 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini index 5e4a8f947..210f89c36 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -125,6 +131,7 @@ icache_port=system.cpu.icache.cpu_side type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu_clk_domain +eventq_index=0 [system.cpu.branchPred] type=BranchPredictor @@ -133,6 +140,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -148,6 +156,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -170,18 +179,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[3] @@ -190,15 +202,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -207,16 +222,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -225,22 +243,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -249,22 +271,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -273,10 +299,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -285,124 +313,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -411,10 +460,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -423,16 +474,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -441,10 +495,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -455,6 +511,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -477,12 +534,14 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=X86LocalApic clk_domain=system.cpu.apic_clk_domain +eventq_index=0 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -493,16 +552,19 @@ pio=system.membus.master[1] [system.cpu.isa] type=X86ISA +eventq_index=0 [system.cpu.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[2] @@ -513,6 +575,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -535,12 +598,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -550,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -559,7 +625,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/twolf +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 @@ -573,11 +640,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -597,6 +666,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -608,17 +678,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 003c2ae7a..3f8722e89 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.144463 # Nu sim_ticks 144463317000 # Number of ticks simulated final_tick 144463317000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66822 # Simulator instruction rate (inst/s) -host_op_rate 111999 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 73091533 # Simulator tick rate (ticks/s) -host_mem_usage 308580 # Number of bytes of host memory used -host_seconds 1976.47 # Real time elapsed on the host +host_inst_rate 55445 # Simulator instruction rate (inst/s) +host_op_rate 92931 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60647702 # Simulator tick rate (ticks/s) +host_mem_usage 328672 # Number of bytes of host memory used +host_seconds 2382.01 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 217088 # Number of bytes read from this memory @@ -207,14 +207,14 @@ system.physmem.bytesPerActivate::5312 1 0.10% 99.79% # By system.physmem.bytesPerActivate::5696 1 0.10% 99.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::5952 1 0.10% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 957 # Bytes accessed per row activation -system.physmem.totQLat 28805000 # Total ticks spent queuing -system.physmem.totMemAccLat 137868750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 28783000 # Total ticks spent queuing +system.physmem.totMemAccLat 137846750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26770000 # Total ticks spent in databus transfers system.physmem.totBankLat 82293750 # Total ticks spent accessing banks -system.physmem.avgQLat 5380.09 # Average queueing delay per DRAM burst +system.physmem.avgQLat 5375.98 # Average queueing delay per DRAM burst system.physmem.avgBankLat 15370.52 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25750.61 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25746.50 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.37 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.37 # Average system read bandwidth in MiByte/s @@ -247,12 +247,12 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 342656 system.membus.tot_pkt_size::total 342656 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 342656 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6948500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6950000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 50662837 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 18648234 # Number of BP lookups -system.cpu.branchPred.condPredicted 18648234 # Number of conditional branches predicted +system.cpu.branchPred.lookups 18648233 # Number of BP lookups +system.cpu.branchPred.condPredicted 18648233 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1490176 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 11407549 # Number of BTB lookups system.cpu.branchPred.BTBHits 10790529 # Number of BTB hits @@ -264,90 +264,90 @@ system.cpu.workload.num_syscalls 400 # Nu system.cpu.numCycles 289221873 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 23458037 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 206724223 # Number of instructions fetch has processed -system.cpu.fetch.Branches 18648234 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 23458043 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 206724218 # Number of instructions fetch has processed +system.cpu.fetch.Branches 18648233 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 12110896 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 54209099 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 15518775 # Number of cycles fetch has spent squashing +system.cpu.fetch.Cycles 54209097 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 15518774 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 178161359 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1571 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 9111 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 38 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22353213 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 224062 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 269612466 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 22353211 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 224061 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 269612469 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 1.268180 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 2.756310 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 216842558 80.43% 80.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 216842563 80.43% 80.43% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 2848142 1.06% 81.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2312056 0.86% 82.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2312055 0.86% 82.34% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 2633842 0.98% 83.32% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 3218714 1.19% 84.51% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 3388946 1.26% 85.77% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 3831195 1.42% 87.19% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 2559437 0.95% 88.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 31977576 11.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 31977575 11.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 269612466 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 269612469 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.064477 # Number of branch fetches per cycle system.cpu.fetch.rate 0.714760 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36899349 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 167130008 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 41545231 # Number of cycles decode is running +system.cpu.decode.IdleCycles 36899359 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 167130004 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 41545229 # Number of cycles decode is running system.cpu.decode.UnblockCycles 10264627 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 13773251 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 336001478 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 13773251 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 44972476 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 116686700 # Number of cycles rename is blocking +system.cpu.decode.SquashCycles 13773250 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 336001462 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 13773250 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 44972487 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 116686698 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 32545 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 42701692 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 51445802 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 329633797 # Number of instructions processed by rename +system.cpu.rename.RunCycles 42701689 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 51445800 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 329633775 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 10827 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 26123597 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22730551 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 382342114 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 917586762 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 605878307 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 22730549 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 382342090 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 917586713 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 605878272 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4127660 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 122912664 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 122912640 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 2051 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 2042 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 105140053 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 84507278 # Number of loads inserted to the mem dependence unit. +system.cpu.rename.skidInsts 105140052 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 84507276 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 30107186 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 58355212 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 18979888 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 322730912 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 322730905 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 4069 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 260501997 # Number of instructions issued +system.cpu.iq.iqInstsIssued 260501994 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 116055 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 100987198 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 210203666 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 100987191 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 210203655 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2824 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 269612466 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 269612469 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.966209 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.343680 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 143429906 53.20% 53.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55567349 20.61% 73.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34108146 12.65% 86.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 19044984 7.06% 93.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10887633 4.04% 97.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4152281 1.54% 99.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1816698 0.67% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 143429912 53.20% 53.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 55567346 20.61% 73.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 34108148 12.65% 86.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19044980 7.06% 93.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10887634 4.04% 97.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4152283 1.54% 99.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1816697 0.67% 99.78% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 472473 0.18% 99.95% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 132996 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 269612466 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 269612469 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 130605 4.82% 4.82% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 4.82% # attempts to use FU when none available @@ -383,7 +383,7 @@ system.cpu.iq.fu_full::MemWrite 302412 11.15% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 1210810 0.46% 0.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 162055945 62.21% 62.67% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 162055944 62.21% 62.67% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 789191 0.30% 62.98% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 7035649 2.70% 65.68% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 1445882 0.56% 66.23% # Type of FU issued @@ -412,26 +412,26 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.23% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.23% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.23% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 65414515 25.11% 91.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 65414513 25.11% 91.34% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 22550005 8.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 260501997 # Type of FU issued -system.cpu.iq.rate 0.900700 # Inst issue rate +system.cpu.iq.FU_type_0::total 260501994 # Type of FU issued +system.cpu.iq.rate 0.900699 # Inst issue rate system.cpu.iq.fu_busy_cnt 2712094 # FU busy when requested system.cpu.iq.fu_busy_rate 0.010411 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 788557581 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 420384882 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 255147074 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_reads 788557578 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 420384868 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 255147075 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4887028 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 3615221 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2349564 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 259544029 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 259544026 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2459252 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18903383 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 18903382 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 27857691 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 25993 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 27857689 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 25992 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 283319 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 9591469 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address @@ -439,57 +439,57 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 49752 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 13773251 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 85040641 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 13773250 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 85040639 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 5471570 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 322734981 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 322734974 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 133239 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 84507278 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 84507276 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 30107186 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 1979 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2708196 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 13910 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 283319 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 639398 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 901241 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1540639 # Number of branch mispredicts detected at execute +system.cpu.iew.predictedNotTakenIncorrect 901242 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1540640 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 258732431 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 64645019 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1769566 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 1769563 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed system.cpu.iew.exec_refs 86992194 # number of memory reference insts executed -system.cpu.iew.exec_branches 14265860 # Number of branches executed +system.cpu.iew.exec_branches 14265859 # Number of branches executed system.cpu.iew.exec_stores 22347175 # Number of stores executed system.cpu.iew.exec_rate 0.894581 # Inst execution rate -system.cpu.iew.wb_sent 258096694 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 257496638 # cumulative count of insts written-back +system.cpu.iew.wb_sent 258096693 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 257496639 # cumulative count of insts written-back system.cpu.iew.wb_producers 205928299 # num instructions producing a value -system.cpu.iew.wb_consumers 369130532 # num instructions consuming a value +system.cpu.iew.wb_consumers 369130530 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 0.890308 # insts written-back per cycle system.cpu.iew.wb_fanout 0.557874 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 101448847 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 101448840 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1491529 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 255839215 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 255839219 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 0.865244 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 1.654327 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 156486613 61.17% 61.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 156486617 61.17% 61.17% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 57197635 22.36% 83.52% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 14067876 5.50% 89.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12054069 4.71% 93.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4176262 1.63% 95.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2944385 1.15% 96.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 904563 0.35% 96.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1049057 0.41% 97.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6958755 2.72% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12054068 4.71% 93.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4176261 1.63% 95.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2944387 1.15% 96.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 904564 0.35% 96.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1049058 0.41% 97.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6958753 2.72% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 255839215 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 255839219 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -500,12 +500,12 @@ system.cpu.commit.branches 12326938 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 219019985 # Number of committed integer instructions. system.cpu.commit.function_calls 797818 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6958755 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6958753 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 571692691 # The number of ROB reads -system.cpu.rob.rob_writes 659422929 # The number of ROB writes +system.cpu.rob.rob_reads 571692690 # The number of ROB reads +system.cpu.rob.rob_writes 659422914 # The number of ROB writes system.cpu.timesIdled 5933064 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19609407 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 19609404 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated @@ -513,13 +513,13 @@ system.cpu.cpi 2.189894 # CP system.cpu.cpi_total 2.189894 # CPI: Total CPI of All Threads system.cpu.ipc 0.456643 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.456643 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 451224157 # number of integer regfile reads +system.cpu.int_regfile_reads 451224153 # number of integer regfile reads system.cpu.int_regfile_writes 233957254 # number of integer regfile writes system.cpu.fp_regfile_reads 3215586 # number of floating regfile reads system.cpu.fp_regfile_writes 2009211 # number of floating regfile writes -system.cpu.cc_regfile_reads 102809518 # number of cc regfile reads -system.cpu.cc_regfile_writes 59799385 # number of cc regfile writes -system.cpu.misc_regfile_reads 133324418 # number of misc regfile reads +system.cpu.cc_regfile_reads 102809513 # number of cc regfile reads +system.cpu.cc_regfile_writes 59799383 # number of cc regfile writes +system.cpu.misc_regfile_reads 133324417 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes system.cpu.toL2Bus.throughput 3898568 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 7250 # Transaction distribution @@ -545,49 +545,49 @@ system.cpu.toL2Bus.respLayer1.occupancy 3467413 # La system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.icache.tags.replacements 4653 # number of replacements system.cpu.icache.tags.tagsinuse 1619.938452 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22344301 # Total number of references to valid blocks. +system.cpu.icache.tags.total_refs 22344300 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 6620 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3375.272054 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 3375.271903 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 1619.938452 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.790986 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.790986 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 22344301 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22344301 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22344301 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22344301 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22344301 # number of overall hits -system.cpu.icache.overall_hits::total 22344301 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8911 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8911 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8911 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8911 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8911 # number of overall misses -system.cpu.icache.overall_misses::total 8911 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 368225749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 368225749 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 368225749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 368225749 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 368225749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 368225749 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22353212 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22353212 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22353212 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22353212 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22353212 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22353212 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_hits::cpu.inst 22344300 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22344300 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22344300 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22344300 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22344300 # number of overall hits +system.cpu.icache.overall_hits::total 22344300 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8910 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8910 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8910 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8910 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8910 # number of overall misses +system.cpu.icache.overall_misses::total 8910 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 368144999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 368144999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 368144999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 368144999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 368144999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 368144999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22353210 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22353210 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22353210 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22353210 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22353210 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22353210 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000399 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000399 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000399 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000399 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000399 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000399 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41322.606778 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 41322.606778 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 41322.606778 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 41322.606778 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 41322.606778 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 41322.606778 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41318.181706 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 41318.181706 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 41318.181706 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 41318.181706 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 41318.181706 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 41318.181706 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 877 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 20 # number of cycles access was blocked @@ -596,45 +596,45 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 43.850000 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2127 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2127 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2127 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2127 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2127 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2127 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2126 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2126 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2126 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2126 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2126 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2126 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6784 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 6784 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 6784 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 6784 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 6784 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 6784 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 271661249 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 271661249 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 271661249 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 271661249 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 271661249 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 271661249 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 271638749 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 271638749 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 271638749 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 271638749 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 271638749 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 271638749 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000303 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000303 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000303 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40044.405808 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40044.405808 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40044.405808 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 40044.405808 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40044.405808 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 40044.405808 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40041.089180 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40041.089180 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40041.089180 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 40041.089180 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40041.089180 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 40041.089180 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2543.926921 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2543.926920 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3266 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3826 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.853633 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 1.725256 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2230.334816 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2230.334814 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 311.866849 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000053 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.068064 # Average percentage of cache occupancy @@ -666,17 +666,17 @@ system.cpu.l2cache.demand_misses::total 5355 # nu system.cpu.l2cache.overall_misses::cpu.inst 3393 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1962 # number of overall misses system.cpu.l2cache.overall_misses::total 5355 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 232439500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 232417000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32755500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 265195000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 265172500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 104434000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 104434000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 232439500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 232417000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 137189500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 369629000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 232439500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 369606500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 232417000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 137189500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 369629000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 369606500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 6620 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 466 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7086 # number of ReadReq accesses(hits+misses) @@ -705,17 +705,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.620870 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.512538 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.978554 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.620870 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68505.599764 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68498.968464 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76175.581395 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69368.297149 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69362.411719 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68168.407311 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68168.407311 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68505.599764 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68498.968464 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69923.292559 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69025.023343 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68505.599764 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69020.821662 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68498.968464 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69923.292559 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69025.023343 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69020.821662 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -737,19 +737,19 @@ system.cpu.l2cache.demand_mshr_misses::total 5355 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3393 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1962 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5355 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 189922000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 189899500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27426500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 217348500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 217326000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1630163 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1630163 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 84874000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 84874000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 189922000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 189899500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 112300500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 302222500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 189922000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 302200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 189899500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 112300500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 302222500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 302200000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.512538 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.922747 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.539515 # mshr miss rate for ReadReq accesses @@ -763,37 +763,37 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.620870 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.512538 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.978554 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.620870 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55974.653699 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55968.022399 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63782.558140 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56852.864243 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56846.978812 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55400.783290 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55400.783290 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55974.653699 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55968.022399 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57237.767584 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56437.441643 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55974.653699 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56433.239963 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55968.022399 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57237.767584 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56437.441643 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56433.239963 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 57 # number of replacements system.cpu.dcache.tags.tagsinuse 1438.861304 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 66102355 # Total number of references to valid blocks. +system.cpu.dcache.tags.total_refs 66102356 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2004 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 32985.207086 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 32985.207585 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 1438.861304 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.351284 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.351284 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 45588096 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 45588096 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 45588097 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 45588097 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20514029 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 20514029 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 66102125 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 66102125 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 66102125 # number of overall hits -system.cpu.dcache.overall_hits::total 66102125 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 66102126 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 66102126 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 66102126 # number of overall hits +system.cpu.dcache.overall_hits::total 66102126 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 935 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 935 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1702 # number of WriteReq misses @@ -810,14 +810,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 176670730 system.cpu.dcache.demand_miss_latency::total 176670730 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 176670730 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 176670730 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 45589031 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 45589031 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 45589032 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 45589032 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 66104762 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 66104762 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 66104762 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 66104762 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 66104763 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 66104763 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 66104763 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 66104763 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000083 # miss rate for WriteReq accesses |