diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
| commit | 324bc9771d1f3129aee87ccb73bcf23ea4c3b60e (patch) | |
| tree | e5ca02cc181b18d2806e30b99da07d6072724988 /tests/long/se/70.twolf | |
| parent | 337774e192cb9268244d05e828b395060ba1cefb (diff) | |
| download | gem5-324bc9771d1f3129aee87ccb73bcf23ea4c3b60e.tar.xz | |
stats: Update stats to match cache changes
Diffstat (limited to 'tests/long/se/70.twolf')
5 files changed, 2109 insertions, 2078 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index 11356e644..8b18f9604 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.051911 # Nu sim_ticks 51910606500 # Number of ticks simulated final_tick 51910606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 339215 # Simulator instruction rate (inst/s) -host_op_rate 339215 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 191602600 # Simulator tick rate (ticks/s) -host_mem_usage 303192 # Number of bytes of host memory used -host_seconds 270.93 # Real time elapsed on the host +host_inst_rate 362776 # Simulator instruction rate (inst/s) +host_op_rate 362776 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 204910533 # Simulator tick rate (ticks/s) +host_mem_usage 303308 # Number of bytes of host memory used +host_seconds 253.33 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -200,12 +200,12 @@ system.physmem.bytesPerActivate::768-895 27 2.76% 85.70% # By system.physmem.bytesPerActivate::896-1023 27 2.76% 88.46% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 113 11.54% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 979 # Bytes accessed per row activation -system.physmem.totQLat 35331250 # Total ticks spent queuing -system.physmem.totMemAccLat 135062500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 35329750 # Total ticks spent queuing +system.physmem.totMemAccLat 135061000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26595000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6642.46 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6642.18 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25392.46 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25392.18 # Average memory access latency per DRAM burst system.physmem.avgRdBW 6.56 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 6.56 # Average system read bandwidth in MiByte/s @@ -227,28 +227,28 @@ system.physmem_0.preEnergy 1914000 # En system.physmem_0.readEnergy 19835400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 3390060960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1735578180 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29619604500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34770500880 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.907929 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49271576750 # Time in different power states +system.physmem_0.actBackEnergy 1735573905 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29619608250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34770500355 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.907919 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49271583750 # Time in different power states system.physmem_0.memoryStateTime::REF 1733160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 898679500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 898672500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 3848040 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 2099625 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 21216000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 3390060960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1825261695 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29540934750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34783421070 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.156857 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49142723000 # Time in different power states +system.physmem_1.actBackEnergy 1825260840 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29540935500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34783420965 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.156855 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49142724000 # Time in different power states system.physmem_1.memoryStateTime::REF 1733160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1030068000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1030067000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 11441088 # Number of BP lookups system.cpu.branchPred.condPredicted 8207826 # Number of conditional branches predicted @@ -305,12 +305,12 @@ system.cpu.ipc 0.885205 # IP system.cpu.tickCycles 102104321 # Number of cycles that the object actually ticked system.cpu.idleCycles 1716892 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1447.424804 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1447.424803 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26573200 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11916.233184 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1447.424804 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1447.424803 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.353375 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.353375 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id @@ -340,12 +340,12 @@ system.cpu.dcache.overall_misses::cpu.data 3431 # system.cpu.dcache.overall_misses::total 3431 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 40212500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 40212500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 214035000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 214035000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 254247500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 254247500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 254247500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 254247500 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 214034000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 214034000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 254246500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 254246500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 254246500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 254246500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20075528 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20075528 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -364,12 +364,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.000129 system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77183.301344 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 77183.301344 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73551.546392 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73551.546392 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 74103.031186 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 74103.031186 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 74103.031186 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 74103.031186 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73551.202749 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73551.202749 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 74102.739726 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 74102.739726 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 74102.739726 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 74102.739726 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -398,12 +398,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 2230 system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37107000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 37107000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131707500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 131707500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 168814500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 168814500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 168814500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 168814500 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131706500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 131706500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 168813500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 168813500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 168813500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 168813500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses @@ -414,20 +414,20 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76509.278351 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76509.278351 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75477.077364 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75477.077364 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75701.569507 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75701.569507 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75701.569507 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75701.569507 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75476.504298 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75476.504298 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75701.121076 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75701.121076 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75701.121076 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75701.121076 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13850 # number of replacements -system.cpu.icache.tags.tagsinuse 1640.456656 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1640.456655 # Cycle average of tags in use system.cpu.icache.tags.total_refs 22937703 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15815 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1450.376415 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1640.456656 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1640.456655 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.801004 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.801004 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id @@ -483,6 +483,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 13850 # number of writebacks +system.cpu.icache.writebacks::total 13850 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15816 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 15816 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 15816 # number of demand (read+write) MSHR misses @@ -509,13 +511,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24855.620890 system.cpu.icache.overall_avg_mshr_miss_latency::total 24855.620890 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2477.794194 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2477.794192 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 26614 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3666 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 7.259684 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 17.781001 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2100.046720 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2100.046719 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 359.966473 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064088 # Average percentage of cache occupancy @@ -530,8 +532,10 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2505 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.111877 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 261827 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 261827 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 13850 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 13850 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12647 # number of ReadCleanReq hits @@ -556,20 +560,22 @@ system.cpu.l2cache.demand_misses::total 5319 # nu system.cpu.l2cache.overall_misses::cpu.inst 3168 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2151 # number of overall misses system.cpu.l2cache.overall_misses::total 5319 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 128817000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 128817000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 236600000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 236600000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 128816000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 128816000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 236598500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 236598500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 35817000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 35817000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 236600000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 164634000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 401234000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 236600000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 164634000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 401234000 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.demand_miss_latency::cpu.inst 236598500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 164633000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 401231500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 236598500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 164633000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 401231500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 107 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 107 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 13850 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 13850 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1745 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1745 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15815 # number of ReadCleanReq accesses(hits+misses) @@ -594,18 +600,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.294763 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200316 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964574 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.294763 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74937.172775 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74937.172775 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74684.343434 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74684.343434 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74936.591041 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74936.591041 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74683.869949 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74683.869949 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82909.722222 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82909.722222 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74684.343434 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76538.354254 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75434.104155 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74684.343434 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76538.354254 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75434.104155 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74683.869949 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76537.889354 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75433.634142 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74683.869949 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76537.889354 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75433.634142 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -626,18 +632,18 @@ system.cpu.l2cache.demand_mshr_misses::total 5319 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2151 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5319 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 111627000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 111627000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 204920000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 204920000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 111626000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 111626000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 204918500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 204918500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31497000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31497000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 204920000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 143124000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 348044000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 204920000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 143124000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 348044000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 204918500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 143123000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 348041500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 204918500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 143123000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 348041500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985100 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985100 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.200316 # mshr miss rate for ReadCleanReq accesses @@ -650,18 +656,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.294763 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200316 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.294763 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64937.172775 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64937.172775 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64684.343434 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64684.343434 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64936.591041 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64936.591041 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64683.869949 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64683.869949 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72909.722222 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72909.722222 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64684.343434 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66538.354254 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65434.104155 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64684.343434 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66538.354254 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65434.104155 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64683.869949 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66537.889354 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65433.634142 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64683.869949 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66537.889354 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65433.634142 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 32052 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 14007 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -670,8 +676,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 16300 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 13900 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 13850 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1745 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1745 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 15815 # Transaction distribution @@ -679,23 +686,23 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 485 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45480 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4617 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 50097 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1012160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1898560 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1161728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2048128 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 32052 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 18045 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 32052 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 18045 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 32052 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 16133000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.snoop_fanout::total 18045 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 29983000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 23722500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3345000 # Layer occupancy (ticks) @@ -719,9 +726,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 5319 # Request fanout histogram -system.membus.reqLayer0.occupancy 6413000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6412500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 28165750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 28165250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index cc5b93144..fdd161331 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.021919 # Number of seconds simulated -sim_ticks 21919473500 # Number of ticks simulated -final_tick 21919473500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.021917 # Number of seconds simulated +sim_ticks 21916940500 # Number of ticks simulated +final_tick 21916940500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 199769 # Simulator instruction rate (inst/s) -host_op_rate 199769 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52017673 # Simulator tick rate (ticks/s) -host_mem_usage 302932 # Number of bytes of host memory used -host_seconds 421.39 # Real time elapsed on the host +host_inst_rate 209109 # Simulator instruction rate (inst/s) +host_op_rate 209109 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54443336 # Simulator tick rate (ticks/s) +host_mem_usage 303052 # Number of bytes of host memory used +host_seconds 402.56 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 195776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 195712 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 138496 # Number of bytes read from this memory -system.physmem.bytes_read::total 334272 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 195776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 195776 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3059 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 334208 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 195712 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 195712 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3058 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2164 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5223 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8931601 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6318400 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15250001 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8931601 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8931601 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8931601 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6318400 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15250001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5223 # Number of read requests accepted +system.physmem.num_reads::total 5222 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8929714 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6319130 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15248844 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8929714 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8929714 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8929714 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6319130 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15248844 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5222 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5223 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5222 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 334272 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 334208 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 334272 # Total read bytes from the system interface side +system.physmem.bytesReadSys 334208 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -50,7 +50,7 @@ system.physmem.perBankRdBursts::5 223 # Pe system.physmem.perBankRdBursts::6 218 # Per bank write bursts system.physmem.perBankRdBursts::7 288 # Per bank write bursts system.physmem.perBankRdBursts::8 239 # Per bank write bursts -system.physmem.perBankRdBursts::9 278 # Per bank write bursts +system.physmem.perBankRdBursts::9 277 # Per bank write bursts system.physmem.perBankRdBursts::10 249 # Per bank write bursts system.physmem.perBankRdBursts::11 251 # Per bank write bursts system.physmem.perBankRdBursts::12 396 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21919378500 # Total gap between requests +system.physmem.totGap 21916845500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5223 # Read request sizes (log2) +system.physmem.readPktSize::6 5222 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1189 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 507 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1190 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 509 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 237 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 860 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 387.497674 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 231.928894 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 358.454487 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 254 29.53% 29.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 187 21.74% 51.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 83 9.65% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 58 6.74% 67.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 36 4.19% 71.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 34 3.95% 75.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 40 4.65% 80.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 50 5.81% 86.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 118 13.72% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 860 # Bytes accessed per row activation -system.physmem.totQLat 44538500 # Total ticks spent queuing -system.physmem.totMemAccLat 142469750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26115000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8527.38 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 859 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 386.235157 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 231.364931 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 358.000658 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 253 29.45% 29.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 187 21.77% 51.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 82 9.55% 60.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 62 7.22% 67.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 35 4.07% 72.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 38 4.42% 76.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 35 4.07% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 43 5.01% 85.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 124 14.44% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 859 # Bytes accessed per row activation +system.physmem.totQLat 43137250 # Total ticks spent queuing +system.physmem.totMemAccLat 141049750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26110000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8260.68 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27277.38 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27010.68 # Average memory access latency per DRAM burst system.physmem.avgRdBW 15.25 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 15.25 # Average system read bandwidth in MiByte/s @@ -216,70 +216,70 @@ system.physmem.busUtilRead 0.12 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4358 # Number of row buffer hits during reads +system.physmem.readRowHits 4353 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.44 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.36 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4196702.76 # Average gap between requests -system.physmem.pageHitRate 83.44 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3160080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1724250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 19741800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 4197021.35 # Average gap between requests +system.physmem.pageHitRate 83.36 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3122280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1703625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 19461000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1431596400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 935708580 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 12330335250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14722266360 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.680556 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 20510216250 # Time in different power states -system.physmem_0.memoryStateTime::REF 731900000 # Time in different power states +system.physmem_0.refreshEnergy 1431087840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 912284145 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 12346211250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14713870140 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.536045 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 20536521000 # Time in different power states +system.physmem_0.memoryStateTime::REF 731640000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 676644750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 642620250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3341520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1823250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 20872800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3311280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1806750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 20748000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1431596400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 913464900 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 12349847250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 14720946120 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.620322 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 20542312250 # Time in different power states -system.physmem_1.memoryStateTime::REF 731900000 # Time in different power states +system.physmem_1.refreshEnergy 1431087840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 917766405 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 12341402250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14716122525 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.638843 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 20529652250 # Time in different power states +system.physmem_1.memoryStateTime::REF 731640000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 644355250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 650829750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 16112018 # Number of BP lookups -system.cpu.branchPred.condPredicted 11701868 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 926184 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8628002 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7529875 # Number of BTB hits +system.cpu.branchPred.lookups 16111441 # Number of BP lookups +system.cpu.branchPred.condPredicted 11701383 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 926235 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8627871 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7529688 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.272523 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1595504 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 407 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 87.271680 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1595490 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 408 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 24062707 # DTB read hits -system.cpu.dtb.read_misses 205786 # DTB read misses +system.cpu.dtb.read_hits 24061115 # DTB read hits +system.cpu.dtb.read_misses 205797 # DTB read misses system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 24268493 # DTB read accesses -system.cpu.dtb.write_hits 7162407 # DTB write hits -system.cpu.dtb.write_misses 1203 # DTB write misses +system.cpu.dtb.read_accesses 24266912 # DTB read accesses +system.cpu.dtb.write_hits 7162299 # DTB write hits +system.cpu.dtb.write_misses 1202 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 7163610 # DTB write accesses -system.cpu.dtb.data_hits 31225114 # DTB hits -system.cpu.dtb.data_misses 206989 # DTB misses +system.cpu.dtb.write_accesses 7163501 # DTB write accesses +system.cpu.dtb.data_hits 31223414 # DTB hits +system.cpu.dtb.data_misses 206999 # DTB misses system.cpu.dtb.data_acv 2 # DTB access violations -system.cpu.dtb.data_accesses 31432103 # DTB accesses -system.cpu.itb.fetch_hits 15925407 # ITB hits +system.cpu.dtb.data_accesses 31430413 # DTB accesses +system.cpu.itb.fetch_hits 15924997 # ITB hits system.cpu.itb.fetch_misses 77 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 15925484 # ITB accesses +system.cpu.itb.fetch_accesses 15925074 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,139 +293,139 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 43838948 # number of cpu cycles simulated +system.cpu.numCycles 43833882 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 16632320 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 137954260 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16112018 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9125379 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 25989721 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1930958 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 137 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 16631894 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 137948476 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16111441 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9125178 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 25988337 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1931044 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 165 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 2266 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 15925407 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 365179 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 43589931 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.164819 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.433135 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 15924997 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 365277 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 43588192 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.164813 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.433150 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19407451 44.52% 44.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2621129 6.01% 50.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1337584 3.07% 53.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1925835 4.42% 58.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3007413 6.90% 64.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1288266 2.96% 67.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1362128 3.12% 71.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 884292 2.03% 73.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11755833 26.97% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19406935 44.52% 44.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2620914 6.01% 50.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1337526 3.07% 53.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1925752 4.42% 58.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3007087 6.90% 64.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1288201 2.96% 67.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1362015 3.12% 71.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 884285 2.03% 73.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11755477 26.97% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43589931 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.367527 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.146842 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12848398 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8248987 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19437203 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2101434 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 953909 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2651089 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 11974 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 132128383 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 49953 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 953909 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13970899 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4649700 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10898 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20300581 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3703944 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 128750721 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 69632 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2039237 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1388591 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 55010 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 94550726 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 167277672 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 159796203 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7481468 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 43588192 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.367557 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.147074 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12849243 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8247037 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19437084 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2100878 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 953950 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2651003 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 11975 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 132120831 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 49966 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 953950 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13971462 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4650933 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10896 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20300187 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3700764 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 128743195 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 69669 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2038779 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1385854 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 54667 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 94545107 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 167268798 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 159787749 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7481048 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 26123365 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 949 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 946 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8314647 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26912240 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8709829 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3514186 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1623457 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111857121 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1283 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 99743085 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 115820 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 27678694 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 21106490 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 894 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43589931 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.288214 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.099779 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 26117746 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 950 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 948 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8310352 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26910154 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8709135 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3511293 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1618997 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111850389 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1284 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 99739394 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 116060 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 27671963 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 21101257 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 895 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43588192 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.288220 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.099837 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11253194 25.82% 25.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 7641118 17.53% 43.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7479948 17.16% 60.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5719610 13.12% 73.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4459621 10.23% 83.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2975044 6.83% 90.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2026173 4.65% 95.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1169285 2.68% 98.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 865938 1.99% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11252596 25.82% 25.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 7641941 17.53% 43.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7479961 17.16% 60.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5717065 13.12% 73.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4459781 10.23% 83.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2974994 6.83% 90.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2026656 4.65% 95.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1169278 2.68% 98.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 865920 1.99% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43589931 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43588192 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 482162 20.24% 20.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 482625 20.24% 20.24% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 20.24% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 20.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 537 0.02% 20.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 536 0.02% 20.26% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 34275 1.44% 21.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 12320 0.52% 22.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1010506 42.41% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 685066 28.75% 93.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 157661 6.62% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 34267 1.44% 21.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 12315 0.52% 22.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1010469 42.37% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 686537 28.79% 93.37% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 158059 6.63% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60678292 60.83% 60.83% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 490564 0.49% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60676588 60.84% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 490565 0.49% 61.33% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2838989 2.85% 64.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115355 0.12% 64.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2438911 2.45% 66.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 313691 0.31% 67.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 766049 0.77% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2839004 2.85% 64.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115354 0.12% 64.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2438838 2.45% 66.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 313701 0.31% 67.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 766055 0.77% 67.82% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.82% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.82% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.82% # Type of FU issued @@ -447,84 +447,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.82% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.82% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.82% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24838081 24.90% 92.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7262827 7.28% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24836317 24.90% 92.72% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7262646 7.28% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 99743085 # Type of FU issued -system.cpu.iq.rate 2.275216 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2382527 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023887 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 229948900 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 130065304 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 89786778 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15625548 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9512793 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7169302 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 93776538 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8349067 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1917366 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 99739394 # Type of FU issued +system.cpu.iq.rate 2.275395 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2384808 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023910 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 229942315 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 130052988 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 89783673 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15625533 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9511643 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7169331 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 93775141 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8349054 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1917494 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6916042 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11056 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 41363 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2208726 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6913956 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11070 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 41356 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2208032 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 42784 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1527 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 42783 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1512 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 953909 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3616734 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 464700 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 122788755 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 239982 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26912240 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8709829 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1283 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 38454 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 420547 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 41363 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 525246 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 502956 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1028202 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 98432500 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 24268972 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1310585 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 953950 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3617044 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 465078 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 122781228 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 240022 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 26910154 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8709135 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1284 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 38486 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 420890 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 41356 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 525280 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 502970 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1028250 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 98428862 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 24267391 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1310532 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10930351 # number of nop insts executed -system.cpu.iew.exec_refs 31432616 # number of memory reference insts executed -system.cpu.iew.exec_branches 12487704 # Number of branches executed -system.cpu.iew.exec_stores 7163644 # Number of stores executed -system.cpu.iew.exec_rate 2.245321 # Inst execution rate -system.cpu.iew.wb_sent 97645732 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 96956080 # cumulative count of insts written-back -system.cpu.iew.wb_producers 66985594 # num instructions producing a value -system.cpu.iew.wb_consumers 95002941 # num instructions consuming a value +system.cpu.iew.exec_nop 10929555 # number of nop insts executed +system.cpu.iew.exec_refs 31430926 # number of memory reference insts executed +system.cpu.iew.exec_branches 12487406 # Number of branches executed +system.cpu.iew.exec_stores 7163535 # Number of stores executed +system.cpu.iew.exec_rate 2.245497 # Inst execution rate +system.cpu.iew.wb_sent 97642114 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 96953004 # cumulative count of insts written-back +system.cpu.iew.wb_producers 66984387 # num instructions producing a value +system.cpu.iew.wb_consumers 95000699 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.211642 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.705090 # average fanout of values written-back +system.cpu.iew.wb_rate 2.211828 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.705094 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 30887581 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 30880053 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 914614 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 39095972 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.350704 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.921132 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 914663 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 39095166 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.350752 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.921213 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 14698430 37.60% 37.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8547015 21.86% 59.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3864183 9.88% 69.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1929221 4.93% 74.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1372371 3.51% 77.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1004316 2.57% 80.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 690404 1.77% 82.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 733733 1.88% 84.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6256299 16.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 14698751 37.60% 37.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8546224 21.86% 59.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3864207 9.88% 69.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1928510 4.93% 74.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1372257 3.51% 77.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1004424 2.57% 80.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 690640 1.77% 82.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 733325 1.88% 84.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6256828 16.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 39095972 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 39095166 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -570,118 +570,118 @@ system.cpu.commit.op_class_0::MemWrite 6501103 7.07% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction -system.cpu.commit.bw_lim_events 6256299 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 155629269 # The number of ROB reads -system.cpu.rob.rob_writes 250130763 # The number of ROB writes -system.cpu.timesIdled 4629 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 249017 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 6256828 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 155620406 # The number of ROB reads +system.cpu.rob.rob_writes 250114778 # The number of ROB writes +system.cpu.timesIdled 4635 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 245690 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.520778 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.520778 # CPI: Total CPI of All Threads -system.cpu.ipc 1.920204 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.920204 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 132982273 # number of integer regfile reads -system.cpu.int_regfile_writes 72919705 # number of integer regfile writes -system.cpu.fp_regfile_reads 6252521 # number of floating regfile reads -system.cpu.fp_regfile_writes 6155462 # number of floating regfile writes -system.cpu.misc_regfile_reads 719143 # number of misc regfile reads +system.cpu.cpi 0.520718 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.520718 # CPI: Total CPI of All Threads +system.cpu.ipc 1.920426 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.920426 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 132978272 # number of integer regfile reads +system.cpu.int_regfile_writes 72916434 # number of integer regfile writes +system.cpu.fp_regfile_reads 6252591 # number of floating regfile reads +system.cpu.fp_regfile_writes 6155476 # number of floating regfile writes +system.cpu.misc_regfile_reads 719142 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 158 # number of replacements -system.cpu.dcache.tags.tagsinuse 1457.350779 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28592916 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1457.328310 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28591208 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2244 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12741.941176 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12741.180036 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1457.350779 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.355799 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.355799 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1457.328310 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.355793 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.355793 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2086 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 542 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1389 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.509277 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 57207152 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 57207152 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22099846 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22099846 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492613 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492613 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 57203742 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 57203742 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22098137 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22098137 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492614 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492614 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 457 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 457 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28592459 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28592459 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28592459 # number of overall hits -system.cpu.dcache.overall_hits::total 28592459 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1047 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1047 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8490 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8490 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 28590751 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28590751 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28590751 # number of overall hits +system.cpu.dcache.overall_hits::total 28590751 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1051 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1051 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8489 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8489 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9537 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9537 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9537 # number of overall misses -system.cpu.dcache.overall_misses::total 9537 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 69532500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 69532500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 543709251 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 543709251 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9540 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9540 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9540 # number of overall misses +system.cpu.dcache.overall_misses::total 9540 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 72374000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 72374000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 544060252 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 544060252 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 85000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 85000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 613241751 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 613241751 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 613241751 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 613241751 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22100893 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22100893 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 616434252 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 616434252 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 616434252 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 616434252 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22099188 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22099188 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 458 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 458 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28601996 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28601996 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28601996 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28601996 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000047 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000047 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 28600291 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28600291 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28600291 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28600291 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000048 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000048 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001306 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001306 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002183 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002183 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000333 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000333 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000333 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000333 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66411.174785 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66411.174785 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64041.136749 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64041.136749 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.000334 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000334 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000334 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000334 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68862.036156 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68862.036156 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64090.028507 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64090.028507 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64301.326518 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64301.326518 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64301.326518 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64301.326518 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32746 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64615.749686 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64615.749686 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64615.749686 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64615.749686 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32998 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 127 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 389 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 378 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 84.179949 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 87.296296 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 63.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 108 # number of writebacks system.cpu.dcache.writebacks::total 108 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 540 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 540 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6754 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6754 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7294 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7294 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7294 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7294 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 544 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 544 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6753 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6753 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7297 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7297 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7297 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7297 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 507 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 507 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1736 # number of WriteReq MSHR misses @@ -692,16 +692,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2243 system.cpu.dcache.demand_mshr_misses::total 2243 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2243 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2243 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39700000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 39700000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 135151495 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 135151495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40562000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 40562000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 135653495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 135653495 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 84000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 84000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 174851495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 174851495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 174851495 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 174851495 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 176215495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 176215495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 176215495 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 176215495 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000267 # mshr miss rate for WriteReq accesses @@ -712,134 +712,138 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000078 system.cpu.dcache.demand_mshr_miss_rate::total 0.000078 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000078 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78303.747535 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78303.747535 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77852.243664 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77852.243664 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80003.944773 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80003.944773 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78141.414171 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78141.414171 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 84000 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 84000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77954.300045 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77954.300045 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77954.300045 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77954.300045 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78562.414177 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78562.414177 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78562.414177 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78562.414177 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 9477 # number of replacements -system.cpu.icache.tags.tagsinuse 1601.339074 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 15910864 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 11414 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1393.977922 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 9476 # number of replacements +system.cpu.icache.tags.tagsinuse 1601.325936 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 15910465 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 11413 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1394.065101 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1601.339074 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.781904 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.781904 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1601.325936 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.781897 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.781897 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 181 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 752 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 944 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 31862226 # Number of tag accesses -system.cpu.icache.tags.data_accesses 31862226 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 15910864 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 15910864 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 15910864 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 15910864 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 15910864 # number of overall hits -system.cpu.icache.overall_hits::total 15910864 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14542 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14542 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14542 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14542 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14542 # number of overall misses -system.cpu.icache.overall_misses::total 14542 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 447928500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 447928500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 447928500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 447928500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 447928500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 447928500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 15925406 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 15925406 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 15925406 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 15925406 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 15925406 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 15925406 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000913 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000913 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000913 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000913 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000913 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000913 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30802.399945 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 30802.399945 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 30802.399945 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 30802.399945 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 30802.399945 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 30802.399945 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 837 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 31861405 # Number of tag accesses +system.cpu.icache.tags.data_accesses 31861405 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 15910465 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 15910465 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 15910465 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 15910465 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 15910465 # 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number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 444593500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 15924996 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 15924996 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 15924996 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 15924996 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 15924996 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 15924996 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000912 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000912 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000912 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000912 # 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number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 11414 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 11414 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 11414 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 11414 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 11414 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 338490500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 338490500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 338490500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 338490500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 338490500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 338490500 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 9476 # number of writebacks +system.cpu.icache.writebacks::total 9476 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3118 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3118 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3118 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3118 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3118 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3118 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11413 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 11413 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 11413 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 11413 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 11413 # 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mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000717 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000717 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29655.729806 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29655.729806 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29655.729806 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 29655.729806 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29655.729806 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 29655.729806 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29438.315955 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29438.315955 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29438.315955 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 29438.315955 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29438.315955 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 29438.315955 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2397.609271 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 17951 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3579 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 5.015647 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2397.525400 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 17950 # 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Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2421 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.109222 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 191659 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 191659 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 108 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 108 # number of Writeback hits +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.109192 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 191642 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 191642 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 108 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 108 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 9476 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 9476 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8355 # number of ReadCleanReq hits @@ -854,66 +858,68 @@ system.cpu.l2cache.overall_hits::cpu.data 80 # n system.cpu.l2cache.overall_hits::total 8435 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 1710 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 1710 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3059 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3059 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3058 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 3058 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 454 # 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number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 233633500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 233633500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 38438500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 38438500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 233633500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 170571000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 404204500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 233633500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 170571000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 404204500 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 108 # 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number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 230850500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 171935000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 402785500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 108 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 108 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 9476 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 9476 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1736 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1736 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 11414 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 11414 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 11413 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 11413 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 508 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 508 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 11414 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 11413 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 2244 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 13658 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 11414 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 13657 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 11413 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2244 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 13658 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 13657 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985023 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.985023 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.268004 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.268004 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.267940 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.267940 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.893701 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.893701 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.268004 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.267940 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.964349 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.382413 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.268004 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.382368 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.267940 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964349 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.382413 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77270.467836 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77270.467836 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76375.776398 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76375.776398 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84666.299559 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84666.299559 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76375.776398 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78822.088725 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77389.335631 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76375.776398 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78822.088725 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77389.335631 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.382368 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77564.035088 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77564.035088 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75490.680183 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75490.680183 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86564.977974 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86564.977974 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75490.680183 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79452.402957 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77132.420529 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75490.680183 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79452.402957 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77132.420529 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -924,112 +930,113 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1710 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1710 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3059 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3059 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3058 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3058 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 454 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 454 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3059 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3058 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 2164 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5223 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3059 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5222 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3058 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2164 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5223 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 115032500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 115032500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 203043500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 203043500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 33898500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 33898500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 203043500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 148931000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 351974500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 203043500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 148931000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 351974500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 5222 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 115534500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 115534500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 200270500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 200270500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 34760500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 34760500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 200270500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 150295000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 350565500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 200270500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 150295000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 350565500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985023 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985023 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.268004 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.268004 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.267940 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.267940 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.893701 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.893701 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.268004 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.267940 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964349 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.382413 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.268004 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.382368 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.267940 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964349 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.382413 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67270.467836 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67270.467836 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66375.776398 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66375.776398 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74666.299559 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74666.299559 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66375.776398 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68822.088725 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67389.335631 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66375.776398 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68822.088725 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67389.335631 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.382368 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67564.035088 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67564.035088 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65490.680183 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65490.680183 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76564.977974 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76564.977974 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65490.680183 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69452.402957 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67132.420529 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65490.680183 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69452.402957 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67132.420529 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 23293 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9635 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 23291 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9634 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 11922 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 108 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 9527 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 11921 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 108 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 9476 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1736 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1736 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 11414 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 11413 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 508 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32305 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32302 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4646 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 36951 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730496 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 36948 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1336896 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 881024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1487424 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 23293 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 13657 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 23293 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 13657 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 23293 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 11754500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 13657 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 21229500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 17121000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 17119500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3366000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3513 # Transaction distribution +system.membus.trans_dist::ReadResp 3512 # Transaction distribution system.membus.trans_dist::ReadExReq 1710 # Transaction distribution system.membus.trans_dist::ReadExResp 1710 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3513 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10446 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10446 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334272 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 334272 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 3512 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10444 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10444 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334208 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 334208 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5223 # Request fanout histogram +system.membus.snoop_fanout::samples 5222 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5223 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5222 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5223 # Request fanout histogram -system.membus.reqLayer0.occupancy 6235500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5222 # Request fanout histogram +system.membus.reqLayer0.occupancy 6271000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 27428750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 27427000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index 13ae4452a..717d8e764 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.130773 # Nu sim_ticks 130772642500 # Number of ticks simulated final_tick 130772642500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 233615 # Simulator instruction rate (inst/s) -host_op_rate 246267 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 177290947 # Simulator tick rate (ticks/s) -host_mem_usage 321196 # Number of bytes of host memory used -host_seconds 737.62 # Real time elapsed on the host +host_inst_rate 246902 # Simulator instruction rate (inst/s) +host_op_rate 260275 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 187375043 # Simulator tick rate (ticks/s) +host_mem_usage 321308 # Number of bytes of host memory used +host_seconds 697.92 # Real time elapsed on the host sim_insts 172317810 # Number of instructions simulated sim_ops 181650743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -591,6 +591,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 2888 # number of writebacks +system.cpu.icache.writebacks::total 2888 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4685 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 4685 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 4685 # number of demand (read+write) MSHR misses @@ -638,8 +640,10 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2004 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084961 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 76658 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 76658 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 2566 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 2566 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2524 # number of ReadCleanReq hits @@ -676,8 +680,10 @@ system.cpu.l2cache.demand_miss_latency::total 294557500 system.cpu.l2cache.overall_miss_latency::cpu.inst 161329500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 133228000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 294557500 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 2566 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 2566 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1098 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1098 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4685 # number of ReadCleanReq accesses(hits+misses) @@ -788,8 +794,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 5396 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2586 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2566 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 20 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 4685 # Transaction distribution @@ -797,22 +804,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 712 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11935 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3656 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 15591 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 299776 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 464000 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 416640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 580864 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 9425 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.083820 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.277132 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 6495 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.071132 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.257064 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 8635 91.62% 91.62% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 790 8.38% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 6033 92.89% 92.89% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 462 7.11% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 9425 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4728500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 6495 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7616500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 7026998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 7a60aaca0..ce097fad9 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,66 +1,66 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.085039 # Number of seconds simulated -sim_ticks 85038866000 # Number of ticks simulated -final_tick 85038866000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.085490 # Number of seconds simulated +sim_ticks 85490431000 # Number of ticks simulated +final_tick 85490431000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 124768 # Simulator instruction rate (inst/s) -host_op_rate 131526 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61578459 # Simulator tick rate (ticks/s) -host_mem_usage 316956 # Number of bytes of host memory used -host_seconds 1380.98 # Real time elapsed on the host +host_inst_rate 129805 # Simulator instruction rate (inst/s) +host_op_rate 136836 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64404554 # Simulator tick rate (ticks/s) +host_mem_usage 317332 # Number of bytes of host memory used +host_seconds 1327.40 # Real time elapsed on the host sim_insts 172303022 # Number of instructions simulated sim_ops 181635954 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 127040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 47872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 71424 # Number of bytes read from this memory -system.physmem.bytes_read::total 246336 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 127040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 127040 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 1985 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 748 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 1116 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3849 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1493905 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 562943 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 839898 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2896746 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1493905 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1493905 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1493905 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 562943 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 839898 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2896746 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3849 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 587136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 132032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 70784 # Number of bytes read from this memory +system.physmem.bytes_read::total 789952 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 587136 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 587136 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 9174 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2063 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 1106 # Number of read requests responded to by this memory +system.physmem.num_reads::total 12343 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 6867856 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1544407 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 827976 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9240239 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6867856 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6867856 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6867856 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1544407 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 827976 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9240239 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 12344 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 3849 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 12344 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 246336 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 790016 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 246336 # Total read bytes from the system interface side +system.physmem.bytesReadSys 790016 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 309 # Per bank write bursts -system.physmem.perBankRdBursts::1 223 # Per bank write bursts -system.physmem.perBankRdBursts::2 134 # Per bank write bursts -system.physmem.perBankRdBursts::3 318 # Per bank write bursts -system.physmem.perBankRdBursts::4 300 # Per bank write bursts -system.physmem.perBankRdBursts::5 302 # Per bank write bursts -system.physmem.perBankRdBursts::6 262 # Per bank write bursts -system.physmem.perBankRdBursts::7 237 # Per bank write bursts -system.physmem.perBankRdBursts::8 252 # Per bank write bursts -system.physmem.perBankRdBursts::9 219 # Per bank write bursts -system.physmem.perBankRdBursts::10 292 # Per bank write bursts -system.physmem.perBankRdBursts::11 194 # Per bank write bursts -system.physmem.perBankRdBursts::12 191 # Per bank write bursts -system.physmem.perBankRdBursts::13 211 # Per bank write bursts -system.physmem.perBankRdBursts::14 211 # Per bank write bursts -system.physmem.perBankRdBursts::15 194 # Per bank write bursts +system.physmem.perBankRdBursts::0 1112 # Per bank write bursts +system.physmem.perBankRdBursts::1 371 # Per bank write bursts +system.physmem.perBankRdBursts::2 5091 # Per bank write bursts +system.physmem.perBankRdBursts::3 435 # Per bank write bursts +system.physmem.perBankRdBursts::4 1954 # Per bank write bursts +system.physmem.perBankRdBursts::5 426 # Per bank write bursts +system.physmem.perBankRdBursts::6 266 # Per bank write bursts +system.physmem.perBankRdBursts::7 369 # Per bank write bursts +system.physmem.perBankRdBursts::8 265 # Per bank write bursts +system.physmem.perBankRdBursts::9 221 # Per bank write bursts +system.physmem.perBankRdBursts::10 295 # Per bank write bursts +system.physmem.perBankRdBursts::11 323 # Per bank write bursts +system.physmem.perBankRdBursts::12 197 # Per bank write bursts +system.physmem.perBankRdBursts::13 249 # Per bank write bursts +system.physmem.perBankRdBursts::14 227 # Per bank write bursts +system.physmem.perBankRdBursts::15 543 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 85038722500 # Total gap between requests +system.physmem.totGap 85490422000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 3849 # Read request sizes (log2) +system.physmem.readPktSize::6 12344 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,15 +94,15 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2529 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 872 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 165 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 40 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 10928 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 977 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 83 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 37 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see @@ -190,79 +190,79 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 773 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 316.357050 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 198.451466 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 308.377497 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 239 30.92% 30.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 194 25.10% 56.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 84 10.87% 66.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 87 11.25% 78.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 29 3.75% 81.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 37 4.79% 86.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 16 2.07% 88.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 13 1.68% 90.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 74 9.57% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 773 # Bytes accessed per row activation -system.physmem.totQLat 41463141 # Total ticks spent queuing -system.physmem.totMemAccLat 113631891 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 19245000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10772.45 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 7242 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 108.822977 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 85.142878 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 132.567115 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 5271 72.78% 72.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 1523 21.03% 93.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 185 2.55% 96.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 87 1.20% 97.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 38 0.52% 98.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 26 0.36% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 17 0.23% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 18 0.25% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 77 1.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 7242 # Bytes accessed per row activation +system.physmem.totQLat 167084529 # Total ticks spent queuing +system.physmem.totMemAccLat 398534529 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 61720000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13535.69 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29522.45 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 32285.69 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 9.24 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.90 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 9.24 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.02 # Data bus utilization in percentage -system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.07 # Data bus utilization in percentage +system.physmem.busUtilRead 0.07 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.83 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 3069 # Number of row buffer hits during reads +system.physmem.readRowHits 5095 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.73 # Row buffer hit rate for reads +system.physmem.readRowHitRate 41.28 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 22093718.50 # Average gap between requests -system.physmem.pageHitRate 79.73 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2789640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1522125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 16239600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 6925666.07 # Average gap between requests +system.physmem.pageHitRate 41.28 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 48527640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 26478375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 78156000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5553983760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2338576335 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 48968955000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 56882066460 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.934025 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 81466129254 # Time in different power states -system.physmem_0.memoryStateTime::REF 2839460000 # Time in different power states +system.physmem_0.refreshEnergy 5583480240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 17009559810 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 36370632750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 59116834815 # Total energy per rank (pJ) +system.physmem_0.averagePower 691.542258 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 60400646468 # Time in different power states +system.physmem_0.memoryStateTime::REF 2854540000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 731738246 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22233687032 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3031560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1654125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 13525200 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 6199200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3382500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 17869800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5553983760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2304071955 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 48999213750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 56875480350 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.856680 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 81513506905 # Time in different power states -system.physmem_1.memoryStateTime::REF 2839460000 # Time in different power states +system.physmem_1.refreshEnergy 5583480240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3325437855 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 48374248500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 57310618095 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.413332 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 80466021414 # Time in different power states +system.physmem_1.memoryStateTime::REF 2854540000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 681039595 # Time in different power states +system.physmem_1.memoryStateTime::ACT 2165082586 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 85929659 # Number of BP lookups -system.cpu.branchPred.condPredicted 68408036 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6017804 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 40110757 # Number of BTB lookups -system.cpu.branchPred.BTBHits 39021888 # Number of BTB hits +system.cpu.branchPred.lookups 85927149 # Number of BP lookups +system.cpu.branchPred.condPredicted 68408695 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6018080 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 40104766 # Number of BTB lookups +system.cpu.branchPred.BTBHits 39018080 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.285344 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3703815 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 81895 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.290382 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3702096 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 81897 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -381,96 +381,96 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 170077733 # number of cpu cycles simulated +system.cpu.numCycles 170980863 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5627528 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 349301730 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85929659 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42725703 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 158283885 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 12049307 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1743 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 5755157 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 349305240 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85927149 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42720176 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 158448180 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 12049937 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2618 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 2380 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 78962015 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 18924 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 169940212 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.150377 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.047263 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3916 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 78960236 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 19348 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 170234862 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.146650 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.050166 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 17375065 10.22% 10.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30210489 17.78% 28.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31838895 18.74% 46.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 90515763 53.26% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 17669518 10.38% 10.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30211265 17.75% 28.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31838913 18.70% 46.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 90515166 53.17% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 169940212 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.505238 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.053777 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17579546 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 17112098 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 122676977 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6721861 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5849730 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11135516 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 190121 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 306633664 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27649172 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5849730 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37767470 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8469466 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 579515 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 108936835 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8337196 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 278676031 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13415385 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3051308 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 841767 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2187025 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 37328 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 26465 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 483141060 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1197017326 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 297598208 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3006154 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 170234862 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.502554 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.042949 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17700032 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 17289472 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 122672401 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6722857 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5850100 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11135652 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 190021 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 306632940 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27644957 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5850100 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37887834 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8551246 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 582035 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 108933106 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8430541 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 278671233 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13418761 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3051568 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 841704 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2280860 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 35921 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 27095 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 483139430 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1196998780 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 297599206 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3005965 # Number of floating rename lookups system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 190164131 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 23534 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23437 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13334158 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 34140467 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14476937 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2547302 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1809047 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 264833552 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 45866 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 214914716 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5193890 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 83243464 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 219964835 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 650 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 169940212 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.264649 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.017441 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 190162501 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 23526 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23429 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13338905 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 34139598 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14476816 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2548575 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1784456 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 264827834 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 45856 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 214914585 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5192491 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 83237736 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 219939522 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 640 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 170234862 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.262459 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.017804 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52857789 31.10% 31.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 36101949 21.24% 52.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 65794996 38.72% 91.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 13566772 7.98% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1571259 0.92% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 47259 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 188 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 53140673 31.22% 31.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 36118420 21.22% 52.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 65796647 38.65% 91.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13561298 7.97% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1570362 0.92% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 47243 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 219 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 169940212 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 170234862 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35605031 66.12% 66.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 152953 0.28% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35603971 66.12% 66.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 152944 0.28% 66.40% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 66.40% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.40% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.40% # attempts to use FU when none available @@ -489,22 +489,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.40% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 66.40% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.40% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 1062 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 1066 0.00% 66.40% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 35733 0.07% 66.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 238 0.00% 66.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 35746 0.07% 66.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 240 0.00% 66.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 1040 0.00% 66.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 34389 0.06% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 14077055 26.14% 92.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3945216 7.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 952 0.00% 66.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 34296 0.06% 66.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.54% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 14072260 26.13% 92.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3948482 7.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 167357469 77.87% 77.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 918949 0.43% 78.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 167357330 77.87% 77.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 918980 0.43% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.30% # Type of FU issued @@ -523,93 +523,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.30% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33022 0.02% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33017 0.02% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 165195 0.08% 78.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 245712 0.11% 78.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 165190 0.08% 78.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 245699 0.11% 78.51% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 460561 0.21% 78.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206706 0.10% 78.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 460522 0.21% 78.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206694 0.10% 78.85% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 32005826 14.89% 93.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13373316 6.22% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 32005177 14.89% 93.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13374016 6.22% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 214914716 # Type of FU issued -system.cpu.iq.rate 1.263626 # Inst issue rate -system.cpu.iq.fu_busy_cnt 53852922 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.250578 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 654863168 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 346117768 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 204606131 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3953288 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2011882 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1806358 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266633604 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2134034 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1600995 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 214914585 # Type of FU issued +system.cpu.iq.rate 1.256951 # Inst issue rate +system.cpu.iq.fu_busy_cnt 53850162 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.250565 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 655153476 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 346106935 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 204606292 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3953209 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2011310 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1806290 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266630626 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2134121 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1600828 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6244323 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7621 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6899 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1832303 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6243454 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7546 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6949 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1832182 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 25728 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 844 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 25935 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 794 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5849730 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5682254 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 37001 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 264895393 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 5850100 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5682962 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 61282 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 264889651 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 34140467 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14476937 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23458 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3889 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 29998 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6899 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3234969 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3247770 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6482739 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 207531016 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 30721231 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7383700 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 34139598 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14476816 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23448 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3916 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 54251 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6949 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3234598 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3248118 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6482716 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 207529725 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 30719767 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7384860 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 15975 # number of nop insts executed -system.cpu.iew.exec_refs 43860800 # number of memory reference insts executed -system.cpu.iew.exec_branches 44937472 # Number of branches executed -system.cpu.iew.exec_stores 13139569 # Number of stores executed -system.cpu.iew.exec_rate 1.220213 # Inst execution rate -system.cpu.iew.wb_sent 206747617 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 206412489 # cumulative count of insts written-back -system.cpu.iew.wb_producers 129477272 # num instructions producing a value -system.cpu.iew.wb_consumers 221702085 # num instructions consuming a value +system.cpu.iew.exec_nop 15961 # number of nop insts executed +system.cpu.iew.exec_refs 43859608 # number of memory reference insts executed +system.cpu.iew.exec_branches 44936158 # Number of branches executed +system.cpu.iew.exec_stores 13139841 # Number of stores executed +system.cpu.iew.exec_rate 1.213760 # Inst execution rate +system.cpu.iew.wb_sent 206746993 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 206412582 # cumulative count of insts written-back +system.cpu.iew.wb_producers 129474820 # num instructions producing a value +system.cpu.iew.wb_consumers 221691878 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.213636 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.584015 # average fanout of values written-back +system.cpu.iew.wb_rate 1.207226 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.584031 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 69549191 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 69543013 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5842881 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158496522 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.146084 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.646497 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5843212 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158791205 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.143957 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.645227 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 73710350 46.51% 46.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 41283484 26.05% 72.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 22554549 14.23% 86.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9626760 6.07% 92.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3551822 2.24% 95.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2145509 1.35% 96.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1280291 0.81% 97.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 989155 0.62% 97.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3354602 2.12% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 73988497 46.59% 46.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 41295308 26.01% 72.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 22556711 14.21% 86.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9630949 6.07% 92.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3552216 2.24% 95.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2148211 1.35% 96.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1284578 0.81% 97.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 986502 0.62% 97.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3348233 2.11% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158496522 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 158791205 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317410 # Number of instructions committed system.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -655,380 +655,382 @@ system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 181650342 # Class of committed instruction -system.cpu.commit.bw_lim_events 3354602 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 406336252 # The number of ROB reads -system.cpu.rob.rob_writes 513856795 # The number of ROB writes -system.cpu.timesIdled 3529 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 137521 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3348233 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 406631126 # The number of ROB reads +system.cpu.rob.rob_writes 513844376 # The number of ROB writes +system.cpu.timesIdled 8957 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 746001 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303022 # Number of Instructions Simulated system.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.987085 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.987085 # CPI: Total CPI of All Threads -system.cpu.ipc 1.013084 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.013084 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 218963852 # number of integer regfile reads -system.cpu.int_regfile_writes 114515225 # number of integer regfile writes -system.cpu.fp_regfile_reads 2904259 # number of floating regfile reads -system.cpu.fp_regfile_writes 2441612 # number of floating regfile writes -system.cpu.cc_regfile_reads 709595430 # number of cc regfile reads -system.cpu.cc_regfile_writes 229551730 # number of cc regfile writes -system.cpu.misc_regfile_reads 59313283 # number of misc regfile reads +system.cpu.cpi 0.992327 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.992327 # CPI: Total CPI of All Threads +system.cpu.ipc 1.007733 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.007733 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 218966975 # number of integer regfile reads +system.cpu.int_regfile_writes 114516229 # number of integer regfile writes +system.cpu.fp_regfile_reads 2904204 # number of floating regfile reads +system.cpu.fp_regfile_writes 2441504 # number of floating regfile writes +system.cpu.cc_regfile_reads 709589080 # number of cc regfile reads +system.cpu.cc_regfile_writes 229556340 # number of cc regfile writes +system.cpu.misc_regfile_reads 59312089 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.dcache.tags.replacements 72876 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.418230 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 41115950 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 73388 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 560.254401 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 506092500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.418230 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998864 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998864 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 72854 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.416253 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 41114439 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 73366 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 560.401807 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 507537500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.416253 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998860 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998860 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 225 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 231 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 42 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 82530918 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 82530918 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 28729730 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28729730 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12341303 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12341303 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 82527906 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 82527906 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28728233 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28728233 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12341290 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12341290 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 361 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 361 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22149 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22149 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22148 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22148 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41071033 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41071033 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41071394 # number of overall hits -system.cpu.dcache.overall_hits::total 41071394 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89456 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89456 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 22984 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 22984 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 116 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 116 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 41069523 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41069523 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41069884 # number of overall hits +system.cpu.dcache.overall_hits::total 41069884 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89457 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89457 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 22997 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22997 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 118 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 118 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 259 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 259 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 112440 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 112440 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 112556 # number of overall misses -system.cpu.dcache.overall_misses::total 112556 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 857049000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 857049000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 246637999 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 246637999 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2309500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 2309500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1103686999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1103686999 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1103686999 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1103686999 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28819186 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28819186 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 112454 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 112454 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 112572 # number of overall misses +system.cpu.dcache.overall_misses::total 112572 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1065753500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1065753500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 241354499 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 241354499 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2315500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 2315500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1307107999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1307107999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1307107999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1307107999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28817690 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28817690 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 477 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 477 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22408 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 22408 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 479 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 479 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41183473 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41183473 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41183950 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41183950 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 41181977 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41181977 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41182456 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41182456 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003104 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003104 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001859 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001859 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.243187 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.243187 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011558 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011558 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002730 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002730 # miss rate for demand accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001860 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001860 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.246347 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.246347 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011559 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011559 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002731 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002731 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002733 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002733 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9580.676534 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9580.676534 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10730.856204 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10730.856204 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8916.988417 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8916.988417 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9815.786188 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9815.786188 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9805.670058 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9805.670058 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11913.584180 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11913.584180 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10495.042788 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10495.042788 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8940.154440 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8940.154440 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 11623.490485 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 11623.490485 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 11611.306533 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 11611.306533 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 166 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 11592 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 10450 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 859 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 866 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 83 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 13.494761 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 12.066975 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 64866 # number of writebacks -system.cpu.dcache.writebacks::total 64866 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24759 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 24759 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14406 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 14406 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 72854 # number of writebacks +system.cpu.dcache.writebacks::total 72854 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24777 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 24777 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14426 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 14426 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 259 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 259 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 39165 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 39165 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 39165 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 39165 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64697 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64697 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8578 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 8578 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 113 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 113 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 73275 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 73275 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 73388 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 73388 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 560382500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 560382500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86241499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 86241499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 962000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 962000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 646623999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 646623999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 647585999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 647585999 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000694 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000694 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.236897 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.236897 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 39203 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 39203 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 39203 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 39203 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64680 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 64680 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8571 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 8571 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 115 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 115 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 73251 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 73251 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 73366 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 73366 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 654439000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 654439000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86279999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 86279999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 978000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 978000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 740718999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 740718999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 741696999 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 741696999 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002244 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002244 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000693 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000693 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.240084 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.240084 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001779 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.001779 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001782 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001782 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8661.645826 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8661.645826 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10053.800303 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10053.800303 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8513.274336 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8513.274336 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8824.619570 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 8824.619570 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8824.140173 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 8824.140173 # average overall mshr miss latency +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001781 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001781 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10118.104515 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10118.104515 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10066.503208 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10066.503208 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8504.347826 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8504.347826 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10112.066716 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 10112.066716 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10109.546643 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 10109.546643 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 54478 # number of replacements -system.cpu.icache.tags.tagsinuse 510.603674 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 78903878 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 54990 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1434.876850 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 84285313500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.603674 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997273 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997273 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 54401 # number of replacements +system.cpu.icache.tags.tagsinuse 510.602972 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78901806 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 54913 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1436.851128 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 84733597500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.602972 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997271 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997271 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 48 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 157978976 # Number of tag accesses -system.cpu.icache.tags.data_accesses 157978976 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 78903878 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78903878 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78903878 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78903878 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78903878 # number of overall hits -system.cpu.icache.overall_hits::total 78903878 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 58115 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 58115 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 58115 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 58115 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 58115 # number of overall misses -system.cpu.icache.overall_misses::total 58115 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 612004953 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 612004953 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 612004953 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 612004953 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 612004953 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 612004953 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78961993 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78961993 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78961993 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78961993 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78961993 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78961993 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000736 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000736 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000736 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000736 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000736 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000736 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10530.929244 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 10530.929244 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 10530.929244 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 10530.929244 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 10530.929244 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 10530.929244 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 59295 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 157975329 # Number of tag accesses +system.cpu.icache.tags.data_accesses 157975329 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 78901806 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 78901806 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 78901806 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 78901806 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 78901806 # number of overall hits +system.cpu.icache.overall_hits::total 78901806 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 58402 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 58402 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 58402 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 58402 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 58402 # number of overall misses +system.cpu.icache.overall_misses::total 58402 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1157058425 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1157058425 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1157058425 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1157058425 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1157058425 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1157058425 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 78960208 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 78960208 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 78960208 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 78960208 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 78960208 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 78960208 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000740 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000740 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000740 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000740 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000740 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000740 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19811.965772 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19811.965772 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19811.965772 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19811.965772 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19811.965772 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19811.965772 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 72401 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 27 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2885 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3397 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 20.552860 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 21.313218 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 13.500000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3125 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3125 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3125 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3125 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3125 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3125 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54990 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 54990 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 54990 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 54990 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 54990 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 54990 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 544384465 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 544384465 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 544384465 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 544384465 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 544384465 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 544384465 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000696 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000696 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000696 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000696 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000696 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000696 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9899.699309 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 9899.699309 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9899.699309 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 9899.699309 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9899.699309 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 9899.699309 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 54401 # number of writebacks +system.cpu.icache.writebacks::total 54401 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3488 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3488 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3488 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3488 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3488 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3488 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54914 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 54914 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 54914 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 54914 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 54914 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 54914 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1043630451 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1043630451 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1043630451 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1043630451 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1043630451 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1043630451 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000695 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000695 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000695 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000695 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000695 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000695 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19004.815730 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19004.815730 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19004.815730 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19004.815730 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19004.815730 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19004.815730 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 9181 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 9181 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 9281 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 9281 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 1371 # number of prefetches not generated due to page crossing +system.cpu.l2cache.prefetcher.pfSpanPage 1359 # number of prefetches not generated due to page crossing system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2666.904370 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 230419 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3586 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 64.255159 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2148.551192 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 159756 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3199 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 49.939356 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 701.956928 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1376.038958 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 419.067836 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 169.840648 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.042844 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.083987 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.025578 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.010366 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.162775 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 265 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3321 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 19 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 85 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 161 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 749 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 37 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2293 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.016174 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.202698 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3935898 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3935898 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 64866 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 64866 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 8409 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 8409 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 52999 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 52999 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 64221 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 64221 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 52999 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 72630 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 125629 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 52999 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 72630 # number of overall hits -system.cpu.l2cache.overall_hits::total 125629 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 239 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 239 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1991 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 1991 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 519 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 519 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1991 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 758 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2749 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1991 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 758 # number of overall misses -system.cpu.l2cache.overall_misses::total 2749 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 19008500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 19008500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 136250000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 136250000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 38006500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 38006500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 136250000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 57015000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 193265000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 136250000 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 147008000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 66908651 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 846333651 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027405 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027405 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.036097 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.036097 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.007893 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.007893 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.036097 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.010192 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.021289 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.036097 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.010192 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027315 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027315 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167079 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.167079 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.028227 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.028227 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167079 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.028119 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.087605 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167079 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.028119 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.035037 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 39957.037394 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 39957.037394 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72419.831224 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72419.831224 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62471.284635 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62471.284635 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67488.258317 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67488.258317 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62471.284635 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69050.802139 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64272.045371 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62471.284635 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69050.802139 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 39957.037394 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54730.918408 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.103555 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 32702.175464 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 32702.175464 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73817.796610 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73817.796610 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68928.283379 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68928.283379 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70928.845101 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70928.845101 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68928.283379 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71259.331071 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69356.202171 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68928.283379 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71259.331071 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 32702.175464 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63710.753613 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 255732 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 127373 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10503 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 649 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 649 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 119730 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 64866 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 51985 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 2111 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 8648 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 8648 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 54990 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 64740 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 156105 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 217502 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 373607 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3519360 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8848256 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 12367616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2111 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 257843 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.084059 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.277477 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 255535 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 127274 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10474 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 11941 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3419 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 8522 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 119639 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 64840 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 51941 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 11001 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 2383 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 8640 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 8640 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 54914 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 64726 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 155926 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 217414 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 373340 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6464768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9219072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 15683840 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 13384 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 141664 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.218517 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.539520 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 236169 91.59% 91.59% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 21674 8.41% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 119230 84.16% 84.16% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 13912 9.82% 93.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 8522 6.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 257843 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 192732000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 82511447 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 141664 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 255022500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 82377983 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 110086990 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 110053990 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3612 # Transaction distribution -system.membus.trans_dist::ReadExReq 237 # Transaction distribution -system.membus.trans_dist::ReadExResp 237 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3612 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7698 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7698 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 246336 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 246336 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 12107 # Transaction distribution +system.membus.trans_dist::ReadExReq 236 # Transaction distribution +system.membus.trans_dist::ReadExResp 236 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 12108 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 24687 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 24687 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 789952 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 789952 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3849 # Request fanout histogram +system.membus.snoop_fanout::samples 12344 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3849 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 12344 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3849 # Request fanout histogram -system.membus.reqLayer0.occupancy 5019167 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 12344 # Request fanout histogram +system.membus.reqLayer0.occupancy 15598659 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 20293808 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 66476550 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index fda8a8b37..5cd25481d 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.079190 # Number of seconds simulated -sim_ticks 79190347500 # Number of ticks simulated -final_tick 79190347500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.079230 # Number of seconds simulated +sim_ticks 79229645000 # Number of ticks simulated +final_tick 79229645000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91850 # Simulator instruction rate (inst/s) -host_op_rate 153949 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55073733 # Simulator tick rate (ticks/s) -host_mem_usage 350132 # Number of bytes of host memory used -host_seconds 1437.90 # Real time elapsed on the host +host_inst_rate 90742 # Simulator instruction rate (inst/s) +host_op_rate 152092 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54436376 # Simulator tick rate (ticks/s) +host_mem_usage 350016 # Number of bytes of host memory used +host_seconds 1455.45 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 220800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 220992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 124928 # Number of bytes read from this memory system.physmem.bytes_read::total 345920 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 220800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 220800 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3450 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1955 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 220992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 220992 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3453 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1952 # Number of read requests responded to by this memory system.physmem.num_reads::total 5405 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2788219 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1579991 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4368209 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2788219 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2788219 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2788219 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1579991 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4368209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 2789259 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1576784 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4366043 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2789259 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2789259 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2789259 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1576784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4366043 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 5405 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 5405 # Number of DRAM read bursts, including those serviced by the write queue @@ -40,23 +40,23 @@ system.physmem.bytesReadSys 345920 # To system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 296 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 299 # Per bank write bursts -system.physmem.perBankRdBursts::1 345 # Per bank write bursts -system.physmem.perBankRdBursts::2 461 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 261 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 295 # Per bank write bursts +system.physmem.perBankRdBursts::1 347 # Per bank write bursts +system.physmem.perBankRdBursts::2 460 # Per bank write bursts system.physmem.perBankRdBursts::3 350 # Per bank write bursts -system.physmem.perBankRdBursts::4 340 # Per bank write bursts -system.physmem.perBankRdBursts::5 325 # Per bank write bursts -system.physmem.perBankRdBursts::6 403 # Per bank write bursts -system.physmem.perBankRdBursts::7 384 # Per bank write bursts -system.physmem.perBankRdBursts::8 342 # Per bank write bursts +system.physmem.perBankRdBursts::4 341 # Per bank write bursts +system.physmem.perBankRdBursts::5 328 # Per bank write bursts +system.physmem.perBankRdBursts::6 402 # Per bank write bursts +system.physmem.perBankRdBursts::7 383 # Per bank write bursts +system.physmem.perBankRdBursts::8 339 # Per bank write bursts system.physmem.perBankRdBursts::9 281 # Per bank write bursts -system.physmem.perBankRdBursts::10 239 # Per bank write bursts +system.physmem.perBankRdBursts::10 240 # Per bank write bursts system.physmem.perBankRdBursts::11 284 # Per bank write bursts system.physmem.perBankRdBursts::12 217 # Per bank write bursts -system.physmem.perBankRdBursts::13 467 # Per bank write bursts -system.physmem.perBankRdBursts::14 385 # Per bank write bursts -system.physmem.perBankRdBursts::15 283 # Per bank write bursts +system.physmem.perBankRdBursts::13 468 # Per bank write bursts +system.physmem.perBankRdBursts::14 388 # Per bank write bursts +system.physmem.perBankRdBursts::15 282 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 79190259000 # Total gap between requests +system.physmem.totGap 79229612500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 898 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 899 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 178 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1097 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 314.107566 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 184.474477 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.278271 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 419 38.20% 38.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 241 21.97% 60.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 97 8.84% 69.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 63 5.74% 74.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 63 5.74% 80.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 54 4.92% 85.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 22 2.01% 87.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 17 1.55% 88.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 121 11.03% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1097 # Bytes accessed per row activation -system.physmem.totQLat 39419500 # Total ticks spent queuing -system.physmem.totMemAccLat 140763250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1099 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 313.361237 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 181.828976 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.670559 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 436 39.67% 39.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 230 20.93% 60.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 99 9.01% 69.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 58 5.28% 74.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 55 5.00% 79.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 56 5.10% 84.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 23 2.09% 87.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 18 1.64% 88.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 124 11.28% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1099 # Bytes accessed per row activation +system.physmem.totQLat 41940250 # Total ticks spent queuing +system.physmem.totMemAccLat 143284000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 27025000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7293.15 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7759.53 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26043.15 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26509.53 # Average memory access latency per DRAM burst system.physmem.avgRdBW 4.37 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.37 # Average system read bandwidth in MiByte/s @@ -214,285 +214,285 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4299 # Number of row buffer hits during reads +system.physmem.readRowHits 4297 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.54 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.50 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 14651296.76 # Average gap between requests -system.physmem.pageHitRate 79.54 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4883760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2664750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 22565400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 14658577.71 # Average gap between requests +system.physmem.pageHitRate 79.50 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4906440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2677125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 22526400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5172055200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2473079805 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 45342485250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 53017734165 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.530615 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 75427842500 # Time in different power states -system.physmem_0.memoryStateTime::REF 2644200000 # Time in different power states +system.physmem_0.refreshEnergy 5174598000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2444474070 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 45390936750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 53040118785 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.484152 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 75508317500 # Time in different power states +system.physmem_0.memoryStateTime::REF 2645500000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1114667500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1071550000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3402000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1856250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 19305000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3386880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1848000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 19312800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5172055200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2272318965 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 45518583000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 52987520415 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.149179 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 75723788000 # Time in different power states -system.physmem_1.memoryStateTime::REF 2644200000 # Time in different power states +system.physmem_1.refreshEnergy 5174598000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2297025045 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 45520269750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 53016440475 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.185395 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 75726888000 # Time in different power states +system.physmem_1.memoryStateTime::REF 2645500000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 820354000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 855243500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 20589195 # Number of BP lookups -system.cpu.branchPred.condPredicted 20589195 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1327817 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12690862 # Number of BTB lookups -system.cpu.branchPred.BTBHits 12013274 # Number of BTB hits +system.cpu.branchPred.lookups 20592907 # Number of BP lookups +system.cpu.branchPred.condPredicted 20592907 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1327799 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 12698364 # Number of BTB lookups +system.cpu.branchPred.BTBHits 12013605 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.660820 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1440361 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 16897 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.607502 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1441126 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 16761 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 158380696 # number of cpu cycles simulated +system.cpu.numCycles 158459291 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 25245702 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 227408017 # Number of instructions fetch has processed -system.cpu.fetch.Branches 20589195 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13453635 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 131309354 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3192879 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 16 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 1952 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 21042 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 25251668 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 227436303 # Number of instructions fetch has processed +system.cpu.fetch.Branches 20592907 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13454731 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 131379126 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3193881 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 2041 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 21671 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.IcacheWaitRetryStallCycles 47 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 24254364 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 267325 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 158174565 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.377629 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.324169 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 24259483 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 266288 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 158251507 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.376692 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.323734 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 95855369 60.60% 60.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4772394 3.02% 63.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3794325 2.40% 66.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4370382 2.76% 68.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4226374 2.67% 71.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4818979 3.05% 74.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4692035 2.97% 77.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3702011 2.34% 79.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 31942696 20.19% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 95931722 60.62% 60.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4757646 3.01% 63.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3806394 2.41% 66.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4363208 2.76% 68.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4227713 2.67% 71.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4814821 3.04% 74.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4714702 2.98% 77.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3700525 2.34% 79.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 31934776 20.18% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 158174565 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.129998 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.435832 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15399565 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96291119 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 23261573 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 21625869 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1596439 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 336537122 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1596439 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 23302832 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 31798352 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 30486 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 35975056 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 65471400 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 328175182 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1530 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 57810134 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7763747 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 166308 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 380366291 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 909731361 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 600445935 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4186121 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 158251507 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.129957 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.435298 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15405673 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96363491 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 23242332 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 21643071 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1596940 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 336546765 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1596940 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 23300664 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 31883477 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 30445 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35976653 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 65463328 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 328193711 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1319 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 57856617 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7708627 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 165863 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 380358715 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 909771649 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 600461611 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4182617 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 120936841 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1921 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1898 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 121141633 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 82738842 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 29779777 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 59550134 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 20391789 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 317761802 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4069 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 259358612 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 72184 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 96402487 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 196983368 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2824 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 158174565 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.639699 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.523293 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 120929265 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2085 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2059 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 121166066 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 82747977 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 29791267 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 59612118 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 20405352 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 317780620 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4165 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 259339471 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 71881 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 96421401 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 197095861 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2920 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 158251507 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.638780 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.522654 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 40029224 25.31% 25.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 47620381 30.11% 55.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 33114320 20.94% 76.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17999452 11.38% 87.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10926984 6.91% 94.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4757371 3.01% 97.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2459469 1.55% 99.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 879282 0.56% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 388082 0.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 40084558 25.33% 25.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 47634072 30.10% 55.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 33122012 20.93% 76.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18013851 11.38% 87.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10936157 6.91% 94.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4740478 3.00% 97.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2457312 1.55% 99.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 875604 0.55% 99.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 387463 0.24% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 158174565 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 158251507 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 231613 7.32% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2544922 80.40% 87.72% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 388680 12.28% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 234483 7.38% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2555698 80.47% 87.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 385880 12.15% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1213055 0.47% 0.47% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 161788642 62.38% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 789415 0.30% 63.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7038152 2.71% 65.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1187589 0.46% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 64884960 25.02% 91.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 22456799 8.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1212784 0.47% 0.47% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 161792342 62.39% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 789140 0.30% 63.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7038106 2.71% 65.87% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1186493 0.46% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 64866325 25.01% 91.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 22454281 8.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 259358612 # Type of FU issued -system.cpu.iq.rate 1.637565 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3165215 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012204 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 675270057 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 410763185 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 253622616 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4859131 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 3700913 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2341090 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 258863930 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2446842 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18717155 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 259339471 # Type of FU issued +system.cpu.iq.rate 1.636632 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3176061 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012247 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 675323210 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 410805836 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 253605894 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4855181 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 3696441 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2340510 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 258858304 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2444444 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18689568 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 26089255 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 12841 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 302099 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 9264060 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 26098390 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 12338 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 302582 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 9275550 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 50731 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 43 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 50123 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 39 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1596439 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 12482349 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 492760 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 317765871 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 91851 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 82738842 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 29779777 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1874 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 386744 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 63788 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 302099 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 551455 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 825732 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1377187 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 257295592 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 64068122 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2063020 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1596940 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 12493200 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 494306 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 317784785 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 94743 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 82747977 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 29791267 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1931 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 389039 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 63652 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 302582 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 551479 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 825731 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1377210 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 257282682 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 64058012 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2056789 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 86346654 # number of memory reference insts executed -system.cpu.iew.exec_branches 14327856 # Number of branches executed -system.cpu.iew.exec_stores 22278532 # Number of stores executed -system.cpu.iew.exec_rate 1.624539 # Inst execution rate -system.cpu.iew.wb_sent 256649039 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 255963706 # cumulative count of insts written-back -system.cpu.iew.wb_producers 204348842 # num instructions producing a value -system.cpu.iew.wb_consumers 369627181 # num instructions consuming a value +system.cpu.iew.exec_refs 86333641 # number of memory reference insts executed +system.cpu.iew.exec_branches 14326229 # Number of branches executed +system.cpu.iew.exec_stores 22275629 # Number of stores executed +system.cpu.iew.exec_rate 1.623652 # Inst execution rate +system.cpu.iew.wb_sent 256637538 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 255946404 # cumulative count of insts written-back +system.cpu.iew.wb_producers 204333247 # num instructions producing a value +system.cpu.iew.wb_consumers 369622334 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.616129 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.552851 # average fanout of values written-back +system.cpu.iew.wb_rate 1.615219 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.552816 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 96410316 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 96429188 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1329636 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 145035845 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.526267 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.955883 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1329692 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 145106129 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.525527 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.953873 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 45546155 31.40% 31.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57399506 39.58% 70.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14176238 9.77% 80.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11993202 8.27% 89.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4061532 2.80% 91.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2861406 1.97% 93.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 912773 0.63% 94.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1078264 0.74% 95.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7006769 4.83% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 45566766 31.40% 31.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57414676 39.57% 70.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14193363 9.78% 80.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12012309 8.28% 89.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4072580 2.81% 91.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2869750 1.98% 93.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 928162 0.64% 94.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1071171 0.74% 95.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6977352 4.81% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 145035845 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 145106129 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -538,339 +538,345 @@ system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction -system.cpu.commit.bw_lim_events 7006769 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 455802776 # The number of ROB reads -system.cpu.rob.rob_writes 648723400 # The number of ROB writes -system.cpu.timesIdled 2658 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 206131 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 6977352 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 455921349 # The number of ROB reads +system.cpu.rob.rob_writes 648768029 # The number of ROB writes +system.cpu.timesIdled 2647 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 207784 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.199207 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.199207 # CPI: Total CPI of All Threads -system.cpu.ipc 0.833884 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.833884 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 448507967 # number of integer regfile reads -system.cpu.int_regfile_writes 232568909 # number of integer regfile writes -system.cpu.fp_regfile_reads 3215393 # number of floating regfile reads -system.cpu.fp_regfile_writes 1999198 # number of floating regfile writes -system.cpu.cc_regfile_reads 102530516 # number of cc regfile reads -system.cpu.cc_regfile_writes 59523273 # number of cc regfile writes -system.cpu.misc_regfile_reads 132435302 # number of misc regfile reads +system.cpu.cpi 1.199802 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.199802 # CPI: Total CPI of All Threads +system.cpu.ipc 0.833471 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.833471 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 448461429 # number of integer regfile reads +system.cpu.int_regfile_writes 232562681 # number of integer regfile writes +system.cpu.fp_regfile_reads 3213153 # number of floating regfile reads +system.cpu.fp_regfile_writes 1998427 # number of floating regfile writes +system.cpu.cc_regfile_reads 102530427 # number of cc regfile reads +system.cpu.cc_regfile_writes 59507422 # number of cc regfile writes +system.cpu.misc_regfile_reads 132428508 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.dcache.tags.replacements 52 # number of replacements -system.cpu.dcache.tags.tagsinuse 1432.092422 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 65736813 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2001 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 32851.980510 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 51 # number of replacements +system.cpu.dcache.tags.tagsinuse 1429.692139 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 65755137 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1993 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 32993.044155 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1432.092422 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.349632 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.349632 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1949 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 500 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1429.692139 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.349046 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.349046 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1942 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 34 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1397 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.475830 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 131480483 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 131480483 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 45222500 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 45222500 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513893 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513893 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 65736393 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 65736393 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 65736393 # number of overall hits -system.cpu.dcache.overall_hits::total 65736393 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1010 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1010 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1838 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1838 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2848 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2848 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2848 # number of overall misses -system.cpu.dcache.overall_misses::total 2848 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 65396000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 65396000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 129164500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 129164500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 194560500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 194560500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 194560500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 194560500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 45223510 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 45223510 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1395 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.474121 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 131517093 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 131517093 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 45240855 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 45240855 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513928 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513928 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 65754783 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 65754783 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 65754783 # number of overall hits +system.cpu.dcache.overall_hits::total 65754783 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 964 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 964 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1803 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1803 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2767 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2767 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2767 # number of overall misses +system.cpu.dcache.overall_misses::total 2767 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 65032500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 65032500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 127862500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 127862500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 192895000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 192895000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 192895000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 192895000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 45241819 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 45241819 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 65739241 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 65739241 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 65739241 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 65739241 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000090 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000090 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64748.514851 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 64748.514851 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70274.483134 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70274.483134 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 68314.782303 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 68314.782303 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 68314.782303 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 68314.782303 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 697 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 65757550 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 65757550 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 65757550 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 65757550 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000088 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000088 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67461.099585 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67461.099585 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70916.528009 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70916.528009 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69712.685219 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69712.685219 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69712.685219 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69712.685219 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 656 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 70 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 87.125000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 93.714286 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 70 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 10 # number of writebacks system.cpu.dcache.writebacks::total 10 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 549 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 549 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 511 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 511 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 551 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 551 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 551 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 551 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 461 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 461 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1836 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1836 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2297 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2297 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2297 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2297 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36137000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36137000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 127182500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 127182500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 163319500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 163319500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 163319500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 163319500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 513 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 513 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 513 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 513 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 453 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 453 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1801 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1801 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2254 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2254 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2254 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2254 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36207500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36207500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 125915500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 125915500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 162123000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 162123000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 162123000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 162123000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000035 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000035 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78388.286334 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78388.286334 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69271.514161 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69271.514161 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71101.218981 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71101.218981 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71101.218981 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71101.218981 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79928.256071 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79928.256071 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69914.214325 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69914.214325 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71926.796806 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71926.796806 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71926.796806 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71926.796806 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 4970 # number of replacements -system.cpu.icache.tags.tagsinuse 1639.175035 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 24244955 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6947 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3489.989204 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 4974 # number of replacements +system.cpu.icache.tags.tagsinuse 1637.723048 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 24250086 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6949 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3489.723126 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1639.175035 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.800378 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.800378 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1977 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 870 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 793 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.965332 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 48515969 # Number of tag accesses -system.cpu.icache.tags.data_accesses 48515969 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 24244955 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 24244955 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 24244955 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 24244955 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 24244955 # number of overall hits -system.cpu.icache.overall_hits::total 24244955 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 9408 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 9408 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 9408 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 9408 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 9408 # number of overall misses -system.cpu.icache.overall_misses::total 9408 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 407324999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 407324999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 407324999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 407324999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 407324999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 407324999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 24254363 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 24254363 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 24254363 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 24254363 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 24254363 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 24254363 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000388 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000388 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000388 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000388 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000388 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000388 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43295.599384 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 43295.599384 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 43295.599384 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 43295.599384 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 43295.599384 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 43295.599384 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 788 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1637.723048 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.799669 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.799669 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1975 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 867 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 792 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.964355 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 48526174 # Number of tag accesses +system.cpu.icache.tags.data_accesses 48526174 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 24250086 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 24250086 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 24250086 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 24250086 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 24250086 # number of overall hits +system.cpu.icache.overall_hits::total 24250086 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 9396 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 9396 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 9396 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 9396 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 9396 # number of overall misses +system.cpu.icache.overall_misses::total 9396 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 410761999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 410761999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 410761999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 410761999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 410761999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 410761999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 24259482 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 24259482 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 24259482 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24259482 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24259482 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 24259482 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000387 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000387 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000387 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000387 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000387 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000387 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43716.687846 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 43716.687846 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 43716.687846 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 43716.687846 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 43716.687846 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 43716.687846 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 900 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 65.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 69.230769 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2164 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2164 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2164 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2164 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2164 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2164 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7244 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 7244 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 7244 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 7244 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 7244 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 7244 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 309481499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 309481499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 309481499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 309481499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 309481499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 309481499 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000299 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000299 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000299 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42722.459829 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42722.459829 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42722.459829 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 42722.459829 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42722.459829 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 42722.459829 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 4974 # number of writebacks +system.cpu.icache.writebacks::total 4974 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2184 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2184 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2184 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2184 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2184 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2184 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7212 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 7212 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 7212 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 7212 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 7212 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 7212 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 312005999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 312005999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 312005999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 312005999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 312005999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 312005999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000297 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000297 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000297 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000297 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000297 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000297 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43262.063089 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43262.063089 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43262.063089 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 43262.063089 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43262.063089 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 43262.063089 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2588.929088 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8413 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3873 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.172218 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2583.684571 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8457 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3872 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.184143 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1.256976 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2282.894376 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 304.777736 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000038 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069668 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.009301 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.079008 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3873 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 989 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 39 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2616 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.118195 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 118429 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 118429 # 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number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 229284000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 130470000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 359754000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 229284000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 130470000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 359754000 # number of overall MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996104 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996104 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.496904 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.496904 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.913232 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.913232 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.496904 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.977011 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.604292 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.496904 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.977011 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.604292 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21677.364865 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21677.364865 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64960.234681 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64960.234681 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65732.975949 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65732.975949 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73089.073634 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73089.073634 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65732.975949 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66710.741688 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66086.570477 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65732.975949 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66710.741688 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66086.570477 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.497050 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.497050 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.922737 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.922737 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.497050 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.979428 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.604563 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.497050 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.979428 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.604563 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21729.885057 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21729.885057 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64882.333768 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64882.333768 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66382.165605 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66382.165605 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74020.334928 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74020.334928 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66382.165605 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66839.139344 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66547.169811 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66382.165605 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66839.139344 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66547.169811 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 14563 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 5344 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 433 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 14491 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 5309 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 353 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 7704 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 4875 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 296 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 296 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7663 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 10 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4883 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 40 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 261 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 261 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1540 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1540 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 7244 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 461 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19022 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4645 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 23667 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 444416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 573120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 299 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 14563 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.061251 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.239799 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 7212 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 453 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19042 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4558 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 23600 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 757120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128192 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 885312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 263 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 9466 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.067293 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.250543 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 13671 93.87% 93.87% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 892 6.13% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 8829 93.27% 93.27% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 637 6.73% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 14563 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7291500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 9466 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12229500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 10864500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 10815000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3149999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3120998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3871 # Transaction distribution -system.membus.trans_dist::UpgradeReq 296 # Transaction distribution -system.membus.trans_dist::UpgradeResp 296 # Transaction distribution +system.membus.trans_dist::ReadResp 3870 # Transaction distribution +system.membus.trans_dist::UpgradeReq 261 # Transaction distribution +system.membus.trans_dist::UpgradeResp 261 # Transaction distribution system.membus.trans_dist::ReadExReq 1534 # Transaction distribution system.membus.trans_dist::ReadExResp 1534 # Transaction distribution system.membus.trans_dist::ReadSharedReq 3871 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11402 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11402 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11402 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 345920 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 345920 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 345920 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11331 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11331 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11331 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 345856 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 345856 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 345856 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5701 # Request fanout histogram +system.membus.snoop_fanout::samples 5666 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5701 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5666 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5701 # Request fanout histogram -system.membus.reqLayer0.occupancy 6922500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5666 # Request fanout histogram +system.membus.reqLayer0.occupancy 6923000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 29231454 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 29158989 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |