diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2013-01-07 13:05:54 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2013-01-07 13:05:54 -0500 |
| commit | 9f15510c2c0c346faf107a47486cc06d4921e7c9 (patch) | |
| tree | fab449df2fd9f1a698ce68437efec47e2d45d5f7 /tests/long/se/70.twolf | |
| parent | 009970f59b86eac6c9a35eeb175dd9e3a3079d13 (diff) | |
| download | gem5-9f15510c2c0c346faf107a47486cc06d4921e7c9.tar.xz | |
stats: update stats for previous changes.
Diffstat (limited to 'tests/long/se/70.twolf')
6 files changed, 461 insertions, 471 deletions
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini index 203e11af7..27d1e0868 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,7 +31,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -56,7 +57,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -115,6 +116,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -131,21 +133,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -434,21 +431,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -457,6 +449,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -477,21 +486,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -518,7 +522,7 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf +executable=/gem5/dist/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout index df8c6714b..1d7c1b114 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 30 2012 11:20:14 -gem5 started Oct 30 2012 20:48:26 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:17:24 +gem5 started Jan 5 2013 01:10:37 +gem5 executing on u200540 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 144145b4f..9ba7feff2 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.074245 # Nu sim_ticks 74245032000 # Number of ticks simulated final_tick 74245032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131550 # Simulator instruction rate (inst/s) -host_op_rate 144033 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56674428 # Simulator tick rate (ticks/s) -host_mem_usage 280244 # Number of bytes of host memory used -host_seconds 1310.03 # Real time elapsed on the host +host_inst_rate 44193 # Simulator instruction rate (inst/s) +host_op_rate 48386 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19039219 # Simulator tick rate (ticks/s) +host_mem_usage 236076 # Number of bytes of host memory used +host_seconds 3899.58 # Real time elapsed on the host sim_insts 172333441 # Number of instructions simulated sim_ops 188686923 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 131008 # Number of bytes read from this memory @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 74245012500 # Total gap between requests +system.physmem.totGap 74245013500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -164,14 +164,14 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 12366785 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 86366785 # Sum of mem lat for all requests +system.physmem.totQLat 12368785 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 86368785 # Sum of mem lat for all requests system.physmem.totBusLat 15172000 # Total cycles spent in databus access system.physmem.totBankLat 58828000 # Total cycles spent in bank access -system.physmem.avgQLat 3260.42 # Average queueing delay per request +system.physmem.avgQLat 3260.95 # Average queueing delay per request system.physmem.avgBankLat 15509.62 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22770.05 # Average memory access latency +system.physmem.avgMemAccLat 22770.57 # Average memory access latency system.physmem.avgRdBW 3.27 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 3.27 # Average consumed read bandwidth in MB/s @@ -184,7 +184,7 @@ system.physmem.readRowHits 3295 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 86.87 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19574218.96 # Average gap between requests +system.physmem.avgGap 19574219.22 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -239,24 +239,24 @@ system.cpu.BPredUnit.BTBHits 43068728 # Nu system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 4355687 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 88461 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 39671704 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 39671705 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 380334125 # Number of instructions fetch has processed system.cpu.fetch.Branches 94824011 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 47424415 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 80393373 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 27296286 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7321256 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.BlockedCycles 7321257 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 11 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 4918 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.IcacheWaitRetryStallCycles 51 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 36859860 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1828379 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 148388373 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 36859861 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1828380 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 148388374 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.800016 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.152801 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68164460 45.94% 45.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68164461 45.94% 45.94% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 5263921 3.55% 49.48% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 10532073 7.10% 56.58% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 10289171 6.93% 63.52% # Number of instructions fetched each cycle (Total) @@ -268,11 +268,11 @@ system.cpu.fetch.rateDist::8 24661769 16.62% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 148388373 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 148388374 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.638588 # Number of branch fetches per cycle system.cpu.fetch.rate 2.561344 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 45525708 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5988328 # Number of cycles decode is blocked +system.cpu.decode.BlockedCycles 5988329 # Number of cycles decode is blocked system.cpu.decode.RunCycles 74834240 # Number of cycles decode is running system.cpu.decode.UnblockCycles 1196373 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 20843724 # Number of cycles decode is squashing @@ -284,19 +284,19 @@ system.cpu.rename.SquashCycles 20843724 # Nu system.cpu.rename.IdleCycles 50922630 # Number of cycles rename is idle system.cpu.rename.BlockCycles 727420 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 699991 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 70572280 # Number of cycles rename is running +system.cpu.rename.RunCycles 70572281 # Number of cycles rename is running system.cpu.rename.UnblockCycles 4622328 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 371457492 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 371457493 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 340569 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 3661423 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 29 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 631852668 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1582346867 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1565037376 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 631852669 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1582346871 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1565037380 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17309491 # Number of floating rename lookups system.cpu.rename.CommittedMaps 298092811 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 333759857 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 333759858 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 32532 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 32528 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 13064863 # count of insts added to the skid buffer @@ -311,11 +311,11 @@ system.cpu.iq.iqSquashedInstsIssued 795533 # Nu system.cpu.iq.iqSquashedInstsExamined 139603170 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 362284552 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 3343 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 148388373 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 148388374 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 1.681611 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.761108 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56153945 37.84% 37.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56153946 37.84% 37.84% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 22688522 15.29% 53.13% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 24821947 16.73% 69.86% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 20330759 13.70% 83.56% # Number of insts issued each cycle @@ -327,7 +327,7 @@ system.cpu.iq.issued_per_cycle::8 180612 0.12% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 148388373 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 148388374 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 962652 38.43% 38.43% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 5596 0.22% 38.65% # attempts to use FU when none available @@ -400,7 +400,7 @@ system.cpu.iq.FU_type_0::total 249531465 # Ty system.cpu.iq.rate 1.680459 # Inst issue rate system.cpu.iq.fu_busy_cnt 2504922 # FU busy when requested system.cpu.iq.fu_busy_rate 0.010039 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 647013011 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 647013012 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 466795184 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 237947786 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 3738747 # Number of floating instruction queue reads @@ -423,7 +423,7 @@ system.cpu.iew.iewSquashCycles 20843724 # Nu system.cpu.iew.iewBlockCycles 17321 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 891 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 329380427 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 786985 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispSquashedInsts 786986 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 43027461 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 16443523 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 32104 # Number of dispatched non-speculative instructions @@ -485,7 +485,7 @@ system.cpu.commit.bw_limited 0 # nu system.cpu.rob.rob_reads 449048801 # The number of ROB reads system.cpu.rob.rob_writes 679713725 # The number of ROB writes system.cpu.timesIdled 2572 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 101692 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 101691 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172333441 # Number of Instructions Simulated system.cpu.committedOps 188686923 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 172333441 # Number of Instructions Simulated @@ -500,12 +500,12 @@ system.cpu.fp_regfile_writes 2497505 # nu system.cpu.misc_regfile_reads 54528814 # number of misc regfile reads system.cpu.misc_regfile_writes 832204 # number of misc regfile writes system.cpu.icache.replacements 2508 # number of replacements -system.cpu.icache.tagsinuse 1347.136586 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1347.136600 # Cycle average of tags in use system.cpu.icache.total_refs 36854521 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 4234 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 8704.421587 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1347.136586 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1347.136600 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.657782 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.657782 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 36854521 # number of ReadReq hits @@ -514,36 +514,36 @@ system.cpu.icache.demand_hits::cpu.inst 36854521 # nu system.cpu.icache.demand_hits::total 36854521 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 36854521 # number of overall hits system.cpu.icache.overall_hits::total 36854521 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5339 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5339 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5339 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5339 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5339 # number of overall misses -system.cpu.icache.overall_misses::total 5339 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 158626499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 158626499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 158626499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 158626499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 158626499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 158626499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 36859860 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 36859860 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 36859860 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 36859860 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 36859860 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 36859860 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_misses::cpu.inst 5340 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5340 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5340 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5340 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5340 # number of overall misses +system.cpu.icache.overall_misses::total 5340 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 158697499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 158697499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 158697499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 158697499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 158697499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 158697499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 36859861 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 36859861 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 36859861 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 36859861 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 36859861 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 36859861 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000145 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000145 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000145 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000145 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000145 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000145 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29710.900730 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 29710.900730 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 29710.900730 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 29710.900730 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 29710.900730 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 29710.900730 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29718.632772 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 29718.632772 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 29718.632772 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 29718.632772 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 29718.632772 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 29718.632772 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 604 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked @@ -552,12 +552,12 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 35.529412 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1102 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1102 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1102 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1102 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1102 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1102 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1103 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1103 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1103 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1103 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1103 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1103 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4237 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 4237 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 4237 # number of demand (read+write) MSHR misses @@ -583,141 +583,15 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 28969.199670 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28969.199670 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 28969.199670 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 57 # number of replacements -system.cpu.dcache.tagsinuse 1406.445400 # Cycle average of tags in use -system.cpu.dcache.total_refs 46805125 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1854 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 25245.482740 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1406.445400 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.343370 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.343370 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 34390274 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 34390274 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12356568 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12356568 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 29790 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 29790 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 28491 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 28491 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 46746842 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 46746842 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 46746842 # number of overall hits -system.cpu.dcache.overall_hits::total 46746842 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1833 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1833 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 7719 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 7719 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9552 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9552 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9552 # number of overall misses -system.cpu.dcache.overall_misses::total 9552 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 82596000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 82596000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 292720496 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 292720496 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 102000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 102000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 375316496 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 375316496 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 375316496 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 375316496 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 34392107 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 34392107 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29792 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 29792 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 28491 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 28491 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46756394 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46756394 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46756394 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46756394 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000624 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000624 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000067 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000067 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000204 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000204 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000204 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000204 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45060.556465 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 45060.556465 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37922.074880 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37922.074880 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39291.927973 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39291.927973 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39291.927973 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39291.927973 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 476 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 40 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 18 # number of writebacks -system.cpu.dcache.writebacks::total 18 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1062 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1062 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7696 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7696 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7696 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7696 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 771 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 771 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1085 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1085 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1856 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1856 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1856 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1856 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36781000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36781000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 47410498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 47410498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 84191498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 84191498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 84191498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 84191498 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47705.577173 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47705.577173 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43696.311521 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43696.311521 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45361.798491 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 45361.798491 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45361.798491 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 45361.798491 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 1961.084973 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 1961.084990 # Cycle average of tags in use system.cpu.l2cache.total_refs 2275 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 2727 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.834250 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 4.022996 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1424.044648 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 533.017329 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1424.044661 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 533.017333 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000123 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.043458 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.016266 # Average percentage of cache occupancy @@ -749,16 +623,16 @@ system.cpu.l2cache.overall_misses::cpu.inst 2051 # system.cpu.l2cache.overall_misses::cpu.data 1756 # number of overall misses system.cpu.l2cache.overall_misses::total 3807 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 96653500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35087500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 131741000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35089000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 131742500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46197000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 46197000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 96653500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 81284500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 177938000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 81286000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 177939500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 96653500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 81284500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 177938000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 81286000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 177939500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 4235 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 771 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 5006 # number of ReadReq accesses(hits+misses) @@ -788,16 +662,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.484298 system.cpu.l2cache.overall_miss_rate::cpu.data 0.947141 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.625226 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47125.060946 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 51523.494860 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 48221.449488 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 51525.697504 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 48221.998536 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42973.953488 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42973.953488 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47125.060946 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46289.578588 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 46739.690045 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46290.432802 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 46740.084056 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47125.060946 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46289.578588 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 46739.690045 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46290.432802 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 46740.084056 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -828,19 +702,19 @@ system.cpu.l2cache.demand_mshr_misses::total 3793 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2048 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1745 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3793 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70387399 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 26266459 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 96653858 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70388399 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 26267459 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 96655858 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32716158 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32716158 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70387399 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 58982617 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 129370016 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70387399 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 58982617 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 129370016 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70388399 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 58983617 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 129372016 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70388399 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 58983617 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 129372016 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.483589 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869001 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.542948 # mshr miss rate for ReadReq accesses @@ -854,19 +728,145 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.622927 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.483589 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.941208 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.622927 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34368.847168 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39203.670149 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35560.654157 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34369.335449 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39205.162687 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35561.389993 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 30433.635349 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 30433.635349 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34368.847168 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33800.926648 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34107.570788 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34368.847168 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33800.926648 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34107.570788 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34369.335449 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33801.499713 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34108.098075 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34369.335449 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33801.499713 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34108.098075 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 57 # number of replacements +system.cpu.dcache.tagsinuse 1406.445410 # Cycle average of tags in use +system.cpu.dcache.total_refs 46805125 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1854 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 25245.482740 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 1406.445410 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.343370 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.343370 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 34390274 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 34390274 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12356568 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12356568 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 29790 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 29790 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 28491 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 28491 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 46746842 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 46746842 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 46746842 # number of overall hits +system.cpu.dcache.overall_hits::total 46746842 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1833 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1833 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 7719 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 7719 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 9552 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9552 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9552 # number of overall misses +system.cpu.dcache.overall_misses::total 9552 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 82599500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 82599500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 292720496 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 292720496 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 102000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 102000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 375319996 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 375319996 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 375319996 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 375319996 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 34392107 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 34392107 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29792 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 29792 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 28491 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 28491 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46756394 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46756394 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46756394 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46756394 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000053 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000624 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000624 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000067 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000067 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000204 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000204 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000204 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000204 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45062.465903 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 45062.465903 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37922.074880 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37922.074880 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39292.294389 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39292.294389 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39292.294389 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39292.294389 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 476 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 40 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 18 # number of writebacks +system.cpu.dcache.writebacks::total 18 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1062 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1062 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7696 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7696 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7696 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7696 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 771 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 771 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1085 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1085 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1856 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1856 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1856 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1856 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36782500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36782500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 47410498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 47410498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 84192998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 84192998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 84192998 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 84192998 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47707.522698 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47707.522698 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43696.311521 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43696.311521 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45362.606681 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 45362.606681 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45362.606681 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 45362.606681 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini index 7edece479..0c6ed2a4b 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,7 +31,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -56,7 +57,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -115,6 +116,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -131,21 +133,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -433,21 +430,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -464,6 +456,9 @@ int_master=system.membus.slave[2] int_slave=system.membus.master[2] pio=system.membus.master[1] +[system.cpu.isa] +type=X86ISA + [system.cpu.itb] type=X86TLB children=walker @@ -483,21 +478,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -524,7 +514,7 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf +executable=/gem5/dist/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout index 248fa6c54..e62279342 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout @@ -1,14 +1,10 @@ -Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 30 2012 00:35:18 -gem5 started Dec 30 2012 00:48:42 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Jan 4 2013 21:20:54 +gem5 started Jan 4 2013 23:04:52 +gem5 executing on u200540 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 5da80c53d..92132dbec 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.082648 # Nu sim_ticks 82648140000 # Number of ticks simulated final_tick 82648140000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 58118 # Simulator instruction rate (inst/s) -host_op_rate 97410 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36369167 # Simulator tick rate (ticks/s) -host_mem_usage 286740 # Number of bytes of host memory used -host_seconds 2272.48 # Real time elapsed on the host +host_inst_rate 31465 # Simulator instruction rate (inst/s) +host_op_rate 52738 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19690094 # Simulator tick rate (ticks/s) +host_mem_usage 268216 # Number of bytes of host memory used +host_seconds 4197.45 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221362961 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 217728 # Number of bytes read from this memory @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 82648108000 # Total gap between requests +system.physmem.totGap 82648109000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -164,14 +164,14 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 16873322 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 122447322 # Sum of mem lat for all requests +system.physmem.totQLat 16873822 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 122447822 # Sum of mem lat for all requests system.physmem.totBusLat 21392000 # Total cycles spent in databus access system.physmem.totBankLat 84182000 # Total cycles spent in bank access -system.physmem.avgQLat 3155.07 # Average queueing delay per request +system.physmem.avgQLat 3155.16 # Average queueing delay per request system.physmem.avgBankLat 15740.84 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22895.91 # Average memory access latency +system.physmem.avgMemAccLat 22896.00 # Average memory access latency system.physmem.avgRdBW 4.14 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 4.14 # Average consumed read bandwidth in MB/s @@ -184,7 +184,7 @@ system.physmem.readRowHits 4742 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 88.67 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 15454021.69 # Average gap between requests +system.physmem.avgGap 15454021.88 # Average gap between requests system.cpu.workload.num_syscalls 400 # Number of system calls system.cpu.numCycles 165296281 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -197,18 +197,18 @@ system.cpu.BPredUnit.BTBHits 13098591 # Nu system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 25830999 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 25831000 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 218891152 # Number of instructions fetch has processed system.cpu.fetch.Branches 19953215 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 13098591 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 57573712 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 17632764 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 66415443 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 241 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.MiscStallCycles 240 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 1579 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 24446052 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 431778 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.CacheLines 24446053 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 431779 # Number of outstanding Icache misses that were squashed system.cpu.fetch.rateDist::samples 165175969 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.190116 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.327383 # Number of instructions fetched each cycle (Total) @@ -454,12 +454,12 @@ system.cpu.fp_regfile_writes 2230055 # nu system.cpu.misc_regfile_reads 137014018 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes system.cpu.icache.replacements 4732 # number of replacements -system.cpu.icache.tagsinuse 1624.168421 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1624.168426 # Cycle average of tags in use system.cpu.icache.total_refs 24437101 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 6701 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 3646.784211 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1624.168421 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1624.168426 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.793051 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.793051 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 24437101 # number of ReadReq hits @@ -468,36 +468,36 @@ system.cpu.icache.demand_hits::cpu.inst 24437101 # nu system.cpu.icache.demand_hits::total 24437101 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 24437101 # number of overall hits system.cpu.icache.overall_hits::total 24437101 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8951 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8951 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8951 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8951 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8951 # number of overall misses -system.cpu.icache.overall_misses::total 8951 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 259393998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 259393998 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 259393998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 259393998 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 259393998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 259393998 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 24446052 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 24446052 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 24446052 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 24446052 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 24446052 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 24446052 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_misses::cpu.inst 8952 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8952 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8952 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8952 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8952 # number of overall misses +system.cpu.icache.overall_misses::total 8952 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 259465998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 259465998 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 259465998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 259465998 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 259465998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 259465998 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 24446053 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 24446053 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 24446053 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24446053 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24446053 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 24446053 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000366 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000366 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000366 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000366 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000366 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000366 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28979.331695 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28979.331695 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28979.331695 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28979.331695 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28979.331695 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28979.331695 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28984.137399 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28984.137399 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28984.137399 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28984.137399 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28984.137399 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28984.137399 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 676 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 21 # number of cycles access was blocked @@ -506,154 +506,46 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 32.190476 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2096 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2096 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2096 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2096 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2096 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2096 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2097 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2097 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2097 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2097 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2097 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2097 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6855 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 6855 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 6855 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 6855 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 6855 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 6855 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 198301998 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 198301998 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 198301998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 198301998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 198301998 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 198301998 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 198302998 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 198302998 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 198302998 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 198302998 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 198302998 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 198302998 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000280 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000280 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000280 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000280 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000280 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000280 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28928.081400 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28928.081400 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28928.081400 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 28928.081400 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28928.081400 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 28928.081400 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28928.227279 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28928.227279 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28928.227279 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 28928.227279 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28928.227279 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 28928.227279 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 55 # number of replacements -system.cpu.dcache.tagsinuse 1411.367255 # Cycle average of tags in use -system.cpu.dcache.total_refs 67560996 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1981 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34104.490661 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1411.367255 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.344572 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.344572 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 47046789 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 47046789 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20514009 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20514009 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 67560798 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 67560798 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 67560798 # number of overall hits -system.cpu.dcache.overall_hits::total 67560798 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 791 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 791 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1722 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1722 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2513 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2513 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2513 # number of overall misses -system.cpu.dcache.overall_misses::total 2513 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 37144500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 37144500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 76853000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 76853000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 113997500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 113997500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 113997500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 113997500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 47047580 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 47047580 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 67563311 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 67563311 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 67563311 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 67563311 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000084 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000084 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000037 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000037 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000037 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000037 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46958.912769 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 46958.912769 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44630.081301 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44630.081301 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45363.111819 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45363.111819 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45363.111819 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45363.111819 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 86 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 43 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 14 # number of writebacks -system.cpu.dcache.writebacks::total 14 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 374 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 374 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 376 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 376 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 376 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 376 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 417 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 417 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1720 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1720 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2137 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2137 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2137 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2137 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22474500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 22474500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73299500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 73299500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 95774000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 95774000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 95774000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 95774000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000084 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53895.683453 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53895.683453 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42615.988372 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42615.988372 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44817.033224 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44817.033224 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44817.033224 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44817.033224 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2509.913634 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2509.913640 # Cycle average of tags in use system.cpu.l2cache.total_refs 3332 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3792 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.878692 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 0.902701 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2234.774408 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 274.236525 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2234.774413 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 274.236526 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000028 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.068200 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.008369 # Average percentage of cache occupancy @@ -684,17 +576,17 @@ system.cpu.l2cache.demand_misses::total 5348 # nu system.cpu.l2cache.overall_misses::cpu.inst 3402 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1946 # number of overall misses system.cpu.l2cache.overall_misses::total 5348 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 158303000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21677500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 179980500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 158304000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21677000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 179981000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 68234000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 68234000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 158303000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 89911500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 248214500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 158303000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 89911500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 248214500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 158304000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 89911000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 248215000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 158304000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 89911000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 248215000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 6701 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 416 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7117 # number of ReadReq accesses(hits+misses) @@ -723,17 +615,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.615845 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.507685 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.981341 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.615845 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 46532.333921 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56159.326425 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 47513.331573 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 46532.627866 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56158.031088 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 47513.463569 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43739.743590 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43739.743590 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 46532.333921 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46203.237410 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 46412.584144 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 46532.333921 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46203.237410 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 46412.584144 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 46532.627866 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46202.980473 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 46412.677636 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 46532.627866 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46202.980473 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 46412.677636 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -755,18 +647,18 @@ system.cpu.l2cache.demand_mshr_misses::total 5348 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3402 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1946 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5348 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115394483 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16844598 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115394983 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16844098 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 132239081 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1540154 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1540154 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48432493 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48432493 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115394483 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 65277091 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115394983 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 65276591 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 180671574 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115394483 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 65277091 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115394983 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 65276591 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 180671574 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.507685 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.927885 # mshr miss rate for ReadReq accesses @@ -781,19 +673,127 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.615845 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.507685 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.981341 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.615845 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33919.601117 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43638.854922 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33919.748089 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43637.559585 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34910.000264 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31046.469872 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31046.469872 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33919.601117 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33544.239979 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33919.748089 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33543.983042 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33783.016829 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33919.601117 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33544.239979 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33919.748089 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33543.983042 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33783.016829 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 55 # number of replacements +system.cpu.dcache.tagsinuse 1411.367257 # Cycle average of tags in use +system.cpu.dcache.total_refs 67560996 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1981 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34104.490661 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 1411.367257 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.344572 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.344572 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 47046789 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 47046789 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20514009 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20514009 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 67560798 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 67560798 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 67560798 # number of overall hits +system.cpu.dcache.overall_hits::total 67560798 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 791 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 791 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1722 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1722 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2513 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2513 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2513 # number of overall misses +system.cpu.dcache.overall_misses::total 2513 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 37144000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 37144000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 76853000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 76853000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 113997000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 113997000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 113997000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 113997000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 47047580 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 47047580 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 67563311 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 67563311 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 67563311 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 67563311 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000084 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000084 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000037 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000037 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000037 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000037 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46958.280657 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 46958.280657 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44630.081301 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44630.081301 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45362.912853 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45362.912853 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45362.912853 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45362.912853 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 86 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 43 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 14 # number of writebacks +system.cpu.dcache.writebacks::total 14 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 374 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 374 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 376 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 376 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 376 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 376 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 417 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 417 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1720 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1720 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2137 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2137 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2137 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2137 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22474000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 22474000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73299500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 73299500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 95773500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 95773500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 95773500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 95773500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000084 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53894.484412 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53894.484412 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42615.988372 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42615.988372 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44816.799251 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 44816.799251 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44816.799251 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44816.799251 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |