diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-11-01 11:56:34 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-11-01 11:56:34 -0400 |
| commit | ccfdc533b9d679f1596d43d647a093885d5e74ab (patch) | |
| tree | 4c785a5e7a7e2d7244fbdbb0a316405898f99e75 /tests/long/se/70.twolf | |
| parent | 460cc77d6db46eef34b14a458816084bf6097b32 (diff) | |
| download | gem5-ccfdc533b9d679f1596d43d647a093885d5e74ab.tar.xz | |
stats: Bump stats to match DRAM controller changes
This patch encompasses all the stats updates needed to reflect the
changes to the DRAM controller.
Diffstat (limited to 'tests/long/se/70.twolf')
4 files changed, 2467 insertions, 2513 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 5350fe782..d049654a9 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.041672 # Number of seconds simulated -sim_ticks 41671895000 # Number of ticks simulated -final_tick 41671895000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.041680 # Number of seconds simulated +sim_ticks 41680207000 # Number of ticks simulated +final_tick 41680207000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 101828 # Simulator instruction rate (inst/s) -host_op_rate 101828 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46172411 # Simulator tick rate (ticks/s) -host_mem_usage 228672 # Number of bytes of host memory used -host_seconds 902.53 # Real time elapsed on the host +host_inst_rate 118687 # Simulator instruction rate (inst/s) +host_op_rate 118687 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53827332 # Simulator tick rate (ticks/s) +host_mem_usage 260144 # Number of bytes of host memory used +host_seconds 774.33 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory @@ -19,78 +19,80 @@ system.physmem.bytes_inst_read::total 178816 # Nu system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 4291046 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3292771 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7583816 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4291046 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4291046 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4291046 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3292771 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7583816 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 4938 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 4938 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 316032 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 316032 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 443 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 270 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 295 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 499 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 209 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 212 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 207 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 265 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 219 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 249 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 238 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 236 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 379 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 325 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 469 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 423 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 41671821000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 4938 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 3328 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1155 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 428 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.bw_read::cpu.inst 4290190 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3292114 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7582304 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4290190 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4290190 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4290190 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3292114 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7582304 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 4938 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 4938 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 316032 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 316032 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 443 # Per bank write bursts +system.physmem.perBankRdBursts::1 270 # Per bank write bursts +system.physmem.perBankRdBursts::2 295 # Per bank write bursts +system.physmem.perBankRdBursts::3 499 # Per bank write bursts +system.physmem.perBankRdBursts::4 209 # Per bank write bursts +system.physmem.perBankRdBursts::5 212 # Per bank write bursts +system.physmem.perBankRdBursts::6 207 # Per bank write bursts +system.physmem.perBankRdBursts::7 265 # Per bank write bursts +system.physmem.perBankRdBursts::8 219 # Per bank write bursts +system.physmem.perBankRdBursts::9 249 # Per bank write bursts +system.physmem.perBankRdBursts::10 238 # Per bank write bursts +system.physmem.perBankRdBursts::11 236 # Per bank write bursts +system.physmem.perBankRdBursts::12 379 # Per bank write bursts +system.physmem.perBankRdBursts::13 325 # Per bank write bursts +system.physmem.perBankRdBursts::14 469 # Per bank write bursts +system.physmem.perBankRdBursts::15 423 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 41680133000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 4938 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 3403 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1090 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 402 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -150,92 +152,83 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 360 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 858.311111 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 328.631203 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1420.533351 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 87 24.17% 24.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 46 12.78% 36.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 36 10.00% 46.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 14 3.89% 50.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 20 5.56% 56.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 14 3.89% 60.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 9 2.50% 62.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 7 1.94% 64.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 8 2.22% 66.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 3 0.83% 67.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 8 2.22% 70.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 5 1.39% 71.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 6 1.67% 73.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 7 1.94% 75.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 4 1.11% 76.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 2 0.56% 76.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 5 1.39% 78.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 1 0.28% 78.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 3 0.83% 79.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 5 1.39% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 1 0.28% 80.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 3 0.83% 81.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 4 1.11% 82.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 2 0.56% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 3 0.83% 84.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 3 0.83% 85.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 2 0.56% 85.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 4 1.11% 86.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 1 0.28% 86.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 4 1.11% 88.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 2 0.56% 88.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 3 0.83% 89.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.28% 89.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.28% 90.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 3 0.83% 90.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 2 0.56% 91.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 1 0.28% 91.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 2 0.56% 92.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.28% 92.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 2 0.56% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 1 0.28% 93.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.28% 93.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 1 0.28% 93.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 2 0.56% 94.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 1 0.28% 94.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 1 0.28% 95.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.28% 95.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 1 0.28% 95.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 1 0.28% 95.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 2 0.56% 96.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 1 0.28% 96.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 1 0.28% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 1 0.28% 97.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 1 0.28% 97.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.28% 97.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 1 0.28% 98.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 1 0.28% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 2 0.56% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 4 1.11% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 360 # Bytes accessed per row activation -system.physmem.totQLat 20561250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 109587500 # Sum of mem lat for all requests -system.physmem.totBusLat 24690000 # Total cycles spent in databus access -system.physmem.totBankLat 64336250 # Total cycles spent in bank access -system.physmem.avgQLat 4163.88 # Average queueing delay per request -system.physmem.avgBankLat 13028.81 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22192.69 # Average memory access latency -system.physmem.avgRdBW 7.58 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 7.58 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bytesPerActivate::samples 743 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 421.641992 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 209.527903 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 761.351186 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 254 34.19% 34.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 96 12.92% 47.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 62 8.34% 55.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 50 6.73% 62.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 29 3.90% 66.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 32 4.31% 70.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 22 2.96% 73.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 25 3.36% 76.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 15 2.02% 78.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 12 1.62% 80.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 14 1.88% 82.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 16 2.15% 84.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 32 4.31% 88.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 17 2.29% 90.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 5 0.67% 91.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 5 0.67% 92.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 8 1.08% 93.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 5 0.67% 94.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 6 0.81% 94.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 6 0.81% 95.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 2 0.27% 95.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 1 0.13% 96.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 1 0.13% 96.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 3 0.40% 96.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 2 0.27% 96.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 1 0.13% 97.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 2 0.27% 97.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 2 0.27% 97.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 1 0.13% 97.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 1 0.13% 97.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 1 0.13% 97.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 1 0.13% 98.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 1 0.13% 98.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 1 0.13% 98.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 1 0.13% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 1 0.13% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.13% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 1 0.13% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 1 0.13% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 1 0.13% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 1 0.13% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 1 0.13% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 1 0.13% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 1 0.13% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 1 0.13% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 1 0.13% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 743 # Bytes accessed per row activation +system.physmem.totQLat 34068750 # Total ticks spent queuing +system.physmem.totMemAccLat 126422500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 24690000 # Total ticks spent in databus transfers +system.physmem.totBankLat 67663750 # Total ticks spent accessing banks +system.physmem.avgQLat 6899.30 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13702.66 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 25601.96 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 7.58 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 7.58 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4578 # Number of row buffer hits during reads +system.physmem.busUtilRead 0.06 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 4195 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 92.71 # Row buffer hit rate for reads +system.physmem.readRowHitRate 84.95 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 8439007.90 # Average gap between requests -system.membus.throughput 7583816 # Throughput (bytes/s) +system.physmem.avgGap 8440691.17 # Average gap between requests +system.physmem.pageHitRate 84.95 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.90 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 7582304 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 3216 # Transaction distribution system.membus.trans_dist::ReadResp 3216 # Transaction distribution system.membus.trans_dist::ReadExReq 1722 # Transaction distribution @@ -246,9 +239,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 316032 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 316032 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 5784500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 5776500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 46068500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 45976500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu.branchPred.lookups 13412627 # Number of BP lookups system.cpu.branchPred.condPredicted 9650146 # Number of conditional branches predicted @@ -263,22 +256,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 19996270 # DTB read hits +system.cpu.dtb.read_hits 19996265 # DTB read hits system.cpu.dtb.read_misses 10 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 19996280 # DTB read accesses -system.cpu.dtb.write_hits 6501863 # DTB write hits +system.cpu.dtb.read_accesses 19996275 # DTB read accesses +system.cpu.dtb.write_hits 6501862 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6501886 # DTB write accesses -system.cpu.dtb.data_hits 26498133 # DTB hits +system.cpu.dtb.write_accesses 6501885 # DTB write accesses +system.cpu.dtb.data_hits 26498127 # DTB hits system.cpu.dtb.data_misses 33 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 26498166 # DTB accesses -system.cpu.itb.fetch_hits 9956949 # ITB hits +system.cpu.dtb.data_accesses 26498160 # DTB accesses +system.cpu.itb.fetch_hits 9956950 # ITB hits system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 9956998 # ITB accesses +system.cpu.itb.fetch_accesses 9956999 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -292,17 +285,17 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 83343791 # number of cpu cycles simulated +system.cpu.numCycles 83360415 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 5905662 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 7506965 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 73570550 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileReads 73570552 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 136146022 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 2206131 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 136146024 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 2206128 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 8058019 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.floatRegFileAccesses 8058016 # Total Accesses (Read+Write) to the FP Register File system.cpu.regfile_manager.regForwards 38521866 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 26722393 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 3469296 # Number of Branches Incorrectly Predicted As Taken. @@ -310,16 +303,16 @@ system.cpu.execution_unit.predictedNotTakenIncorrect 799060 system.cpu.execution_unit.mispredicted 4268356 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.predicted 5972346 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.mispredictPct 41.680307 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 57404028 # Number of Instructions Executed. +system.cpu.execution_unit.executions 57404027 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 458253 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 82970405 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 82971123 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 10389 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7736037 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 75607754 # Number of cycles cpu stages are processed. -system.cpu.activity 90.717920 # Percentage of cycles cpu is active +system.cpu.timesIdled 10519 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7752656 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 75607759 # Number of cycles cpu stages are processed. +system.cpu.activity 90.699835 # Percentage of cycles cpu is active system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed @@ -331,72 +324,72 @@ system.cpu.committedInsts 91903056 # Nu system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) -system.cpu.cpi 0.906866 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.907047 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.906866 # CPI: Total CPI of All Threads -system.cpu.ipc 1.102698 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.907047 # CPI: Total CPI of All Threads +system.cpu.ipc 1.102478 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.102698 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 27663446 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 55680345 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 66.808030 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 34092107 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 49251684 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 59.094605 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33492443 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 1.102478 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 27680069 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 55680346 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 66.794708 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 34108732 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 49251683 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 59.082819 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 33509067 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 49851348 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 59.814111 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65317278 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 18026513 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.629101 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 29484037 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 53859754 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.623595 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.utilization 59.802183 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65333914 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 18026501 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.624774 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 29500659 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 53859756 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.610710 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 7635 # number of replacements -system.cpu.icache.tags.tagsinuse 1492.268238 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1492.182806 # Cycle average of tags in use system.cpu.icache.tags.total_refs 9945551 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 9520 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1044.700735 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1492.268238 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.728647 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.728647 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1492.182806 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.728605 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.728605 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 9945551 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 9945551 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 9945551 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 9945551 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 9945551 # number of overall hits system.cpu.icache.overall_hits::total 9945551 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11398 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11398 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11398 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11398 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11398 # number of overall misses -system.cpu.icache.overall_misses::total 11398 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 318279500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 318279500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 318279500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 318279500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 318279500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 318279500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9956949 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9956949 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9956949 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9956949 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9956949 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9956949 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_misses::cpu.inst 11399 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11399 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11399 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11399 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11399 # number of overall misses +system.cpu.icache.overall_misses::total 11399 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 325867750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 325867750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 325867750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 325867750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 325867750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 325867750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9956950 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9956950 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9956950 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9956950 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9956950 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9956950 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001145 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001145 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001145 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.001145 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001145 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001145 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27924.153360 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27924.153360 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27924.153360 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27924.153360 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27924.153360 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27924.153360 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28587.398017 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28587.398017 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28587.398017 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28587.398017 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28587.398017 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28587.398017 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -405,38 +398,38 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 7 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1878 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1878 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1878 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1878 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1878 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1878 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1879 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1879 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1879 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1879 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1879 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1879 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9520 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 9520 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 9520 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 9520 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 9520 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 9520 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 259449500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 259449500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 259449500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 259449500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 259449500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 259449500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 266340500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 266340500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 266340500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 266340500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 266340500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 266340500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000956 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000956 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27253.098739 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27253.098739 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27253.098739 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 27253.098739 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27253.098739 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 27253.098739 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27976.943277 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27976.943277 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27976.943277 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 27976.943277 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27976.943277 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 27976.943277 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 18199316 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 18195687 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 9995 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 9995 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution @@ -452,23 +445,23 @@ system.cpu.toL2Bus.data_through_bus 758400 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 6032000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 14868500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 14812000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3600000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3559500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2189.714615 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2189.577948 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 6793 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3282 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 2.069775 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.843770 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1820.865070 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 351.005775 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 17.842967 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1820.748644 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 350.986337 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055568 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.010712 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.066825 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055565 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.010711 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.066821 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 6726 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6779 # number of ReadReq hits @@ -493,17 +486,17 @@ system.cpu.l2cache.demand_misses::total 4938 # nu system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4938 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 182392000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 29940500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 212332500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 115205000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 115205000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 182392000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 145145500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 327537500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 182392000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 145145500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 327537500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 189283000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32395250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 221678250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 122427250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 122427250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 189283000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 154822500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 344105500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 189283000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 154822500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 344105500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 9520 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 9995 # number of ReadReq accesses(hits+misses) @@ -528,17 +521,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.420506 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293487 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.420506 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65279.885469 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70949.052133 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 66023.787313 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66901.858304 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66901.858304 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65279.885469 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67698.460821 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66329.991900 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65279.885469 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67698.460821 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66329.991900 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67746.241947 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76765.995261 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68929.804104 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71095.963995 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71095.963995 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67746.241947 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72211.986940 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69685.196436 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67746.241947 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72211.986940 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69685.196436 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -558,17 +551,17 @@ system.cpu.l2cache.demand_mshr_misses::total 4938 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 147140500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24615500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 171756000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 94045000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 94045000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 147140500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 118660500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 265801000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 147140500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 118660500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 265801000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 154136500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27132250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 181268750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 101289250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 101289250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 154136500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 128421500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 282558000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 154136500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 128421500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 282558000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321761 # mshr miss rate for ReadReq accesses @@ -580,51 +573,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.420506 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.420506 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52663.027917 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58330.568720 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53406.716418 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54613.821138 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54613.821138 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52663.027917 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55345.382463 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53827.663021 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52663.027917 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55345.382463 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53827.663021 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55166.964925 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64294.431280 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56364.661070 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58820.702671 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58820.702671 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55166.964925 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59898.087687 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57221.142163 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55166.964925 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59898.087687 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57221.142163 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1441.455272 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26488508 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1441.367779 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26488450 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11915.658120 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11915.632029 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1441.455272 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.351918 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.351918 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 19995622 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 19995622 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492886 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492886 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26488508 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26488508 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26488508 # number of overall hits -system.cpu.dcache.overall_hits::total 26488508 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 576 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 576 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8217 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8217 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 8793 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 8793 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 8793 # number of overall misses -system.cpu.dcache.overall_misses::total 8793 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 38176750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 38176750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 468176250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 468176250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 506353000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 506353000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 506353000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 506353000 # number of overall miss cycles +system.cpu.dcache.tags.occ_blocks::cpu.data 1441.367779 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.351896 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.351896 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 19995621 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 19995621 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492829 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492829 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26488450 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26488450 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26488450 # number of overall hits +system.cpu.dcache.overall_hits::total 26488450 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 577 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 577 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8274 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8274 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 8851 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8851 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 8851 # number of overall misses +system.cpu.dcache.overall_misses::total 8851 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 41022750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 41022750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 492651500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 492651500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 533674250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 533674250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 533674250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 533674250 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -635,38 +628,38 @@ system.cpu.dcache.overall_accesses::cpu.data 26497301 system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000029 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001264 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001264 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000332 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000332 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000332 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000332 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66279.079861 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66279.079861 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56976.542534 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56976.542534 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 57585.920619 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 57585.920619 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 57585.920619 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 57585.920619 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 22475 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001273 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001273 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000334 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000334 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000334 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000334 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71096.620451 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71096.620451 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59542.119894 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59542.119894 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60295.362106 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60295.362106 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60295.362106 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60295.362106 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 23885 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 847 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 841 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.534829 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.400713 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 107 # number of writebacks system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 101 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6469 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6469 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6570 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6570 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6570 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6570 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 102 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 102 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6526 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6526 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6628 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6628 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6628 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6628 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses @@ -675,14 +668,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30964000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30964000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 117222500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 117222500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 148186500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 148186500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 148186500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 148186500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33418750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33418750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 124444750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 124444750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 157863500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 157863500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 157863500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 157863500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -691,14 +684,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65187.368421 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65187.368421 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67060.926773 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67060.926773 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66660.593792 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66660.593792 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66660.593792 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66660.593792 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70355.263158 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70355.263158 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71192.648741 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71192.648741 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71013.720198 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71013.720198 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71013.720198 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71013.720198 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 758c8228e..1aa820757 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,96 +1,98 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023492 # Number of seconds simulated -sim_ticks 23492267500 # Number of ticks simulated -final_tick 23492267500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023462 # Number of seconds simulated +sim_ticks 23461709500 # Number of ticks simulated +final_tick 23461709500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 158745 # Simulator instruction rate (inst/s) -host_op_rate 158745 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44301493 # Simulator tick rate (ticks/s) -host_mem_usage 233720 # Number of bytes of host memory used -host_seconds 530.28 # Real time elapsed on the host +host_inst_rate 165875 # Simulator instruction rate (inst/s) +host_op_rate 165875 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46230980 # Simulator tick rate (ticks/s) +host_mem_usage 261164 # Number of bytes of host memory used +host_seconds 507.49 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 195904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138560 # Number of bytes read from this memory -system.physmem.bytes_read::total 334464 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 195904 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 195904 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3061 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2165 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5226 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8339084 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5898111 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14237195 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8339084 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8339084 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8339084 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5898111 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 14237195 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5226 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 5226 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 334464 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 334464 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 469 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 291 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 301 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 520 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 220 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 227 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 220 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 289 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 237 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 280 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 248 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 252 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 398 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 337 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 491 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 446 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 23492140500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 5226 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 3268 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1366 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 506 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 78 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.bytes_read::cpu.inst 195968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138624 # Number of bytes read from this memory +system.physmem.bytes_read::total 334592 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 195968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 195968 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3062 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2166 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5228 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8352674 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5908521 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14261194 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8352674 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8352674 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8352674 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5908521 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 14261194 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5228 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 5228 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 334592 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 334592 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 466 # Per bank write bursts +system.physmem.perBankRdBursts::1 290 # Per bank write bursts +system.physmem.perBankRdBursts::2 300 # Per bank write bursts +system.physmem.perBankRdBursts::3 524 # Per bank write bursts +system.physmem.perBankRdBursts::4 220 # Per bank write bursts +system.physmem.perBankRdBursts::5 226 # Per bank write bursts +system.physmem.perBankRdBursts::6 219 # Per bank write bursts +system.physmem.perBankRdBursts::7 288 # Per bank write bursts +system.physmem.perBankRdBursts::8 240 # Per bank write bursts +system.physmem.perBankRdBursts::9 279 # Per bank write bursts +system.physmem.perBankRdBursts::10 248 # Per bank write bursts +system.physmem.perBankRdBursts::11 254 # Per bank write bursts +system.physmem.perBankRdBursts::12 400 # Per bank write bursts +system.physmem.perBankRdBursts::13 336 # Per bank write bursts +system.physmem.perBankRdBursts::14 491 # Per bank write bursts +system.physmem.perBankRdBursts::15 447 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 23461582500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 5228 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 3259 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1363 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 513 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 84 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -150,135 +152,127 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 416 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 780.923077 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 283.989164 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1375.157964 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 120 28.85% 28.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 59 14.18% 43.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 37 8.89% 51.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 19 4.57% 56.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 16 3.85% 60.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 20 4.81% 65.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 8 1.92% 67.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 8 1.92% 68.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 5 1.20% 70.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 5 1.20% 71.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 6 1.44% 72.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 8 1.92% 74.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 6 1.44% 76.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 4 0.96% 77.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 4 0.96% 78.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 2 0.48% 78.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 5 1.20% 79.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 3 0.72% 80.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 4 0.96% 81.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 3 0.72% 82.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 4 0.96% 83.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 3 0.72% 83.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 5 1.20% 85.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 3 0.72% 85.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 4 0.96% 86.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 3 0.72% 87.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 1 0.24% 87.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 3 0.72% 88.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 1 0.24% 88.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 4 0.96% 89.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 2 0.48% 90.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 2 0.48% 90.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 1 0.24% 90.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.24% 91.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 2 0.48% 91.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.24% 91.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 1 0.24% 92.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 2 0.48% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 1 0.24% 92.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 1 0.24% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.24% 93.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 1 0.24% 93.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.24% 93.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.24% 93.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 2 0.48% 94.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 1 0.24% 94.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 2 0.48% 95.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.24% 95.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 1 0.24% 95.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 5 1.20% 96.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 1 0.24% 97.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 1 0.24% 97.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 1 0.24% 97.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.24% 97.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 1 0.24% 98.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 1 0.24% 98.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 1 0.24% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 2 0.48% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 4 0.96% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 416 # Bytes accessed per row activation -system.physmem.totQLat 21308250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 115583250 # Sum of mem lat for all requests -system.physmem.totBusLat 26130000 # Total cycles spent in databus access -system.physmem.totBankLat 68145000 # Total cycles spent in bank access -system.physmem.avgQLat 4077.35 # Average queueing delay per request -system.physmem.avgBankLat 13039.61 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22116.96 # Average memory access latency -system.physmem.avgRdBW 14.24 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 14.24 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bytesPerActivate::samples 750 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 442.026667 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 206.409345 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 807.667918 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 266 35.47% 35.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 111 14.80% 50.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 59 7.87% 58.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 40 5.33% 63.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 26 3.47% 66.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 30 4.00% 70.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 24 3.20% 74.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 16 2.13% 76.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 9 1.20% 77.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 13 1.73% 79.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 15 2.00% 81.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 13 1.73% 82.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 37 4.93% 87.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 11 1.47% 89.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 6 0.80% 90.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 3 0.40% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 7 0.93% 91.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 7 0.93% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 3 0.40% 92.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 3 0.40% 93.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 8 1.07% 94.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 1 0.13% 94.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 3 0.40% 94.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 2 0.27% 95.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 4 0.53% 95.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 2 0.27% 95.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 1 0.13% 96.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 1 0.13% 96.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 3 0.40% 96.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 3 0.40% 96.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 1 0.13% 97.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 3 0.40% 97.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 1 0.13% 97.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 1 0.13% 97.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 3 0.40% 98.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 1 0.13% 98.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.13% 98.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 2 0.27% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 1 0.13% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 1 0.13% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 1 0.13% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 1 0.13% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 1 0.13% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 1 0.13% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 1 0.13% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 2 0.27% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 1 0.13% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 750 # Bytes accessed per row activation +system.physmem.totQLat 37518250 # Total ticks spent queuing +system.physmem.totMemAccLat 134402000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26140000 # Total ticks spent in databus transfers +system.physmem.totBankLat 70743750 # Total ticks spent accessing banks +system.physmem.avgQLat 7176.41 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13531.70 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 25708.11 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 14.26 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 14.26 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.11 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4810 # Number of row buffer hits during reads +system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 4478 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 92.04 # Row buffer hit rate for reads +system.physmem.readRowHitRate 85.65 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4495243.11 # Average gap between requests -system.membus.throughput 14237195 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 3520 # Transaction distribution -system.membus.trans_dist::ReadResp 3520 # Transaction distribution -system.membus.trans_dist::ReadExReq 1706 # Transaction distribution -system.membus.trans_dist::ReadExResp 1706 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10452 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10452 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334464 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 334464 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 334464 # Total data (bytes) +system.physmem.avgGap 4487678.37 # Average gap between requests +system.physmem.pageHitRate 85.65 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 1.19 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 14261194 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3523 # Transaction distribution +system.membus.trans_dist::ReadResp 3523 # Transaction distribution +system.membus.trans_dist::ReadExReq 1705 # Transaction distribution +system.membus.trans_dist::ReadExResp 1705 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10456 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10456 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334592 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 334592 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 334592 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6824500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6832000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 49069500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 49013750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.cpu.branchPred.lookups 14868892 # Number of BP lookups -system.cpu.branchPred.condPredicted 10787177 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 926932 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8430316 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6969924 # Number of BTB hits +system.cpu.branchPred.lookups 14847721 # Number of BP lookups +system.cpu.branchPred.condPredicted 10774921 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 922205 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8301784 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6957683 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 82.676901 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1469870 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3126 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 83.809492 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1467978 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3097 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 23134581 # DTB read hits -system.cpu.dtb.read_misses 192685 # DTB read misses -system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 23327266 # DTB read accesses -system.cpu.dtb.write_hits 7072669 # DTB write hits -system.cpu.dtb.write_misses 1128 # DTB write misses -system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 7073797 # DTB write accesses -system.cpu.dtb.data_hits 30207250 # DTB hits -system.cpu.dtb.data_misses 193813 # DTB misses -system.cpu.dtb.data_acv 4 # DTB access violations -system.cpu.dtb.data_accesses 30401063 # DTB accesses -system.cpu.itb.fetch_hits 14756036 # ITB hits -system.cpu.itb.fetch_misses 101 # ITB misses +system.cpu.dtb.read_hits 23117785 # DTB read hits +system.cpu.dtb.read_misses 192281 # DTB read misses +system.cpu.dtb.read_acv 4 # DTB read access violations +system.cpu.dtb.read_accesses 23310066 # DTB read accesses +system.cpu.dtb.write_hits 7068175 # DTB write hits +system.cpu.dtb.write_misses 1137 # DTB write misses +system.cpu.dtb.write_acv 4 # DTB write access violations +system.cpu.dtb.write_accesses 7069312 # DTB write accesses +system.cpu.dtb.data_hits 30185960 # DTB hits +system.cpu.dtb.data_misses 193418 # DTB misses +system.cpu.dtb.data_acv 8 # DTB access violations +system.cpu.dtb.data_accesses 30379378 # DTB accesses +system.cpu.itb.fetch_hits 14734161 # ITB hits +system.cpu.itb.fetch_misses 103 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14756137 # ITB accesses +system.cpu.itb.fetch_accesses 14734264 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -292,237 +286,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 46984536 # number of cpu cycles simulated +system.cpu.numCycles 46923420 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15488073 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 127117981 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14868892 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 8439794 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22159630 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4494895 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5563054 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2312 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14756036 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 325999 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46746670 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.719295 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.375691 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15463377 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 126961895 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14847721 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 8425661 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22130057 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4473004 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5559399 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 52 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2205 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 25 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 14734161 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 324640 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46671602 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.720324 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.376096 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24587040 52.60% 52.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2365337 5.06% 57.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1191741 2.55% 60.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1747442 3.74% 63.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2760154 5.90% 69.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1154764 2.47% 72.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1218466 2.61% 74.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 772204 1.65% 76.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10949522 23.42% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24541545 52.58% 52.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2361252 5.06% 57.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1192515 2.56% 60.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1742111 3.73% 63.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2755702 5.90% 69.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1149393 2.46% 72.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1220691 2.62% 74.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 771783 1.65% 76.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10936610 23.43% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46746670 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.316464 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.705528 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17316199 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4260248 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20549941 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1098483 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3521799 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2517933 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12169 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 124122749 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 32253 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3521799 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18461305 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 962240 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7648 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20480612 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3313066 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 121283530 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 59 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 398899 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2436739 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 89066471 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 157595093 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 150534218 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7060874 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 46671602 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.316425 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.705726 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17289391 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4257221 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20524695 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1095542 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3504753 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2511898 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12165 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 123979131 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 31595 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3504753 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18431775 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 963421 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7928 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20455401 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3308324 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 121154586 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 87 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 400162 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2430153 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 88974234 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 157440436 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 150394666 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7045769 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 20639110 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 733 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 729 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8785388 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 25392018 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8252125 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2596537 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 925406 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 105547434 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2098 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 96644788 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 177437 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 20878127 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15672265 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1709 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46746670 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.067415 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.876261 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 20546873 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 749 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 744 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8783261 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 25363135 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8241350 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2569635 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 893782 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 105438340 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 961 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 96565073 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 178504 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 20784584 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15622472 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 572 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46671602 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.069033 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.876517 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12170136 26.03% 26.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 9358863 20.02% 46.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8416132 18.00% 64.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6289434 13.45% 77.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4916374 10.52% 88.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2864607 6.13% 94.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1727461 3.70% 97.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 797242 1.71% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 206421 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12133901 26.00% 26.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9340973 20.01% 46.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8404137 18.01% 64.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6285068 13.47% 77.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4921134 10.54% 88.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2853572 6.11% 94.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1727806 3.70% 97.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 798698 1.71% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 206313 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46746670 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46671602 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 188535 12.02% 12.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 12.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 12.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 207 0.01% 12.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 7191 0.46% 12.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 5653 0.36% 12.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 842893 53.74% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.60% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 446132 28.45% 95.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 77750 4.96% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 187905 11.99% 11.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 198 0.01% 12.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 7114 0.45% 12.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 5683 0.36% 12.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 843073 53.81% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 444038 28.34% 94.98% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 78699 5.02% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58781922 60.82% 60.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 479844 0.50% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58732394 60.82% 60.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 479878 0.50% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2799901 2.90% 64.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115380 0.12% 64.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2387749 2.47% 66.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 311051 0.32% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 760106 0.79% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23852037 24.68% 92.60% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7156472 7.40% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2798409 2.90% 64.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115272 0.12% 64.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2387143 2.47% 66.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 310920 0.32% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 760028 0.79% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23829441 24.68% 92.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7151262 7.41% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 96644788 # Type of FU issued -system.cpu.iq.rate 2.056949 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1568361 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016228 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 226659796 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 117693658 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87130802 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15122248 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 8768674 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7065649 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90221948 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7991194 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1517986 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 96565073 # Type of FU issued +system.cpu.iq.rate 2.057929 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1566710 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016224 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 226434514 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 117518312 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87069210 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15112448 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 8740080 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7062492 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90145383 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7986393 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1518186 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5395820 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 18680 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34810 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1751022 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5366937 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 18425 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34629 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1740247 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10535 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1932 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10551 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2023 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3521799 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 133427 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18321 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 115791419 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 375079 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 25392018 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8252125 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2098 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2892 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 38 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34810 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 537595 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 497018 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1034613 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 95405393 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23327731 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1239395 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3504753 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 133474 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 18356 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 115674273 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 366324 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 25363135 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8241350 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 961 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2994 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 35 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 34629 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 535207 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 494157 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1029364 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 95337689 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23310553 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1227384 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10241887 # number of nop insts executed -system.cpu.iew.exec_refs 30401730 # number of memory reference insts executed -system.cpu.iew.exec_branches 12031007 # Number of branches executed -system.cpu.iew.exec_stores 7073999 # Number of stores executed -system.cpu.iew.exec_rate 2.030570 # Inst execution rate -system.cpu.iew.wb_sent 94717591 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 94196451 # cumulative count of insts written-back -system.cpu.iew.wb_producers 64508240 # num instructions producing a value -system.cpu.iew.wb_consumers 89892394 # num instructions consuming a value +system.cpu.iew.exec_nop 10234972 # number of nop insts executed +system.cpu.iew.exec_refs 30380075 # number of memory reference insts executed +system.cpu.iew.exec_branches 12022158 # Number of branches executed +system.cpu.iew.exec_stores 7069522 # Number of stores executed +system.cpu.iew.exec_rate 2.031772 # Inst execution rate +system.cpu.iew.wb_sent 94652013 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 94131702 # cumulative count of insts written-back +system.cpu.iew.wb_producers 64474348 # num instructions producing a value +system.cpu.iew.wb_consumers 89850693 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.004839 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717616 # average fanout of values written-back +system.cpu.iew.wb_rate 2.006071 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717572 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23889448 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 23772324 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 915179 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43224871 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.126161 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.744271 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 910471 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43166849 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.129019 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.746086 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16760873 38.78% 38.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9929358 22.97% 61.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4485318 10.38% 72.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2262602 5.23% 77.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1610546 3.73% 81.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1125217 2.60% 83.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 721883 1.67% 85.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 816904 1.89% 87.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5512170 12.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16723467 38.74% 38.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9908467 22.95% 61.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4486822 10.39% 72.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2263317 5.24% 77.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1605459 3.72% 81.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1122723 2.60% 83.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 719573 1.67% 85.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 818064 1.90% 87.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5518957 12.79% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43224871 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43166849 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -533,212 +528,212 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5512170 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5518957 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 153504164 # The number of ROB reads -system.cpu.rob.rob_writes 235130535 # The number of ROB writes -system.cpu.timesIdled 5262 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 237866 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 153322231 # The number of ROB reads +system.cpu.rob.rob_writes 234879486 # The number of ROB writes +system.cpu.timesIdled 5401 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 251818 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.558146 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.558146 # CPI: Total CPI of All Threads -system.cpu.ipc 1.791647 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.791647 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 129142322 # number of integer regfile reads -system.cpu.int_regfile_writes 70569523 # number of integer regfile writes -system.cpu.fp_regfile_reads 6189856 # number of floating regfile reads -system.cpu.fp_regfile_writes 6047601 # number of floating regfile writes -system.cpu.misc_regfile_reads 714537 # number of misc regfile reads +system.cpu.cpi 0.557420 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.557420 # CPI: Total CPI of All Threads +system.cpu.ipc 1.793981 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.793981 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 129048096 # number of integer regfile reads +system.cpu.int_regfile_writes 70519804 # number of integer regfile writes +system.cpu.fp_regfile_reads 6188545 # number of floating regfile reads +system.cpu.fp_regfile_writes 6044303 # number of floating regfile writes +system.cpu.misc_regfile_reads 714547 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 37717943 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 12006 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 12006 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 108 # Transaction distribution +system.cpu.toL2Bus.throughput 37824354 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 12026 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 12026 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 109 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1731 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1731 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22984 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4598 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27582 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 735488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 886080 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 886080 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23020 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4603 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27623 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 736640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 887424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 887424 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 7030500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 7042000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 17871250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 17847250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3590750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3547000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 9559 # number of replacements -system.cpu.icache.tags.tagsinuse 1595.799290 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 14741729 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 11492 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1282.781848 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 9576 # number of replacements +system.cpu.icache.tags.tagsinuse 1596.482982 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 14719875 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 11510 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1278.877063 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1595.799290 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.779199 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.779199 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14741729 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14741729 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14741729 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14741729 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14741729 # number of overall hits -system.cpu.icache.overall_hits::total 14741729 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14307 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14307 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14307 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14307 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14307 # number of overall misses -system.cpu.icache.overall_misses::total 14307 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 399491250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 399491250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 399491250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 399491250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 399491250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 399491250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14756036 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14756036 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14756036 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14756036 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14756036 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14756036 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 1596.482982 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.779533 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.779533 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14719875 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14719875 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14719875 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14719875 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14719875 # number of overall hits +system.cpu.icache.overall_hits::total 14719875 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14285 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14285 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14285 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14285 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14285 # number of overall misses +system.cpu.icache.overall_misses::total 14285 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 413142250 # 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miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.893411 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.292949 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.984980 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.984980 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.266030 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.963952 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.380025 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.266030 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.963952 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.380025 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67821.603527 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74970.173536 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68757.025263 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72908.651026 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72908.651026 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67821.603527 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73347.414589 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70110.988906 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67821.603527 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73347.414589 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70110.988906 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -747,178 +742,178 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3061 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 459 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3520 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1706 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1706 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3061 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2165 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 282275500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 160781250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 121494250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 282275500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.266359 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.892996 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.293187 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985557 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985557 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.266359 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52525.726887 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56117.436490 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54013.681592 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52525.726887 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56117.436490 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54013.681592 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3062 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 461 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3523 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1705 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1705 # 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number of replacements -system.cpu.dcache.tags.tagsinuse 1457.925933 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28096273 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2245 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12515.043653 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 159 # number of replacements +system.cpu.dcache.tags.tagsinuse 1459.152637 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28079168 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2247 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12496.291945 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1457.925933 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.355939 # 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number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8212 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8212 # number of WriteReq misses +system.cpu.dcache.tags.occ_blocks::cpu.data 1459.152637 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.356238 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.356238 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 21586035 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21586035 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492869 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492869 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 264 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 264 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28078904 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28078904 # 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number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21587009 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21587009 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 237 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 237 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28105237 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28105237 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28105237 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28105237 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001263 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001263 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004219 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004219 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000327 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000327 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000327 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000327 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60881.072874 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60881.072874 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58069.964321 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 58069.964321 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 265 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 265 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28088112 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28088112 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28088112 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28088112 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001267 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001267 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003774 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003774 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000328 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000328 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000328 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000328 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59845.739220 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59845.739220 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61430.142701 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61430.142701 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 58371.852935 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 58371.852935 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 58371.852935 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 58371.852935 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21919 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61262.548328 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61262.548328 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61262.548328 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61262.548328 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 24052 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 336 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 65.235119 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 71.583333 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 108 # number of writebacks -system.cpu.dcache.writebacks::total 108 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 475 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 475 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6481 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6481 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6956 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6956 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6956 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6956 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 513 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 513 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 109 # number of writebacks +system.cpu.dcache.writebacks::total 109 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 459 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 459 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6503 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6503 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6962 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6962 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6962 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6962 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 515 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 515 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1731 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1731 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2244 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2244 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2244 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2244 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 35017250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 35017250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116268497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 116268497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2246 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2246 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2246 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2246 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 35552500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 35552500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 126440497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 126440497 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 151285747 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 151285747 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 151285747 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 151285747 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161992997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 161992997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161992997 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 161992997 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004219 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004219 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.003774 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.003774 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68259.746589 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68259.746589 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67168.398036 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67168.398036 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69033.980583 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69033.980583 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73044.770075 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73044.770075 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67417.890820 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67417.890820 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67417.890820 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67417.890820 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72125.109973 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72125.109973 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72125.109973 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72125.109973 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index a815317b1..4425c72f1 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,96 +1,98 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.074201 # Number of seconds simulated -sim_ticks 74201024500 # Number of ticks simulated -final_tick 74201024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.074220 # Number of seconds simulated +sim_ticks 74219948500 # Number of ticks simulated +final_tick 74219948500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 115322 # Simulator instruction rate (inst/s) -host_op_rate 126267 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49662501 # Simulator tick rate (ticks/s) -host_mem_usage 251448 # Number of bytes of host memory used -host_seconds 1494.11 # Real time elapsed on the host +host_inst_rate 110839 # Simulator instruction rate (inst/s) +host_op_rate 121359 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47744278 # Simulator tick rate (ticks/s) +host_mem_usage 278976 # Number of bytes of host memory used +host_seconds 1554.53 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 188656503 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 131328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 111872 # Number of bytes read from this memory -system.physmem.bytes_read::total 243200 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 131328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 131328 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2052 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1748 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3800 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1769895 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1507688 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3277583 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1769895 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1769895 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1769895 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1507688 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3277583 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3801 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 3801 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 243200 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 243200 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 308 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 215 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 134 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 308 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 298 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 300 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 261 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 216 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 246 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 215 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 289 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 194 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 191 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 208 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 218 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 200 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 74201006000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 3801 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 2829 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 792 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.bytes_read::cpu.inst 131072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 111680 # Number of bytes read from this memory +system.physmem.bytes_read::total 242752 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 131072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 131072 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2048 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1745 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3793 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1765994 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1504717 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3270711 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1765994 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1765994 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1765994 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1504717 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3270711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3794 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 3794 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 242816 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 242816 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 306 # Per bank write bursts +system.physmem.perBankRdBursts::1 215 # Per bank write bursts +system.physmem.perBankRdBursts::2 133 # Per bank write bursts +system.physmem.perBankRdBursts::3 308 # Per bank write bursts +system.physmem.perBankRdBursts::4 298 # Per bank write bursts +system.physmem.perBankRdBursts::5 299 # Per bank write bursts +system.physmem.perBankRdBursts::6 264 # Per bank write bursts +system.physmem.perBankRdBursts::7 216 # Per bank write bursts +system.physmem.perBankRdBursts::8 246 # Per bank write bursts +system.physmem.perBankRdBursts::9 215 # Per bank write bursts +system.physmem.perBankRdBursts::10 289 # Per bank write bursts +system.physmem.perBankRdBursts::11 193 # Per bank write bursts +system.physmem.perBankRdBursts::12 189 # Per bank write bursts +system.physmem.perBankRdBursts::13 206 # Per bank write bursts +system.physmem.perBankRdBursts::14 217 # Per bank write bursts +system.physmem.perBankRdBursts::15 200 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 74219930000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 3794 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 2825 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 142 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -150,114 +152,100 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 389 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 616.966581 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 221.267348 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1216.553816 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 139 35.73% 35.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 59 15.17% 50.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 33 8.48% 59.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 24 6.17% 65.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 15 3.86% 69.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 13 3.34% 72.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 4 1.03% 73.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 7 1.80% 75.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 5 1.29% 76.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 8 2.06% 78.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 4 1.03% 79.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 4 1.03% 80.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 3 0.77% 81.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 3 0.77% 82.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 5 1.29% 83.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 4 1.03% 84.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 4 1.03% 85.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 1 0.26% 86.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 1 0.26% 86.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 3 0.77% 87.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 3 0.77% 87.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 3 0.77% 88.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 2 0.51% 89.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 1 0.26% 89.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 3 0.77% 90.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 3 0.77% 91.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 1 0.26% 91.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 1 0.26% 91.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 1 0.26% 91.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 1 0.26% 92.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 2 0.51% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 1 0.26% 92.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.26% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.26% 93.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.26% 93.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.26% 93.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 1 0.26% 94.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.26% 94.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.26% 94.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 1 0.26% 94.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 1 0.26% 95.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.26% 95.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 4 1.03% 96.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.26% 96.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.26% 96.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 1 0.26% 97.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 1 0.26% 97.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 1 0.26% 97.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 1 0.26% 97.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 1 0.26% 98.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 1 0.26% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 1 0.26% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 1 0.26% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 1 0.26% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 1 0.26% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 2 0.51% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 389 # Bytes accessed per row activation -system.physmem.totQLat 12962000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 86183250 # Sum of mem lat for all requests -system.physmem.totBusLat 19005000 # Total cycles spent in databus access -system.physmem.totBankLat 54216250 # Total cycles spent in bank access -system.physmem.avgQLat 3410.16 # Average queueing delay per request -system.physmem.avgBankLat 14263.68 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22673.84 # Average memory access latency -system.physmem.avgRdBW 3.28 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.28 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bytesPerActivate::samples 717 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 334.192469 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 180.652659 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 576.534776 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 257 35.84% 35.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 120 16.74% 52.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 71 9.90% 62.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 49 6.83% 69.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 19 2.65% 71.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 26 3.63% 75.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 20 2.79% 78.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 17 2.37% 80.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 17 2.37% 83.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 40 5.58% 88.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 17 2.37% 91.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 6 0.84% 91.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 6 0.84% 92.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 8 1.12% 93.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 6 0.84% 94.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 5 0.70% 95.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 4 0.56% 95.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 1 0.14% 96.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 2 0.28% 96.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 2 0.28% 96.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 2 0.28% 96.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 2 0.28% 97.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 1 0.14% 97.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 1 0.14% 97.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 1 0.14% 97.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 1 0.14% 97.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 1 0.14% 97.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 2 0.28% 98.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 1 0.14% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 2 0.28% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 1 0.14% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 1 0.14% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 1 0.14% 99.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 1 0.14% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 1 0.14% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 1 0.14% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 1 0.14% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 1 0.14% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 1 0.14% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 1 0.14% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 717 # Bytes accessed per row activation +system.physmem.totQLat 25205500 # Total ticks spent queuing +system.physmem.totMemAccLat 100715500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 18970000 # Total ticks spent in databus transfers +system.physmem.totBankLat 56540000 # Total ticks spent accessing banks +system.physmem.avgQLat 6643.52 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14902.48 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26545.99 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.27 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 3412 # Number of row buffer hits during reads +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 3077 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.77 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.10 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19521443.30 # Average gap between requests -system.membus.throughput 3277583 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 2726 # Transaction distribution -system.membus.trans_dist::ReadResp 2725 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 1075 # Transaction distribution -system.membus.trans_dist::ReadExResp 1075 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7605 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7605 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 243200 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 243200 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 243200 # Total data (bytes) +system.physmem.avgGap 19562448.60 # Average gap between requests +system.physmem.pageHitRate 81.10 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.24 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 3270711 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 2723 # Transaction distribution +system.membus.trans_dist::ReadResp 2722 # Transaction distribution +system.membus.trans_dist::ReadExReq 1071 # Transaction distribution +system.membus.trans_dist::ReadExResp 1071 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7587 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7587 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 242752 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 242752 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 242752 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 4684500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4683500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 35707998 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 35533250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 94803777 # Number of BP lookups -system.cpu.branchPred.condPredicted 74793629 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6279390 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 44652033 # Number of BTB lookups -system.cpu.branchPred.BTBHits 43049215 # Number of BTB hits +system.cpu.branchPred.lookups 94784279 # Number of BP lookups +system.cpu.branchPred.condPredicted 74784012 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6281562 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 44678427 # Number of BTB lookups +system.cpu.branchPred.BTBHits 43050018 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 96.410425 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 4355984 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 88442 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 96.355268 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 4356637 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 88400 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -301,135 +289,135 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 148402050 # number of cpu cycles simulated +system.cpu.numCycles 148439898 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 39645282 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 380210735 # Number of instructions fetch has processed -system.cpu.fetch.Branches 94803777 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 47405199 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80366135 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 27283939 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7211893 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 5835 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 39656913 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 380179952 # Number of instructions fetch has processed +system.cpu.fetch.Branches 94784279 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 47406655 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80370667 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 27283129 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7220970 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 44 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 6188 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 74 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 36839707 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1829204 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 148218142 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.802317 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.153165 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 50 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 36850892 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1831983 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 148240575 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.801601 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.152871 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68020669 45.89% 45.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5263809 3.55% 49.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10529342 7.10% 56.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10284383 6.94% 63.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8663442 5.85% 69.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6544357 4.42% 73.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6237651 4.21% 77.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8018779 5.41% 83.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 24655710 16.63% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68038754 45.90% 45.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5265463 3.55% 49.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10540667 7.11% 56.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10285704 6.94% 63.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8660470 5.84% 69.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6545128 4.42% 73.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6246382 4.21% 77.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8002829 5.40% 83.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 24655178 16.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 148218142 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.638831 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.562032 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45496346 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5881053 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74801402 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1203851 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 20835490 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14335605 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 164633 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 392823460 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 736203 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 20835490 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 50883815 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 724795 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 600466 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 70555670 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4617906 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 371356593 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 28 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 342994 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3662384 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 29 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 631760398 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1581883462 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1507069248 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3196133 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 148240575 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.638536 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.561171 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45513789 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5886753 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74804125 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1203493 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 20832415 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14327913 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 164349 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 392779898 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 733794 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 20832415 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50900742 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 730699 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 603190 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 70558310 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4615219 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 371308094 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 339277 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3661219 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 233 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 631703486 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1581699955 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1506871299 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3203425 # Number of floating rename lookups system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 333716259 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25188 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25185 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13032916 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 43019038 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16425001 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5693552 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3686945 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 329243417 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 47203 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 249464214 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 795417 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 139561180 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 362246737 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1987 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 148218142 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.683088 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.761802 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 333659347 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 25072 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 25068 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13010245 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 43012685 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16416405 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5733542 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3666500 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 329190158 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 47154 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 249456619 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 789371 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 139503403 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 362002811 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1938 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 148240575 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.682782 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.761427 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56048230 37.81% 37.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 22642926 15.28% 53.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 24814212 16.74% 69.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20312337 13.70% 83.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12552656 8.47% 92.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6518158 4.40% 96.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4033272 2.72% 99.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1116001 0.75% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 180350 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56059831 37.82% 37.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 22638796 15.27% 53.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24824163 16.75% 69.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20343400 13.72% 83.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12534795 8.46% 92.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6516114 4.40% 96.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4026097 2.72% 99.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1116067 0.75% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 181312 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 148218142 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 148240575 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 965237 38.47% 38.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5595 0.22% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 98 0.00% 38.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 50 0.00% 38.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1168121 46.56% 85.25% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 370007 14.75% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 965215 38.57% 38.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5593 0.22% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 101 0.00% 38.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 48 0.00% 38.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1158967 46.31% 85.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 372730 14.89% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 194903493 78.13% 78.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 979289 0.39% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 194899965 78.13% 78.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 979613 0.39% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued @@ -448,93 +436,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.52% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33083 0.01% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 164442 0.07% 78.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 254821 0.10% 78.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76413 0.03% 78.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 465720 0.19% 78.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33082 0.01% 78.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 164367 0.07% 78.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 255141 0.10% 78.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76420 0.03% 78.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 466123 0.19% 78.92% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 206380 0.08% 79.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71858 0.03% 79.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 79.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 38359883 15.38% 94.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13948512 5.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71866 0.03% 79.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 38355278 15.38% 94.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13948063 5.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 249464214 # Type of FU issued -system.cpu.iq.rate 1.681002 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2509108 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010058 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 646714008 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 466681926 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237887502 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3737087 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2188015 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1841410 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 250098110 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1875212 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2005238 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 249456619 # Type of FU issued +system.cpu.iq.rate 1.680523 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2502654 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010032 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 646705831 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 466563436 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237885445 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3740007 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2195697 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1842613 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 250082854 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1876419 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2013198 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13169554 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11470 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18663 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3780367 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13163201 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11604 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18881 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3771771 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 11 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 113 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 107 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 20835490 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 18710 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 879 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 329307607 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 785363 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 43019038 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16425001 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 24795 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 182 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 275 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18663 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3889158 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3759638 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7648796 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 242968769 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 36856935 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6495445 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 20832415 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 18550 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 893 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 329254508 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 785294 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 43012685 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16416405 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 24746 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 188 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 276 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18881 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3889958 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3760086 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7650044 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 242960519 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 36851938 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6496100 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 16987 # number of nop insts executed -system.cpu.iew.exec_refs 50502724 # number of memory reference insts executed -system.cpu.iew.exec_branches 53433142 # Number of branches executed -system.cpu.iew.exec_stores 13645789 # Number of stores executed -system.cpu.iew.exec_rate 1.637233 # Inst execution rate -system.cpu.iew.wb_sent 240789077 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 239728912 # cumulative count of insts written-back -system.cpu.iew.wb_producers 148477198 # num instructions producing a value -system.cpu.iew.wb_consumers 267296630 # num instructions consuming a value +system.cpu.iew.exec_nop 17196 # number of nop insts executed +system.cpu.iew.exec_refs 50500394 # number of memory reference insts executed +system.cpu.iew.exec_branches 53426072 # Number of branches executed +system.cpu.iew.exec_stores 13648456 # Number of stores executed +system.cpu.iew.exec_rate 1.636760 # Inst execution rate +system.cpu.iew.wb_sent 240785663 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 239728058 # cumulative count of insts written-back +system.cpu.iew.wb_producers 148474079 # num instructions producing a value +system.cpu.iew.wb_consumers 267261472 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.615402 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.555477 # average fanout of values written-back +system.cpu.iew.wb_rate 1.614984 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.555539 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 140636703 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 140583620 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6125970 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 127382652 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.481135 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.185870 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6128235 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 127408160 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.480838 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.185451 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 57681624 45.28% 45.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 31696418 24.88% 70.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13781439 10.82% 80.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7634613 5.99% 86.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4380226 3.44% 90.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1319827 1.04% 91.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1706186 1.34% 92.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1307951 1.03% 93.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7874368 6.18% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 57701826 45.29% 45.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 31696936 24.88% 70.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13777779 10.81% 80.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7640619 6.00% 86.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4387787 3.44% 90.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1321958 1.04% 91.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1703212 1.34% 92.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1308014 1.03% 93.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7870029 6.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 127382652 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 127408160 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317409 # Number of instructions committed system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -545,220 +533,212 @@ system.cpu.commit.branches 40300311 # Nu system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. system.cpu.commit.int_insts 150106217 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 7874368 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 7870029 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 448810677 # The number of ROB reads -system.cpu.rob.rob_writes 679560182 # The number of ROB writes -system.cpu.timesIdled 2800 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 183908 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 448787441 # The number of ROB reads +system.cpu.rob.rob_writes 679451137 # The number of ROB writes +system.cpu.timesIdled 2805 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 199323 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303021 # Number of Instructions Simulated system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated -system.cpu.cpi 0.861285 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.861285 # CPI: Total CPI of All Threads -system.cpu.ipc 1.161056 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.161056 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1079439367 # number of integer regfile reads -system.cpu.int_regfile_writes 384873719 # number of integer regfile writes -system.cpu.fp_regfile_reads 2913212 # number of floating regfile reads -system.cpu.fp_regfile_writes 2497494 # number of floating regfile writes -system.cpu.misc_regfile_reads 54494427 # number of misc regfile reads +system.cpu.cpi 0.861505 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.861505 # CPI: Total CPI of All Threads +system.cpu.ipc 1.160759 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.160759 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1079417004 # number of integer regfile reads +system.cpu.int_regfile_writes 384871783 # number of integer regfile writes +system.cpu.fp_regfile_reads 2913086 # number of floating regfile reads +system.cpu.fp_regfile_writes 2499105 # number of floating regfile writes +system.cpu.misc_regfile_reads 54501288 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.toL2Bus.throughput 5172543 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 4897 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 4896 # Transaction distribution +system.cpu.toL2Bus.throughput 5169500 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 4899 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 4898 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 18 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1083 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1083 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8247 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3732 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 11979 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 263808 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 1079 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1079 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8251 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3722 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 11973 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 264000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119680 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size::total 383680 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 383680 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 128 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3018000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3016000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6609745 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6552496 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3106490 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3047739 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 2391 # number of replacements -system.cpu.icache.tags.tagsinuse 1346.456608 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 36834377 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4122 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8936.044881 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2394 # number of replacements +system.cpu.icache.tags.tagsinuse 1347.740549 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 36845555 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4125 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8932.255758 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1346.456608 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.657450 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.657450 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 36834377 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 36834377 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 36834377 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 36834377 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 36834377 # number of overall hits -system.cpu.icache.overall_hits::total 36834377 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5330 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5330 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5330 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5330 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5330 # number of overall misses -system.cpu.icache.overall_misses::total 5330 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 215954243 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 215954243 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 215954243 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 215954243 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 215954243 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 215954243 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 36839707 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 36839707 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 36839707 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 36839707 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 36839707 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 36839707 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 1347.740549 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.658076 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.658076 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 36845555 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 36845555 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 36845555 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 36845555 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 36845555 # number of overall hits +system.cpu.icache.overall_hits::total 36845555 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5337 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5337 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5337 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5337 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5337 # number of overall misses +system.cpu.icache.overall_misses::total 5337 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 225944745 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 225944745 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 225944745 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 225944745 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 225944745 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 225944745 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 36850892 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 36850892 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 36850892 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 36850892 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 36850892 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 36850892 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000145 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000145 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000145 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000145 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000145 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000145 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40516.743527 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 40516.743527 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 40516.743527 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 40516.743527 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 40516.743527 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 40516.743527 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1739 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42335.534008 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42335.534008 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42335.534008 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42335.534008 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42335.534008 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42335.534008 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1128 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 21 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 82.809524 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 59.368421 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1205 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1205 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1205 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1205 # 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number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54590750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111409500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 92723500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 204133000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111409500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 92723500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 204133000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.497938 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871762 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.556895 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992613 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992613 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.497938 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942318 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.635831 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.497938 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942318 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.635831 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54266.682903 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56660.846954 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54857.758621 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50782.093023 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50782.093023 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54266.682903 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53045.480549 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53705.077611 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54266.682903 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53045.480549 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53705.077611 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 11 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 15 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 11 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 11 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2049 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 674 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2723 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1071 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1071 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2049 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1745 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3794 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2049 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1745 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 3794 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117254500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42298000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159552500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 58841750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 58841750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117254500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101139750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 218394250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117254500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101139750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 218394250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871928 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.555828 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992586 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992586 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942225 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.634660 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.496607 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942225 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.634660 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57225.231820 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62756.676558 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58594.381197 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54940.943044 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54940.943044 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57225.231820 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57959.742120 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57563.060095 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57225.231820 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57959.742120 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57563.060095 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 57 # number of replacements -system.cpu.dcache.tags.tagsinuse 1404.261851 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 46798452 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1855 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 25228.276011 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1406.103135 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 46786156 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1852 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 25262.503240 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1404.261851 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.342837 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.342837 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 34397014 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 34397014 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12356557 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12356557 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22472 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22472 # number of LoadLockedReq hits +system.cpu.dcache.tags.occ_blocks::cpu.data 1406.103135 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.343287 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.343287 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 34384711 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 34384711 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12356564 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12356564 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22474 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22474 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 46753571 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 46753571 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 46753571 # number of overall hits -system.cpu.dcache.overall_hits::total 46753571 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1913 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1913 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 7730 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 7730 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 46741275 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 46741275 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 46741275 # number of overall hits +system.cpu.dcache.overall_hits::total 46741275 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1902 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1902 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 7723 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 7723 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9643 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9643 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9643 # number of overall misses -system.cpu.dcache.overall_misses::total 9643 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 114314976 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 114314976 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 447415748 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 447415748 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9625 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9625 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9625 # number of overall misses +system.cpu.dcache.overall_misses::total 9625 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 121870727 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 121870727 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 465623246 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 465623246 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 142500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 561730724 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 561730724 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 561730724 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 561730724 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 34398927 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 34398927 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 587493973 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 587493973 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 587493973 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 587493973 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 34386613 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 34386613 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22474 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 22474 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22476 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22476 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46763214 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46763214 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46763214 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46763214 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000056 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000056 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 46750900 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46750900 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46750900 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46750900 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000055 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000055 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000625 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000625 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses @@ -892,68 +864,68 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59756.913748 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59756.913748 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57880.433118 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 57880.433118 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64075.040484 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 64075.040484 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60290.463033 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60290.463033 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 58252.693560 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 58252.693560 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 58252.693560 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 58252.693560 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 597 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 154 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61038.334857 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61038.334857 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61038.334857 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61038.334857 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 592 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 314 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.272727 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 77 # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.818182 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 78.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 18 # number of writebacks system.cpu.dcache.writebacks::total 18 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1140 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1140 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6646 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6646 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1128 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1128 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6645 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6645 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7786 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7786 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7786 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7786 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 773 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 773 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1084 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1084 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1857 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1857 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1857 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1857 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 48960262 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 48960262 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 69313496 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 69313496 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 118273758 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 118273758 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 118273758 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 118273758 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 7773 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7773 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7773 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7773 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 774 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 774 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1078 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1078 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1852 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1852 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1852 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1852 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53114761 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 53114761 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73392998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 73392998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126507759 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 126507759 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126507759 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 126507759 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000087 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63337.984476 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63337.984476 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63942.339483 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63942.339483 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63690.768982 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 63690.768982 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63690.768982 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 63690.768982 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68623.722222 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68623.722222 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68082.558442 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68082.558442 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68308.725162 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68308.725162 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68308.725162 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68308.725162 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 06f12379e..003c2ae7a 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,97 +1,99 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.144337 # Number of seconds simulated -sim_ticks 144337151000 # Number of ticks simulated -final_tick 144337151000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.144463 # Number of seconds simulated +sim_ticks 144463317000 # Number of ticks simulated +final_tick 144463317000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71990 # Simulator instruction rate (inst/s) -host_op_rate 120663 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 78676444 # Simulator tick rate (ticks/s) -host_mem_usage 280564 # Number of bytes of host memory used -host_seconds 1834.57 # Real time elapsed on the host +host_inst_rate 66822 # Simulator instruction rate (inst/s) +host_op_rate 111999 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 73091533 # Simulator tick rate (ticks/s) +host_mem_usage 308580 # Number of bytes of host memory used +host_seconds 1976.47 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 217984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125184 # Number of bytes read from this memory -system.physmem.bytes_read::total 343168 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 217984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 217984 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3406 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1956 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5362 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1510242 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 867303 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2377545 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1510242 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1510242 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1510242 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 867303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2377545 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5363 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 5363 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 343168 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 343168 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 155 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 287 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 360 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 449 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 361 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 329 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 326 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 396 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 379 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 340 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 277 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 230 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 279 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 206 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 469 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 390 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 285 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 144337117000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 5363 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 4337 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 861 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 143 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.bytes_read::cpu.inst 217088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125568 # Number of bytes read from this memory +system.physmem.bytes_read::total 342656 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 217088 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 217088 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3392 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1962 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5354 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1502721 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 869203 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2371924 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1502721 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1502721 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1502721 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 869203 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2371924 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5354 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 5354 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 342656 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 342656 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 163 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 289 # Per bank write bursts +system.physmem.perBankRdBursts::1 357 # Per bank write bursts +system.physmem.perBankRdBursts::2 453 # Per bank write bursts +system.physmem.perBankRdBursts::3 356 # Per bank write bursts +system.physmem.perBankRdBursts::4 332 # Per bank write bursts +system.physmem.perBankRdBursts::5 326 # Per bank write bursts +system.physmem.perBankRdBursts::6 402 # Per bank write bursts +system.physmem.perBankRdBursts::7 377 # Per bank write bursts +system.physmem.perBankRdBursts::8 341 # Per bank write bursts +system.physmem.perBankRdBursts::9 276 # Per bank write bursts +system.physmem.perBankRdBursts::10 232 # Per bank write bursts +system.physmem.perBankRdBursts::11 277 # Per bank write bursts +system.physmem.perBankRdBursts::12 205 # Per bank write bursts +system.physmem.perBankRdBursts::13 465 # Per bank write bursts +system.physmem.perBankRdBursts::14 384 # Per bank write bursts +system.physmem.perBankRdBursts::15 282 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 144463266500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 5354 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 4302 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 874 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 155 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -150,350 +152,344 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 502 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 668.557769 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 237.238454 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1295.396575 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 170 33.86% 33.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 76 15.14% 49.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 42 8.37% 57.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 23 4.58% 61.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 26 5.18% 67.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 11 2.19% 69.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 16 3.19% 72.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 9 1.79% 74.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 9 1.79% 76.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 7 1.39% 77.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 3 0.60% 78.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 8 1.59% 79.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 5 1.00% 80.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 3 0.60% 81.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 4 0.80% 82.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 5 1.00% 83.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 4 0.80% 83.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 5 1.00% 84.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 2 0.40% 85.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 2 0.40% 85.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 3 0.60% 86.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 5 1.00% 87.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 3 0.60% 87.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 1 0.20% 88.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 2 0.40% 88.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 1 0.20% 88.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 1 0.20% 88.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 2 0.40% 89.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 4 0.80% 90.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 4 0.80% 90.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 1 0.20% 91.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 2 0.40% 91.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 1 0.20% 91.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 4 0.80% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.20% 92.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 2 0.40% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 2 0.40% 93.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.20% 93.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 1 0.20% 93.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 5 1.00% 94.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 1 0.20% 95.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.20% 95.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 1 0.20% 95.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.20% 95.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 1 0.20% 95.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 2 0.40% 96.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 1 0.20% 96.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 1 0.20% 96.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 1 0.20% 96.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 2 0.40% 97.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 1 0.20% 97.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 1 0.20% 97.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 1 0.20% 97.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.20% 98.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.20% 98.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 1 0.20% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 1 0.20% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 1 0.20% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 1 0.20% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 5 1.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 502 # Bytes accessed per row activation -system.physmem.totQLat 12694000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 119204000 # Sum of mem lat for all requests -system.physmem.totBusLat 26815000 # Total cycles spent in databus access -system.physmem.totBankLat 79695000 # Total cycles spent in bank access -system.physmem.avgQLat 2366.96 # Average queueing delay per request -system.physmem.avgBankLat 14860.15 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22227.11 # Average memory access latency -system.physmem.avgRdBW 2.38 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2.38 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.bytesPerActivate::samples 957 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 353.103448 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 172.307957 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 612.115437 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 385 40.23% 40.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 164 17.14% 57.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 81 8.46% 65.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 46 4.81% 70.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 43 4.49% 75.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 20 2.09% 77.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 26 2.72% 79.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 19 1.99% 81.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 17 1.78% 83.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 26 2.72% 86.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 27 2.82% 89.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 7 0.73% 89.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 7 0.73% 90.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 7 0.73% 91.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 3 0.31% 91.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 5 0.52% 92.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 6 0.63% 92.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 6 0.63% 93.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 4 0.42% 93.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 2 0.21% 94.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 2 0.21% 94.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408 3 0.31% 94.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472 7 0.73% 95.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 1 0.10% 95.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 5 0.52% 96.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 4 0.42% 96.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728 2 0.21% 96.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792 2 0.21% 96.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 2 0.21% 97.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 3 0.31% 97.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984 2 0.21% 97.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112 1 0.10% 97.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176 1 0.10% 97.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240 1 0.10% 97.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304 1 0.10% 98.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 1 0.10% 98.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 2 0.21% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496 1 0.10% 98.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816 2 0.21% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880 3 0.31% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072 1 0.10% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328 1 0.10% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456 1 0.10% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584 1 0.10% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160 1 0.10% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352 1 0.10% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736 1 0.10% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312 1 0.10% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696 1 0.10% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952 1 0.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 957 # Bytes accessed per row activation +system.physmem.totQLat 28805000 # Total ticks spent queuing +system.physmem.totMemAccLat 137868750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26770000 # Total ticks spent in databus transfers +system.physmem.totBankLat 82293750 # Total ticks spent accessing banks +system.physmem.avgQLat 5380.09 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 15370.52 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 25750.61 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.37 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.37 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4861 # Number of row buffer hits during reads +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 4397 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.64 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.13 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 26913503.08 # Average gap between requests -system.membus.throughput 2376658 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 3834 # Transaction distribution -system.membus.trans_dist::ReadResp 3831 # Transaction distribution -system.membus.trans_dist::UpgradeReq 155 # Transaction distribution -system.membus.trans_dist::UpgradeResp 155 # Transaction distribution -system.membus.trans_dist::ReadExReq 1529 # Transaction distribution -system.membus.trans_dist::ReadExResp 1529 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11033 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11033 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11033 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 343040 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 343040 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 343040 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 343040 # Total data (bytes) +system.physmem.avgGap 26982306.03 # Average gap between requests +system.physmem.pageHitRate 82.13 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.41 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 2371924 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3822 # Transaction distribution +system.membus.trans_dist::ReadResp 3822 # Transaction distribution +system.membus.trans_dist::UpgradeReq 163 # Transaction distribution +system.membus.trans_dist::UpgradeResp 163 # Transaction distribution +system.membus.trans_dist::ReadExReq 1532 # Transaction distribution +system.membus.trans_dist::ReadExResp 1532 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11034 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11034 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11034 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 342656 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 342656 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 342656 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 342656 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6990500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6948500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 50919845 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 50662837 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 18643050 # Number of BP lookups -system.cpu.branchPred.condPredicted 18643050 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1490032 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11410312 # Number of BTB lookups -system.cpu.branchPred.BTBHits 10785938 # Number of BTB hits +system.cpu.branchPred.lookups 18648234 # Number of BP lookups +system.cpu.branchPred.condPredicted 18648234 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1490176 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11407549 # Number of BTB lookups +system.cpu.branchPred.BTBHits 10790529 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.527985 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1319504 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 23183 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.591126 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1320367 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 22841 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 288958646 # number of cpu cycles simulated +system.cpu.numCycles 289221873 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 23449793 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 206693394 # Number of instructions fetch has processed -system.cpu.fetch.Branches 18643050 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 12105442 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 54202287 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 15520872 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 177854529 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1763 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 10399 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22344441 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 223502 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 269290652 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.269559 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.757534 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 23458037 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 206724223 # Number of instructions fetch has processed +system.cpu.fetch.Branches 18648234 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 12110896 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 54209099 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 15518775 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 178161359 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1571 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9111 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 38 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22353213 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 224062 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 269612466 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.268180 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.756310 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 216527015 80.41% 80.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2848467 1.06% 81.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2311919 0.86% 82.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2635920 0.98% 83.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3216253 1.19% 84.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3385278 1.26% 85.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3830479 1.42% 87.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2556488 0.95% 88.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 31978833 11.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 216842558 80.43% 80.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2848142 1.06% 81.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2312056 0.86% 82.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2633842 0.98% 83.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3218714 1.19% 84.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3388946 1.26% 85.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3831195 1.42% 87.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2559437 0.95% 88.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 31977576 11.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 269290652 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.064518 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.715304 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36876732 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 166835033 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 41579230 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10227851 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 13771806 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 335978387 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 13771806 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 44930878 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 116570981 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 32723 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 42705730 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 51278534 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 329616672 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 10920 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 26000838 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22678371 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 382329896 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 917574751 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 605864950 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4114395 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 269612466 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.064477 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.714760 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 36899349 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 167130008 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 41545231 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10264627 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 13773251 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 336001478 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 13773251 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 44972476 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 116686700 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 32545 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 42701692 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 51445802 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 329633797 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 10827 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 26123597 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22730551 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 382342114 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 917586762 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 605878307 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4127660 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 122900446 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2069 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2059 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 104883314 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 84491871 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 30099442 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 58238426 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 18921052 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 322680314 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4268 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 260554870 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 118520 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 100937084 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 209936848 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3023 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 269290652 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.967560 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.344979 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 122912664 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2051 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2042 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 105140053 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 84507278 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 30107186 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 58355212 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 18979888 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 322730912 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4069 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 260501997 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 116055 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 100987198 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 210203666 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2824 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 269612466 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.966209 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.343680 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 143216818 53.18% 53.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55391998 20.57% 73.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34136198 12.68% 86.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 19056794 7.08% 93.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10890991 4.04% 97.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4174838 1.55% 99.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1812713 0.67% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 476754 0.18% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 133548 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 143429906 53.20% 53.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 55567349 20.61% 73.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 34108146 12.65% 86.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19044984 7.06% 93.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10887633 4.04% 97.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4152281 1.54% 99.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1816698 0.67% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 472473 0.18% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 132996 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 269290652 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 269612466 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 129591 4.77% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2286947 84.14% 88.91% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 301448 11.09% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 130605 4.82% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2279077 84.03% 88.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 302412 11.15% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1210947 0.46% 0.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 162062878 62.20% 62.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 788601 0.30% 62.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7035610 2.70% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1446949 0.56% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 65458486 25.12% 91.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 22551399 8.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1210810 0.46% 0.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 162055945 62.21% 62.67% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 789191 0.30% 62.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7035649 2.70% 65.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1445882 0.56% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 65414515 25.11% 91.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 22550005 8.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 260554870 # Type of FU issued -system.cpu.iq.rate 0.901703 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2717986 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010432 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 788349666 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 420314195 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 255192215 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4887232 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 3589351 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2349681 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 259602195 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2459714 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18922795 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 260501997 # Type of FU issued +system.cpu.iq.rate 0.900700 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2712094 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010411 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 788557581 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 420384882 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 255147074 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4887028 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 3615221 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2349564 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 259544029 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2459252 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18903383 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 27842284 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 26598 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 287421 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 9583725 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 27857691 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 25993 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 283319 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 9591469 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 49875 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 33 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 49752 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 13771806 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 85094278 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5458618 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 322684582 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 133416 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 84491871 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 30099442 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2045 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2689502 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13828 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 287421 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 641114 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 899581 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1540695 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 258780631 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 64687698 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1774239 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 13773251 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 85040641 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5471570 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 322734981 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 133239 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 84507278 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 30107186 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1979 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2708196 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 13910 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 283319 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 639398 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 901241 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1540639 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 258732431 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 64645019 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1769566 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 87035316 # number of memory reference insts executed -system.cpu.iew.exec_branches 14266808 # Number of branches executed -system.cpu.iew.exec_stores 22347618 # Number of stores executed -system.cpu.iew.exec_rate 0.895563 # Inst execution rate -system.cpu.iew.wb_sent 258140972 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 257541896 # cumulative count of insts written-back -system.cpu.iew.wb_producers 206006775 # num instructions producing a value -system.cpu.iew.wb_consumers 369206880 # num instructions consuming a value +system.cpu.iew.exec_refs 86992194 # number of memory reference insts executed +system.cpu.iew.exec_branches 14265860 # Number of branches executed +system.cpu.iew.exec_stores 22347175 # Number of stores executed +system.cpu.iew.exec_rate 0.894581 # Inst execution rate +system.cpu.iew.wb_sent 258096694 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 257496638 # cumulative count of insts written-back +system.cpu.iew.wb_producers 205928299 # num instructions producing a value +system.cpu.iew.wb_consumers 369130532 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.891276 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.557971 # average fanout of values written-back +system.cpu.iew.wb_rate 0.890308 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.557874 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 101393363 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 101448847 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1491544 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 255518846 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.866329 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.656611 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1491529 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 255839215 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.865244 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.654327 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 156315405 61.18% 61.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57071451 22.34% 83.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14008929 5.48% 88.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12048531 4.72% 93.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4172668 1.63% 95.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2970306 1.16% 96.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 908783 0.36% 96.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1048602 0.41% 97.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6974171 2.73% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 156486613 61.17% 61.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57197635 22.36% 83.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14067876 5.50% 89.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12054069 4.71% 93.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4176262 1.63% 95.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2944385 1.15% 96.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 904563 0.35% 96.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1049057 0.41% 97.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6958755 2.72% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 255518846 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 255839215 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -504,224 +500,222 @@ system.cpu.commit.branches 12326938 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 219019985 # Number of committed integer instructions. system.cpu.commit.function_calls 797818 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6974171 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6958755 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 571301422 # The number of ROB reads -system.cpu.rob.rob_writes 659310799 # The number of ROB writes -system.cpu.timesIdled 5931788 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19667994 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 571692691 # The number of ROB reads +system.cpu.rob.rob_writes 659422929 # The number of ROB writes +system.cpu.timesIdled 5933064 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19609407 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated -system.cpu.cpi 2.187901 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.187901 # CPI: Total CPI of All Threads -system.cpu.ipc 0.457059 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.457059 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 451358394 # number of integer regfile reads -system.cpu.int_regfile_writes 233998694 # number of integer regfile writes -system.cpu.fp_regfile_reads 3217923 # number of floating regfile reads -system.cpu.fp_regfile_writes 2009376 # number of floating regfile writes -system.cpu.cc_regfile_reads 102822009 # number of cc regfile reads -system.cpu.cc_regfile_writes 59823089 # number of cc regfile writes -system.cpu.misc_regfile_reads 133360573 # number of misc regfile reads +system.cpu.cpi 2.189894 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.189894 # CPI: Total CPI of All Threads +system.cpu.ipc 0.456643 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.456643 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 451224157 # number of integer regfile reads +system.cpu.int_regfile_writes 233957254 # number of integer regfile writes +system.cpu.fp_regfile_reads 3215586 # number of floating regfile reads +system.cpu.fp_regfile_writes 2009211 # number of floating regfile writes +system.cpu.cc_regfile_reads 102809518 # number of cc regfile reads +system.cpu.cc_regfile_writes 59799385 # number of cc regfile writes +system.cpu.misc_regfile_reads 133324418 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.toL2Bus.throughput 3892220 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7233 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7229 # Transaction distribution +system.cpu.toL2Bus.throughput 3898568 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7250 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7248 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 13 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 156 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 156 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1536 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1536 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13381 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4322 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 17703 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 423168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 551808 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 551808 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 9984 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4482000 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::UpgradeReq 163 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 163 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1539 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1539 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13403 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4348 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 17751 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 423616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 552704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 552704 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 10496 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4495500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 10834750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 10760250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3517155 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3467413 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 4647 # number of replacements -system.cpu.icache.tags.tagsinuse 1626.526476 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22335618 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6612 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3378.042650 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 4653 # number of replacements +system.cpu.icache.tags.tagsinuse 1619.938452 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22344301 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6620 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3375.272054 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1626.526476 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.794202 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.794202 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 22335618 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22335618 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22335618 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22335618 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22335618 # number of overall hits -system.cpu.icache.overall_hits::total 22335618 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8823 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8823 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8823 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8823 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8823 # number of overall misses -system.cpu.icache.overall_misses::total 8823 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 352032500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 352032500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 352032500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 352032500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 352032500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 352032500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22344441 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22344441 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22344441 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22344441 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22344441 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22344441 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000395 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000395 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000395 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000395 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000395 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000395 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39899.410631 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 39899.410631 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 39899.410631 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 39899.410631 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 39899.410631 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 39899.410631 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 978 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1619.938452 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.790986 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.790986 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 22344301 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22344301 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22344301 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22344301 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22344301 # number of overall hits +system.cpu.icache.overall_hits::total 22344301 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8911 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8911 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8911 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8911 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8911 # number of overall misses +system.cpu.icache.overall_misses::total 8911 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 368225749 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 368225749 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 368225749 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 368225749 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 368225749 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 368225749 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22353212 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22353212 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22353212 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22353212 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22353212 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22353212 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000399 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000399 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000399 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000399 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000399 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000399 # 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number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -730,166 +724,166 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3407 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 428 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3835 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 155 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 155 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1529 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1529 # 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mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.541896 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.993590 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.993590 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995443 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995443 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.515197 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.978500 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.622780 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.515197 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.978500 # 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number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 84874000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 84874000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 189922000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 112300500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 302222500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 189922000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 112300500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 302222500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.512538 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.922747 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.539515 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995452 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995452 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.512538 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.978554 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.620870 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.512538 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.978554 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.620870 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55974.653699 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63782.558140 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56852.864243 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50409.090909 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50409.090909 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53106.251834 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52509.197752 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52888.422819 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53106.251834 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52509.197752 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52888.422819 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55400.783290 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55400.783290 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55974.653699 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57237.767584 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56437.441643 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55974.653699 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57237.767584 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56437.441643 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 54 # number of replacements -system.cpu.dcache.tags.tagsinuse 1431.071380 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 66125331 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1997 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33112.334001 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 57 # number of replacements +system.cpu.dcache.tags.tagsinuse 1438.861304 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 66102355 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2004 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 32985.207086 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1431.071380 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.349383 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.349383 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 45611085 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 45611085 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20514038 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20514038 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 66125123 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 66125123 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 66125123 # number of overall hits -system.cpu.dcache.overall_hits::total 66125123 # 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number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 161256457 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 161256457 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 161256457 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 45612000 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 45612000 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 1438.861304 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.351284 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.351284 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 45588096 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 45588096 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20514029 # 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number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 66127731 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 66127731 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 66127731 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 66127731 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 66104762 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 66104762 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 66104762 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 66104762 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000083 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000083 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000039 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000039 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000039 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000039 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60300.876503 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60300.876503 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62658.685765 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62658.685765 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61831.463574 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61831.463574 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61831.463574 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61831.463574 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 351 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.000040 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000040 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000040 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000040 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67126.809626 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67126.809626 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66925.477673 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66925.477673 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 66996.863860 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66996.863860 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 66996.863860 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66996.863860 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 87.750000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 77 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 13 # number of writebacks system.cpu.dcache.writebacks::total 13 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 450 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 450 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 452 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 452 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 452 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 452 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 465 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 465 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1691 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1691 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2156 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2156 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2156 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2156 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31924750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 31924750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 101851095 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 101851095 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 133775845 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 133775845 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 133775845 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 133775845 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 468 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 468 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 469 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 469 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 469 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 469 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 467 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1701 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1701 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2168 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2168 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2168 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2168 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33590500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33590500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 109769587 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 109769587 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 143360087 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 143360087 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 143360087 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 143360087 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000082 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000082 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000083 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000083 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000033 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000033 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68655.376344 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68655.376344 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60231.280308 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60231.280308 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62048.165584 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 62048.165584 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62048.165584 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 62048.165584 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71928.265525 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71928.265525 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64532.385068 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64532.385068 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66125.501384 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66125.501384 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66125.501384 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66125.501384 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |