diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-04-09 12:13:40 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-04-09 12:13:40 -0400 |
| commit | d9193d1b2039739ef4fb264c742d37f9803817e5 (patch) | |
| tree | 7904829173102a8d8f654873d5cefb790e148298 /tests/long/se/70.twolf | |
| parent | 1d61224a8ba60a2c8cb06e9877b7e548d47bb99a (diff) | |
| download | gem5-d9193d1b2039739ef4fb264c742d37f9803817e5.tar.xz | |
stats: Match current behaviour
Small changes to the branch predictor and BTB caused stats changes
throughout.
Diffstat (limited to 'tests/long/se/70.twolf')
5 files changed, 2966 insertions, 2874 deletions
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index 8b18f9604..6eb6b8f50 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.051911 # Number of seconds simulated -sim_ticks 51910606500 # Number of ticks simulated -final_tick 51910606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.051906 # Number of seconds simulated +sim_ticks 51905634500 # Number of ticks simulated +final_tick 51905634500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 362776 # Simulator instruction rate (inst/s) -host_op_rate 362776 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 204910533 # Simulator tick rate (ticks/s) -host_mem_usage 303308 # Number of bytes of host memory used -host_seconds 253.33 # Real time elapsed on the host +host_inst_rate 327219 # Simulator instruction rate (inst/s) +host_op_rate 327219 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 184808729 # Simulator tick rate (ticks/s) +host_mem_usage 257300 # Number of bytes of host memory used +host_seconds 280.86 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 202752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 202816 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 137664 # Number of bytes read from this memory -system.physmem.bytes_read::total 340416 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 202752 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 202752 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3168 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 340480 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 202816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 202816 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3169 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2151 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5319 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3905791 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2651944 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6557735 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3905791 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3905791 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3905791 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2651944 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6557735 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5319 # Number of read requests accepted +system.physmem.num_reads::total 5320 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 3907399 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2652198 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6559596 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3907399 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3907399 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3907399 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2652198 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6559596 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5320 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5319 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5320 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 340416 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 340480 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 340416 # Total read bytes from the system interface side +system.physmem.bytesReadSys 340480 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -49,7 +49,7 @@ system.physmem.perBankRdBursts::4 224 # Pe system.physmem.perBankRdBursts::5 238 # Per bank write bursts system.physmem.perBankRdBursts::6 222 # Per bank write bursts system.physmem.perBankRdBursts::7 289 # Per bank write bursts -system.physmem.perBankRdBursts::8 251 # Per bank write bursts +system.physmem.perBankRdBursts::8 252 # Per bank write bursts system.physmem.perBankRdBursts::9 282 # Per bank write bursts system.physmem.perBankRdBursts::10 254 # Per bank write bursts system.physmem.perBankRdBursts::11 261 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 51910519000 # Total gap between requests +system.physmem.totGap 51905547000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5319 # Read request sizes (log2) +system.physmem.readPktSize::6 5320 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4921 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4923 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 378 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 979 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 346.541369 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 213.036393 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 328.369108 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 309 31.56% 31.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 207 21.14% 52.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 105 10.73% 63.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 89 9.09% 72.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 71 7.25% 79.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 31 3.17% 82.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 27 2.76% 85.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 27 2.76% 88.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 113 11.54% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 979 # Bytes accessed per row activation -system.physmem.totQLat 35329750 # Total ticks spent queuing -system.physmem.totMemAccLat 135061000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26595000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6642.18 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 982 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 346.395112 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 212.989816 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 328.326928 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 308 31.36% 31.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 213 21.69% 53.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 101 10.29% 63.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 90 9.16% 72.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 71 7.23% 79.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 37 3.77% 83.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 21 2.14% 85.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 29 2.95% 88.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 112 11.41% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 982 # Bytes accessed per row activation +system.physmem.totQLat 32661000 # Total ticks spent queuing +system.physmem.totMemAccLat 132411000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26600000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6139.29 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25392.18 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24889.29 # Average memory access latency per DRAM burst system.physmem.avgRdBW 6.56 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 6.56 # Average system read bandwidth in MiByte/s @@ -216,70 +216,74 @@ system.physmem.busUtilRead 0.05 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4332 # Number of row buffer hits during reads +system.physmem.readRowHits 4334 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.44 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.47 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9759450.84 # Average gap between requests -system.physmem.pageHitRate 81.44 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3507840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1914000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 19835400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 9756681.77 # Average gap between requests +system.physmem.pageHitRate 81.47 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3515400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1918125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 19983600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 3390060960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1735573905 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29619608250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34770500355 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.907919 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49271583750 # Time in different power states +system.physmem_0.actBackEnergy 1736098875 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29619147750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34770724710 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.912241 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49270880000 # Time in different power states system.physmem_0.memoryStateTime::REF 1733160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 898672500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 899376250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3848040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2099625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 21216000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3885840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2120250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 21309600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 3390060960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1825260840 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29540935500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34783420965 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.156855 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49142724000 # Time in different power states +system.physmem_1.actBackEnergy 1812535875 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29552097750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34782010275 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.129676 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49159142250 # Time in different power states system.physmem_1.memoryStateTime::REF 1733160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1030067000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1011440250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 11441088 # Number of BP lookups -system.cpu.branchPred.condPredicted 8207826 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 765853 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 6077536 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5340604 # Number of BTB hits +system.cpu.branchPred.lookups 11440185 # Number of BP lookups +system.cpu.branchPred.condPredicted 8207191 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 765027 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 6076858 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5316207 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.874494 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1173808 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 87.482824 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1173724 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 26312 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 24255 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 2057 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 983 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20417089 # DTB read hits -system.cpu.dtb.read_misses 43350 # DTB read misses +system.cpu.dtb.read_hits 20416195 # DTB read hits +system.cpu.dtb.read_misses 43360 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20460439 # DTB read accesses -system.cpu.dtb.write_hits 6579898 # DTB write hits +system.cpu.dtb.read_accesses 20459555 # DTB read accesses +system.cpu.dtb.write_hits 6579893 # DTB write hits system.cpu.dtb.write_misses 278 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6580176 # DTB write accesses -system.cpu.dtb.data_hits 26996987 # DTB hits -system.cpu.dtb.data_misses 43628 # DTB misses +system.cpu.dtb.write_accesses 6580171 # DTB write accesses +system.cpu.dtb.data_hits 26996088 # DTB hits +system.cpu.dtb.data_misses 43638 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 27040615 # DTB accesses -system.cpu.itb.fetch_hits 22953519 # ITB hits +system.cpu.dtb.data_accesses 27039726 # DTB accesses +system.cpu.itb.fetch_hits 22951506 # ITB hits system.cpu.itb.fetch_misses 90 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 22953609 # ITB accesses +system.cpu.itb.fetch_accesses 22951596 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,26 +297,61 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 103821213 # number of cpu cycles simulated +system.cpu.numCycles 103811269 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 91903089 # Number of instructions committed system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2183676 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2181586 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.129681 # CPI: cycles per instruction -system.cpu.ipc 0.885205 # IPC: instructions per cycle -system.cpu.tickCycles 102104321 # Number of cycles that the object actually ticked -system.cpu.idleCycles 1716892 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.129573 # CPI: cycles per instruction +system.cpu.ipc 0.885290 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 7723353 8.40% 8.40% # Class of committed instruction +system.cpu.op_class_0::IntAlu 51001454 55.49% 63.90% # Class of committed instruction +system.cpu.op_class_0::IntMult 458252 0.50% 64.40% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 64.40% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 2732553 2.97% 67.37% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 104605 0.11% 67.48% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 2333953 2.54% 70.02% # Class of committed instruction +system.cpu.op_class_0::FloatMult 296445 0.32% 70.35% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 754822 0.82% 71.17% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 318 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::MemRead 19996208 21.76% 92.93% # Class of committed instruction +system.cpu.op_class_0::MemWrite 6501126 7.07% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 91903089 # Class of committed instruction +system.cpu.tickCycles 102098443 # Number of cycles that the object actually ticked +system.cpu.idleCycles 1712826 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1447.424803 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26573200 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1447.414267 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26572424 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11916.233184 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11915.885202 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1447.424803 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.353375 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.353375 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1447.414267 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.353373 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.353373 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id @@ -320,56 +359,56 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 227 system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1379 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 53155492 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 53155492 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20075007 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20075007 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6498193 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6498193 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26573200 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26573200 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26573200 # number of overall hits -system.cpu.dcache.overall_hits::total 26573200 # number of overall hits +system.cpu.dcache.tags.tag_accesses 53153936 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 53153936 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20074229 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20074229 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6498195 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6498195 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26572424 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26572424 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26572424 # number of overall hits +system.cpu.dcache.overall_hits::total 26572424 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 521 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 521 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2910 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2910 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3431 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3431 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3431 # number of overall misses -system.cpu.dcache.overall_misses::total 3431 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 40212500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 40212500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 214034000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 214034000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 254246500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 254246500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 254246500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 254246500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20075528 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20075528 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 2908 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2908 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3429 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3429 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3429 # number of overall misses +system.cpu.dcache.overall_misses::total 3429 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 40464500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 40464500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 214055500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 214055500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 254520000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 254520000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 254520000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 254520000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20074750 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20074750 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 26576631 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 26576631 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 26576631 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 26576631 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 26575853 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26575853 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 26575853 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26575853 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000448 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000448 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000447 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000447 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000129 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000129 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77183.301344 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 77183.301344 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73551.202749 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73551.202749 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 74102.739726 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 74102.739726 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 74102.739726 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 74102.739726 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77666.986564 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 77666.986564 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73609.181568 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73609.181568 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 74225.721785 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 74225.721785 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 74225.721785 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 74225.721785 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,12 +421,12 @@ system.cpu.dcache.writebacks::writebacks 107 # nu system.cpu.dcache.writebacks::total 107 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 36 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 36 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1165 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1165 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1201 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1201 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1201 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1201 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1163 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1163 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1199 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1199 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1199 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1199 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 485 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 485 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1745 # number of WriteReq MSHR misses @@ -396,14 +435,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2230 system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2230 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37107000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 37107000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131706500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 131706500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 168813500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 168813500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 168813500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 168813500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36953000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36953000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131397000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 131397000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 168350000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 168350000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 168350000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 168350000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses @@ -412,69 +451,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76509.278351 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76509.278351 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75476.504298 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75476.504298 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75701.121076 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75701.121076 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75701.121076 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75701.121076 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76191.752577 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76191.752577 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75299.140401 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75299.140401 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75493.273543 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75493.273543 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75493.273543 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75493.273543 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 13850 # number of replacements -system.cpu.icache.tags.tagsinuse 1640.456655 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22937703 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15815 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1450.376415 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 13853 # number of replacements +system.cpu.icache.tags.tagsinuse 1642.330146 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22935687 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15818 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1449.973891 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1640.456655 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.801004 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.801004 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1642.330146 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.801919 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.801919 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 671 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 672 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 150 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 946 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45922853 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45922853 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 22937703 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22937703 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22937703 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22937703 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22937703 # number of overall hits -system.cpu.icache.overall_hits::total 22937703 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 15816 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 15816 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 15816 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 15816 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 15816 # number of overall misses -system.cpu.icache.overall_misses::total 15816 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 408931500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 408931500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 408931500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 408931500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 408931500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 408931500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22953519 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22953519 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22953519 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22953519 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22953519 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22953519 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 45918830 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45918830 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 22935687 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22935687 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22935687 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22935687 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22935687 # number of overall hits +system.cpu.icache.overall_hits::total 22935687 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 15819 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 15819 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 15819 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 15819 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 15819 # number of overall misses +system.cpu.icache.overall_misses::total 15819 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 406827000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 406827000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 406827000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 406827000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 406827000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 406827000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22951506 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22951506 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22951506 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22951506 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22951506 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22951506 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000689 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000689 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000689 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000689 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000689 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000689 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25855.557663 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25855.557663 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25855.557663 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25855.557663 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25855.557663 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25855.557663 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25717.618054 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25717.618054 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25717.618054 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25717.618054 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25717.618054 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25717.618054 # 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average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24855.620890 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 24855.620890 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24717.681269 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24717.681269 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24717.681269 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24717.681269 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24717.681269 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24717.681269 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # 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Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 770 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 183 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2505 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.111877 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 261827 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 261827 # Number of data accesses +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2507 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.111908 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 261876 # 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number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 234465500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 164169000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 398634500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 234465500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 164169000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 398634500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 107 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 107 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 13850 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 13850 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 13853 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 13853 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1745 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1745 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15815 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 15815 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15818 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 15818 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 485 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 485 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 15815 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 15818 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 2230 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 18045 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 15815 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 18048 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 15818 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2230 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 18045 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 18048 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985100 # 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miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200316 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.294770 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200341 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964574 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.294763 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74936.591041 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74936.591041 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74683.869949 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74683.869949 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82909.722222 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82909.722222 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74683.869949 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76537.889354 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75433.634142 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74683.869949 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76537.889354 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75433.634142 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.294770 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74756.253636 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74756.253636 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73987.219943 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73987.219943 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82553.240741 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82553.240741 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73987.219943 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76322.175732 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74931.296992 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73987.219943 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76322.175732 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74931.296992 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -622,113 +661,113 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1719 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1719 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3168 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3168 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3169 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3169 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 432 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 432 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3168 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3169 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 2151 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5319 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3168 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5320 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3169 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2151 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5319 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 111626000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 111626000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 204918500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 204918500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31497000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31497000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 204918500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 143123000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 348041500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 204918500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 143123000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 348041500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 5320 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 111316000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 111316000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 202775500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 202775500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31343000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31343000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 202775500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 142659000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 345434500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 202775500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 142659000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 345434500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985100 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985100 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.200316 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.200316 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.200341 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.200341 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.890722 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.890722 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200316 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200341 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.294763 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200316 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.294770 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200341 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.294763 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64936.591041 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64936.591041 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64683.869949 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64683.869949 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72909.722222 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72909.722222 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64683.869949 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66537.889354 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65433.634142 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64683.869949 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66537.889354 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65433.634142 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.294770 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64756.253636 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64756.253636 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63987.219943 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63987.219943 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72553.240741 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72553.240741 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63987.219943 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66322.175732 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64931.296992 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63987.219943 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66322.175732 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64931.296992 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 32052 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 14007 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 32058 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 14010 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 16300 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 16303 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 13850 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 13853 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1745 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1745 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 15815 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 15818 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 485 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45480 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45489 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4617 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 50097 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1898560 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 50106 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1898944 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2048128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2048512 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 18045 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 18048 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 18045 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 18048 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 18045 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 29983000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 18048 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 29989000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 23722500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 23727000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3345000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3600 # Transaction distribution +system.membus.trans_dist::ReadResp 3601 # Transaction distribution system.membus.trans_dist::ReadExReq 1719 # Transaction distribution system.membus.trans_dist::ReadExResp 1719 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3600 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10638 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10638 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340416 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 340416 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 3601 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10640 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10640 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 340480 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5319 # Request fanout histogram +system.membus.snoop_fanout::samples 5320 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5319 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5320 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5319 # Request fanout histogram -system.membus.reqLayer0.occupancy 6412500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5320 # Request fanout histogram +system.membus.reqLayer0.occupancy 6419000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 28165250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 28167750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 5f230123f..5ce51dae8 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,48 +1,48 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.021917 # Number of seconds simulated -sim_ticks 21916940500 # Number of ticks simulated -final_tick 21916940500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.021909 # Number of seconds simulated +sim_ticks 21909208500 # Number of ticks simulated +final_tick 21909208500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 209109 # Simulator instruction rate (inst/s) -host_op_rate 209109 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54443336 # Simulator tick rate (ticks/s) -host_mem_usage 303052 # Number of bytes of host memory used -host_seconds 402.56 # Real time elapsed on the host +host_inst_rate 236201 # Simulator instruction rate (inst/s) +host_op_rate 236201 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61475451 # Simulator tick rate (ticks/s) +host_mem_usage 258056 # Number of bytes of host memory used +host_seconds 356.39 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 195712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138496 # Number of bytes read from this memory -system.physmem.bytes_read::total 334208 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 195712 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 195712 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3058 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2164 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5222 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8929714 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6319130 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15248844 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8929714 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8929714 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8929714 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6319130 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15248844 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5222 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 195968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138560 # Number of bytes read from this memory +system.physmem.bytes_read::total 334528 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 195968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 195968 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3062 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2165 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5227 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8944550 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6324281 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15268831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8944550 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8944550 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8944550 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6324281 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15268831 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5227 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5222 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5227 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 334208 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 334528 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 334208 # Total read bytes from the system interface side +system.physmem.bytesReadSys 334528 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 470 # Per bank write bursts -system.physmem.perBankRdBursts::1 290 # Per bank write bursts +system.physmem.perBankRdBursts::1 291 # Per bank write bursts system.physmem.perBankRdBursts::2 302 # Per bank write bursts system.physmem.perBankRdBursts::3 523 # Per bank write bursts system.physmem.perBankRdBursts::4 220 # Per bank write bursts @@ -50,12 +50,12 @@ system.physmem.perBankRdBursts::5 223 # Pe system.physmem.perBankRdBursts::6 218 # Per bank write bursts system.physmem.perBankRdBursts::7 288 # Per bank write bursts system.physmem.perBankRdBursts::8 239 # Per bank write bursts -system.physmem.perBankRdBursts::9 277 # Per bank write bursts +system.physmem.perBankRdBursts::9 278 # Per bank write bursts system.physmem.perBankRdBursts::10 249 # Per bank write bursts system.physmem.perBankRdBursts::11 251 # Per bank write bursts -system.physmem.perBankRdBursts::12 396 # Per bank write bursts -system.physmem.perBankRdBursts::13 338 # Per bank write bursts -system.physmem.perBankRdBursts::14 489 # Per bank write bursts +system.physmem.perBankRdBursts::12 395 # Per bank write bursts +system.physmem.perBankRdBursts::13 339 # Per bank write bursts +system.physmem.perBankRdBursts::14 492 # Per bank write bursts system.physmem.perBankRdBursts::15 449 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21916845500 # Total gap between requests +system.physmem.totGap 21909113500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5222 # Read request sizes (log2) +system.physmem.readPktSize::6 5227 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,12 +90,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3268 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1190 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 509 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3269 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 507 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 232 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 859 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 386.235157 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 231.364931 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 358.000658 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 253 29.45% 29.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 187 21.77% 51.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 82 9.55% 60.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 62 7.22% 67.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 35 4.07% 72.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 38 4.42% 76.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 35 4.07% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 43 5.01% 85.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 124 14.44% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 859 # Bytes accessed per row activation -system.physmem.totQLat 43137250 # Total ticks spent queuing -system.physmem.totMemAccLat 141049750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26110000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8260.68 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 857 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 387.435239 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 233.348968 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 357.138574 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 246 28.70% 28.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 186 21.70% 50.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 85 9.92% 60.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 65 7.58% 67.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 37 4.32% 72.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 35 4.08% 76.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 34 3.97% 80.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 49 5.72% 86.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 120 14.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 857 # Bytes accessed per row activation +system.physmem.totQLat 42496500 # Total ticks spent queuing +system.physmem.totMemAccLat 140502750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26135000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8130.19 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27010.68 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 15.25 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26880.19 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 15.27 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 15.25 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 15.27 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.12 # Data bus utilization in percentage @@ -216,70 +216,74 @@ system.physmem.busUtilRead 0.12 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4353 # Number of row buffer hits during reads +system.physmem.readRowHits 4359 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.36 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.39 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4197021.35 # Average gap between requests -system.physmem.pageHitRate 83.36 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3122280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1703625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 19461000 # Energy for read commands per rank (pJ) +system.physmem.avgGap 4191527.36 # Average gap between requests +system.physmem.pageHitRate 83.39 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3076920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1678875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 19468800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1431087840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 912284145 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 12346211250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14713870140 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.536045 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 20536521000 # Time in different power states -system.physmem_0.memoryStateTime::REF 731640000 # Time in different power states +system.physmem_0.refreshEnergy 1430579280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 930163050 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 12325856250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14710823175 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.635656 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 20502630500 # Time in different power states +system.physmem_0.memoryStateTime::REF 731380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 642620250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 668984500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3311280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1806750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 20748000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3341520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1823250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 20771400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1431087840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 917766405 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 12341402250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 14716122525 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.638843 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 20529652250 # Time in different power states -system.physmem_1.memoryStateTime::REF 731640000 # Time in different power states +system.physmem_1.refreshEnergy 1430579280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 904676355 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 12348213000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14709404805 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.570899 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 20540502500 # Time in different power states +system.physmem_1.memoryStateTime::REF 731380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 650829750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 632027000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 16111441 # Number of BP lookups -system.cpu.branchPred.condPredicted 11701383 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 926235 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8627871 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7529688 # Number of BTB hits +system.cpu.branchPred.lookups 16102191 # Number of BP lookups +system.cpu.branchPred.condPredicted 11688099 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 930994 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8963309 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7508263 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.271680 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1595490 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 408 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 83.766642 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1594548 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 465 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 29370 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 25724 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 3646 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 560 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 24061115 # DTB read hits -system.cpu.dtb.read_misses 205797 # DTB read misses -system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 24266912 # DTB read accesses -system.cpu.dtb.write_hits 7162299 # DTB write hits -system.cpu.dtb.write_misses 1202 # DTB write misses +system.cpu.dtb.read_hits 24064579 # DTB read hits +system.cpu.dtb.read_misses 206327 # DTB read misses +system.cpu.dtb.read_acv 4 # DTB read access violations +system.cpu.dtb.read_accesses 24270906 # DTB read accesses +system.cpu.dtb.write_hits 7168860 # DTB write hits +system.cpu.dtb.write_misses 1193 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 7163501 # DTB write accesses -system.cpu.dtb.data_hits 31223414 # DTB hits -system.cpu.dtb.data_misses 206999 # DTB misses -system.cpu.dtb.data_acv 2 # DTB access violations -system.cpu.dtb.data_accesses 31430413 # DTB accesses -system.cpu.itb.fetch_hits 15924997 # ITB hits -system.cpu.itb.fetch_misses 77 # ITB misses +system.cpu.dtb.write_accesses 7170053 # DTB write accesses +system.cpu.dtb.data_hits 31233439 # DTB hits +system.cpu.dtb.data_misses 207520 # DTB misses +system.cpu.dtb.data_acv 4 # DTB access violations +system.cpu.dtb.data_accesses 31440959 # DTB accesses +system.cpu.itb.fetch_hits 15932703 # ITB hits +system.cpu.itb.fetch_misses 79 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 15925074 # ITB accesses +system.cpu.itb.fetch_accesses 15932782 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,236 +297,236 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 43833882 # number of cpu cycles simulated +system.cpu.numCycles 43818418 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 16631894 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 137948476 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16111441 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9125178 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 25988337 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1931044 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 16643559 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 137979359 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16102191 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9128535 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 25956071 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1939868 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 165 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2266 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 2614 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 15924997 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 365277 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 43588192 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.164813 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.433150 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 15932703 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 367699 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 43572351 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.166672 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.433625 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19406935 44.52% 44.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2620914 6.01% 50.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1337526 3.07% 53.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1925752 4.42% 58.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3007087 6.90% 64.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1288201 2.96% 67.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1362015 3.12% 71.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 884285 2.03% 73.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11755477 26.97% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19392056 44.51% 44.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2618542 6.01% 50.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1330036 3.05% 53.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1934112 4.44% 58.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3001913 6.89% 64.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1292242 2.97% 67.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1355704 3.11% 70.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 886645 2.03% 73.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11761101 26.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43588192 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.367557 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.147074 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12849243 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8247037 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19437084 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2100878 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 953950 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2651003 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 11975 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 132120831 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 49966 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 953950 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13971462 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4650933 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10896 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20300187 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3700764 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 128743195 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 69669 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2038779 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1385854 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 54667 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 94545107 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 167268798 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 159787749 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7481048 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 43572351 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.367475 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.148890 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12867028 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8206518 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19434084 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2106116 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 958605 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2654233 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 11853 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 132149690 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 49712 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 958605 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13986113 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4641138 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10397 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20305818 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3670280 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 128777120 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 70822 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2026790 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1359443 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 54939 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 94599417 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 167333836 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 159779688 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7554147 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 26117746 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 26172056 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 950 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 948 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8310352 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26910154 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8709135 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3511293 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1618997 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111850389 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1284 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 99739394 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 116060 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 27671963 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 21101257 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 895 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43588192 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.288220 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.099837 # Number of insts issued each cycle +system.cpu.rename.tempSerializingInsts 946 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8271760 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26904379 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8704430 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3459754 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1614105 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111855372 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1919 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 99762873 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 119457 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 27677581 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 21095041 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1530 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43572351 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.289591 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.099378 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11252596 25.82% 25.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 7641941 17.53% 43.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7479961 17.16% 60.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5717065 13.12% 73.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4459781 10.23% 83.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2974994 6.83% 90.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2026656 4.65% 95.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1169278 2.68% 98.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 865920 1.99% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11226739 25.77% 25.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 7658694 17.58% 43.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7470474 17.14% 60.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5702469 13.09% 73.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4463101 10.24% 83.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2983064 6.85% 90.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2041659 4.69% 95.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1171062 2.69% 98.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 855089 1.96% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43588192 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43572351 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 482625 20.24% 20.24% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 20.24% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 20.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 536 0.02% 20.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 34267 1.44% 21.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 12315 0.52% 22.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1010469 42.37% 64.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 64.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 64.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 686537 28.79% 93.37% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 158059 6.63% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 483998 20.16% 20.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 20.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 20.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 538 0.02% 20.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 34928 1.45% 21.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 12187 0.51% 22.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1012495 42.17% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 694978 28.95% 93.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 161680 6.73% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60676588 60.84% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 490565 0.49% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2839004 2.85% 64.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115354 0.12% 64.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2438838 2.45% 66.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 313701 0.31% 67.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 766055 0.77% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24836317 24.90% 92.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7262646 7.28% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60663003 60.81% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 489936 0.49% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2847512 2.85% 64.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115351 0.12% 64.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2443315 2.45% 66.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 314199 0.31% 67.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 765838 0.77% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24854808 24.91% 92.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7268585 7.29% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 99739394 # Type of FU issued -system.cpu.iq.rate 2.275395 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2384808 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023910 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 229942315 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 130052988 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 89783673 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15625533 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9511643 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7169331 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 93775141 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8349054 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1917494 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 99762873 # Type of FU issued +system.cpu.iq.rate 2.276734 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2400804 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.024065 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 229929463 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 129921880 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 89757813 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15688895 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9653551 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7189472 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 93781732 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8381938 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1923340 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6913956 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11070 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 41356 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2208032 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6908181 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11335 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 40937 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2203327 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 42783 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1512 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 42874 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1494 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 953950 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3617044 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 465078 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 122781228 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 240022 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26910154 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8709135 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1284 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 38486 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 420890 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 41356 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 525280 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 502970 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1028250 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 98428862 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 24267391 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1310532 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 958605 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3611196 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 465334 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 122779718 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 241439 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 26904379 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8704430 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1919 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 38387 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 421097 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 40937 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 531949 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 502390 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1034339 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 98437326 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 24271451 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1325547 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10929555 # number of nop insts executed -system.cpu.iew.exec_refs 31430926 # number of memory reference insts executed -system.cpu.iew.exec_branches 12487406 # Number of branches executed -system.cpu.iew.exec_stores 7163535 # Number of stores executed -system.cpu.iew.exec_rate 2.245497 # Inst execution rate -system.cpu.iew.wb_sent 97642114 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 96953004 # cumulative count of insts written-back -system.cpu.iew.wb_producers 66984387 # num instructions producing a value -system.cpu.iew.wb_consumers 95000699 # num instructions consuming a value -system.cpu.iew.wb_rate 2.211828 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.705094 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 30880053 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 10922427 # number of nop insts executed +system.cpu.iew.exec_refs 31441543 # number of memory reference insts executed +system.cpu.iew.exec_branches 12471856 # Number of branches executed +system.cpu.iew.exec_stores 7170092 # Number of stores executed +system.cpu.iew.exec_rate 2.246483 # Inst execution rate +system.cpu.iew.wb_sent 97646069 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 96947285 # cumulative count of insts written-back +system.cpu.iew.wb_producers 66976790 # num instructions producing a value +system.cpu.iew.wb_consumers 94960923 # num instructions consuming a value +system.cpu.iew.wb_rate 2.212478 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.705309 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 30878414 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 914663 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 39095166 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.350752 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.921213 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 919665 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 39078577 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.351750 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.919984 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 14698751 37.60% 37.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8546224 21.86% 59.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3864207 9.88% 69.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1928510 4.93% 74.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1372257 3.51% 77.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1004424 2.57% 80.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 690640 1.77% 82.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 733325 1.88% 84.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6256828 16.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 14680368 37.57% 37.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8532696 21.83% 59.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3879932 9.93% 69.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1909819 4.89% 74.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1376650 3.52% 77.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1035169 2.65% 80.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 692226 1.77% 82.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 728499 1.86% 84.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6243218 15.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 39095166 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 39078577 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -568,356 +572,356 @@ system.cpu.commit.op_class_0::MemWrite 6501103 7.07% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction -system.cpu.commit.bw_lim_events 6256828 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 155620406 # The number of ROB reads -system.cpu.rob.rob_writes 250114778 # The number of ROB writes -system.cpu.timesIdled 4635 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 245690 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 6243218 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 155615788 # The number of ROB reads +system.cpu.rob.rob_writes 250112160 # The number of ROB writes +system.cpu.timesIdled 4756 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 246067 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.520718 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.520718 # CPI: Total CPI of All Threads -system.cpu.ipc 1.920426 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.920426 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 132978272 # number of integer regfile reads -system.cpu.int_regfile_writes 72916434 # number of integer regfile writes -system.cpu.fp_regfile_reads 6252591 # number of floating regfile reads -system.cpu.fp_regfile_writes 6155476 # number of floating regfile writes -system.cpu.misc_regfile_reads 719142 # number of misc regfile reads +system.cpu.cpi 0.520534 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.520534 # CPI: Total CPI of All Threads +system.cpu.ipc 1.921103 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.921103 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 133011224 # number of integer regfile reads +system.cpu.int_regfile_writes 72905073 # number of integer regfile writes +system.cpu.fp_regfile_reads 6263399 # number of floating regfile reads +system.cpu.fp_regfile_writes 6178143 # number of floating regfile writes +system.cpu.misc_regfile_reads 719113 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 158 # number of replacements -system.cpu.dcache.tags.tagsinuse 1457.328310 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28591208 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2244 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12741.180036 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1457.375474 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28588753 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2245 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12734.411136 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1457.328310 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.355793 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.355793 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2086 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1457.375474 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.355805 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.355805 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2087 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 542 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 137 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 536 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1389 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.509277 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 57203742 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 57203742 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22098137 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22098137 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492614 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492614 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 457 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 457 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28590751 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28590751 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28590751 # number of overall hits -system.cpu.dcache.overall_hits::total 28590751 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1051 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1051 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8489 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8489 # number of WriteReq misses +system.cpu.dcache.tags.occ_task_id_percent::1024 0.509521 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 57198843 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 57198843 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22095651 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22095651 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492632 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492632 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 470 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 470 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28588283 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28588283 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28588283 # number of overall hits +system.cpu.dcache.overall_hits::total 28588283 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1074 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1074 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8471 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8471 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9540 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9540 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9540 # number of overall misses -system.cpu.dcache.overall_misses::total 9540 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 72374000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 72374000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 544060252 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 544060252 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9545 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9545 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9545 # number of overall misses +system.cpu.dcache.overall_misses::total 9545 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 71413000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 71413000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 546757246 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 546757246 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 85000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 85000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 616434252 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 616434252 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 616434252 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 616434252 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22099188 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22099188 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 618170246 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 618170246 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 618170246 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 618170246 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22096725 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22096725 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 458 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 458 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28600291 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28600291 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28600291 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28600291 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000048 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000048 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001306 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001306 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002183 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002183 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 471 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 471 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28597828 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28597828 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28597828 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28597828 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000049 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000049 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001303 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001303 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002123 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002123 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000334 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000334 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000334 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000334 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68862.036156 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68862.036156 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64090.028507 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64090.028507 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66492.551210 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66492.551210 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64544.592846 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64544.592846 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64615.749686 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64615.749686 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64615.749686 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64615.749686 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32998 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64763.776427 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64763.776427 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64763.776427 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64763.776427 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32543 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 127 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 378 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 392 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 87.296296 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.017857 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 63.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 108 # number of writebacks system.cpu.dcache.writebacks::total 108 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 544 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 544 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6753 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6753 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7297 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7297 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7297 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7297 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 507 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 335979500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 335979500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 335979500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000717 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000717 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000717 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000717 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000717 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000717 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29438.315955 # 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number of cache copies performed -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1710 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1710 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3058 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3058 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 454 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 454 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3058 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2164 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5222 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3058 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2164 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5222 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 115534500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 115534500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 200270500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 200270500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 34760500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 34760500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 200270500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 150295000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 350565500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 200270500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 150295000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 350565500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985023 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985023 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.267940 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.267940 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.893701 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.893701 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.267940 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964349 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.382368 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.267940 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964349 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.382368 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67564.035088 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67564.035088 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65490.680183 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65490.680183 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76564.977974 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76564.977974 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65490.680183 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69452.402957 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67132.420529 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65490.680183 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69452.402957 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67132.420529 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1703 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1703 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3062 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3062 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 462 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 462 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3062 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2165 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5227 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3062 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2165 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5227 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 115846500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 115846500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 200477000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 200477000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 33886000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 33886000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 200477000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 149732500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 350209500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 200477000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 149732500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 350209500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984962 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984962 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.267330 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.267330 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.895349 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.895349 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.267330 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964365 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.381561 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.267330 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964365 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.381561 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68024.955960 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68024.955960 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65472.566950 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65472.566950 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73346.320346 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73346.320346 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65472.566950 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69160.508083 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67000.095657 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65472.566950 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69160.508083 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67000.095657 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 23291 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9634 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 23372 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9673 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 11921 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 11969 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 108 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 9476 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 9515 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1736 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1736 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 11413 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 508 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32302 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4646 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 36948 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1336896 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1487424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 1729 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1729 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 11454 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 516 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32422 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4648 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 37070 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1341952 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1492544 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 13657 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 13699 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 13657 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 13699 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 13657 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 21229500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 13699 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 21309000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 17119500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 17179500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3366000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3367500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3512 # Transaction distribution -system.membus.trans_dist::ReadExReq 1710 # Transaction distribution -system.membus.trans_dist::ReadExResp 1710 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3512 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10444 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10444 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 334208 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 3524 # Transaction distribution +system.membus.trans_dist::ReadExReq 1703 # Transaction distribution +system.membus.trans_dist::ReadExResp 1703 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3524 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10454 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10454 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 334528 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5222 # Request fanout histogram +system.membus.snoop_fanout::samples 5227 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5222 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5227 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5222 # Request fanout histogram -system.membus.reqLayer0.occupancy 6271000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5227 # Request fanout histogram +system.membus.reqLayer0.occupancy 6276500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 27427000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 27456000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index fae4160aa..21492b1f0 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.130773 # Number of seconds simulated -sim_ticks 130772642500 # Number of ticks simulated -final_tick 130772642500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.130383 # Number of seconds simulated +sim_ticks 130382890500 # Number of ticks simulated +final_tick 130382890500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 239563 # Simulator instruction rate (inst/s) -host_op_rate 252538 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 181805529 # Simulator tick rate (ticks/s) -host_mem_usage 322304 # Number of bytes of host memory used -host_seconds 719.30 # Real time elapsed on the host +host_inst_rate 248644 # Simulator instruction rate (inst/s) +host_op_rate 262111 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 188134778 # Simulator tick rate (ticks/s) +host_mem_usage 275596 # Number of bytes of host memory used +host_seconds 693.03 # Real time elapsed on the host sim_insts 172317810 # Number of instructions simulated sim_ops 181650743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 138112 # Nu system.physmem.num_reads::cpu.inst 2158 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory system.physmem.num_reads::total 3866 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1056123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 835893 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1892017 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1056123 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1056123 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1056123 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 835893 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1892017 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1059280 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 838392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1897672 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1059280 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1059280 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1059280 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 838392 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1897672 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 3866 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 3866 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 130772548000 # Total gap between requests +system.physmem.totGap 130382796000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3617 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3618 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 236 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 905 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 271.628729 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.806384 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 277.022098 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 259 28.62% 28.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 352 38.90% 67.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 86 9.50% 77.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 59 6.52% 83.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 34 3.76% 87.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 21 2.32% 89.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 17 1.88% 91.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 17 1.88% 93.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 60 6.63% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 905 # Bytes accessed per row activation -system.physmem.totQLat 27654500 # Total ticks spent queuing -system.physmem.totMemAccLat 100142000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 915 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 268.939891 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 176.781102 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 276.529935 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 273 29.84% 29.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 347 37.92% 67.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 83 9.07% 76.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 59 6.45% 83.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 35 3.83% 87.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 24 2.62% 89.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 16 1.75% 91.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 20 2.19% 93.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 58 6.34% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 915 # Bytes accessed per row activation +system.physmem.totQLat 27071500 # Total ticks spent queuing +system.physmem.totMemAccLat 99559000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 19330000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7153.26 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7002.46 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25903.26 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.89 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25752.46 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.89 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.90 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.01 # Data bus utilization in percentage @@ -216,49 +216,53 @@ system.physmem.busUtilRead 0.01 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 2957 # Number of row buffer hits during reads +system.physmem.readRowHits 2948 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.49 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.25 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 33826318.68 # Average gap between requests -system.physmem.pageHitRate 76.49 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3099600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1691250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 16161600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 33725503.36 # Average gap between requests +system.physmem.pageHitRate 76.25 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3144960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1716000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16192800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 8541265200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3568631490 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 75331810500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 87462659640 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.826558 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 125319167750 # Time in different power states -system.physmem_0.memoryStateTime::REF 4366700000 # Time in different power states +system.physmem_0.refreshEnergy 8515837200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3562127505 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 75103936500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 87202954965 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.831686 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 124939990750 # Time in different power states +system.physmem_0.memoryStateTime::REF 4353700000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1084461000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1087339250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3727080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2033625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 13782600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3764880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2054250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13790400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 8541265200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3564306900 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 75335612250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 87460727655 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.811714 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 125325942500 # Time in different power states -system.physmem_1.memoryStateTime::REF 4366700000 # Time in different power states +system.physmem_1.refreshEnergy 8515837200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3544157970 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 75119701500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 87199306200 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.803682 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 124966482000 # Time in different power states +system.physmem_1.memoryStateTime::REF 4353700000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1077991500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1060850750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 49732170 # Number of BP lookups -system.cpu.branchPred.condPredicted 39495980 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5592247 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24154061 # Number of BTB lookups -system.cpu.branchPred.BTBHits 23128262 # Number of BTB hits +system.cpu.branchPred.lookups 49622074 # Number of BP lookups +system.cpu.branchPred.condPredicted 39447439 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5514206 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 24092073 # Number of BTB lookups +system.cpu.branchPred.BTBHits 22843202 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.753099 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1888632 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 94.816258 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1888965 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 142 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 213748 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 207973 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5775 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 40452 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -377,69 +381,104 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 261545285 # number of cpu cycles simulated +system.cpu.numCycles 260765781 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 172317810 # Number of instructions committed system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed -system.cpu.discardedOps 11660914 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 11583006 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.517808 # CPI: cycles per instruction -system.cpu.ipc 0.658845 # IPC: instructions per cycle -system.cpu.tickCycles 255252020 # Number of cycles that the object actually ticked -system.cpu.idleCycles 6293265 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.513284 # CPI: cycles per instruction +system.cpu.ipc 0.660815 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.op_class_0::IntAlu 138988213 76.51% 76.51% # Class of committed instruction +system.cpu.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 32754 0.02% 77.03% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 77.03% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 154829 0.09% 77.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 238880 0.13% 77.25% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 76016 0.04% 77.29% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 437591 0.24% 77.53% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction +system.cpu.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction +system.cpu.op_class_0::MemWrite 12644635 6.96% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 181650743 # Class of committed instruction +system.cpu.tickCycles 254551967 # Number of cycles that the object actually ticked +system.cpu.idleCycles 6213814 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1377.707606 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40756382 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22517.338122 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1378.689350 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40754473 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1811 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22503.850359 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1377.707606 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.336354 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.336354 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1378.689350 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.336594 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.336594 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1769 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1358 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.431641 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 81519460 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 81519460 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 28348467 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28348467 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12362639 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12362639 # number of WriteReq hits +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1359 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.431885 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 81515639 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 81515639 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28346557 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28346557 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12362640 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12362640 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40711106 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40711106 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40711568 # number of overall hits -system.cpu.dcache.overall_hits::total 40711568 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 794 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 794 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1648 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1648 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 40709197 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40709197 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40709659 # number of overall hits +system.cpu.dcache.overall_hits::total 40709659 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 793 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 793 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1647 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1647 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 2442 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2442 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2443 # number of overall misses -system.cpu.dcache.overall_misses::total 2443 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 58082000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 58082000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 126294500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 126294500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 184376500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 184376500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 184376500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 184376500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28349261 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28349261 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2440 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2440 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2441 # number of overall misses +system.cpu.dcache.overall_misses::total 2441 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 59629000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 59629000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 126003000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 126003000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 185632000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 185632000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 185632000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 185632000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28347350 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28347350 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses) @@ -448,10 +487,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 40713548 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 40713548 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 40714011 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 40714011 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 40711637 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 40711637 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 40712100 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 40712100 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses @@ -462,14 +501,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73151.133501 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 73151.133501 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76635.012136 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76635.012136 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 75502.252252 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 75502.252252 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 75471.346705 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 75471.346705 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75194.199243 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 75194.199243 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76504.553734 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76504.553734 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76078.688525 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76078.688525 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76047.521508 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76047.521508 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -480,34 +519,34 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 16 # number of writebacks system.cpu.dcache.writebacks::total 16 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 550 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 550 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 633 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 633 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 633 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 633 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 82 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 548 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 548 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 630 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 630 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 630 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 630 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1098 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1098 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1099 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1099 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1809 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1809 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1810 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51822500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 51822500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85060000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 85060000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 1810 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1811 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1811 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52555500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 52555500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85213000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85213000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 70000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 70000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136882500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 136882500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136952500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 136952500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 137768500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 137768500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 137838500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 137838500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses @@ -518,71 +557,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72886.779184 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72886.779184 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77468.123862 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77468.123862 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73917.721519 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73917.721519 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77536.851683 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77536.851683 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75667.495854 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75667.495854 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75664.364641 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75664.364641 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76115.193370 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76115.193370 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76111.816676 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76111.816676 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 2888 # number of replacements -system.cpu.icache.tags.tagsinuse 1423.991712 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 71011798 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4684 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 15160.503416 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2881 # number of replacements +system.cpu.icache.tags.tagsinuse 1423.942746 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 70779397 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4677 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 15133.503742 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1423.991712 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.695308 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.695308 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1423.942746 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.695285 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.695285 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1796 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 123 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 496 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 122 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1068 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.876953 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 142037650 # Number of tag accesses -system.cpu.icache.tags.data_accesses 142037650 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 71011798 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 71011798 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 71011798 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 71011798 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 71011798 # number of overall hits -system.cpu.icache.overall_hits::total 71011798 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4685 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4685 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4685 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4685 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4685 # number of overall misses -system.cpu.icache.overall_misses::total 4685 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 199916500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 199916500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 199916500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 199916500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 199916500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 199916500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 71016483 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 71016483 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 71016483 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 71016483 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 71016483 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 71016483 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 141572827 # Number of tag accesses +system.cpu.icache.tags.data_accesses 141572827 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 70779397 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 70779397 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 70779397 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 70779397 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 70779397 # number of overall hits +system.cpu.icache.overall_hits::total 70779397 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4678 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4678 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4678 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4678 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4678 # number of overall misses +system.cpu.icache.overall_misses::total 4678 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 198432500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 198432500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 198432500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 198432500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 198432500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 198432500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 70784075 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 70784075 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 70784075 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 70784075 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 70784075 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 70784075 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42671.611526 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42671.611526 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42671.611526 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42671.611526 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42671.611526 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42671.611526 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42418.234288 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42418.234288 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42418.234288 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42418.234288 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42418.234288 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42418.234288 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -591,135 +630,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 2888 # number of writebacks -system.cpu.icache.writebacks::total 2888 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4685 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4685 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4685 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4685 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4685 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4685 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 195232500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 195232500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 195232500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 195232500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 195232500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 195232500 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 2881 # number of writebacks +system.cpu.icache.writebacks::total 2881 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4678 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4678 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4678 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4678 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4678 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4678 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 193755500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 193755500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 193755500 # 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average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41671.824973 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41671.824973 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 41671.824973 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41671.824973 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 41671.824973 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41418.448055 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41418.448055 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41418.448055 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 41418.448055 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41418.448055 # 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Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 3.029285 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1506.756648 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 490.818207 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 3.029345 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1506.706963 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 489.811820 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.045983 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.014979 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.061054 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 2784 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.045981 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.014948 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.061021 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 2783 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 524 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 151 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2004 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084961 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 76658 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 76658 # Number of data accesses +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 149 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2003 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084930 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 76554 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 76554 # Number of data accesses system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 2566 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 2566 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::writebacks 2559 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 2559 # 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number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 134101000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 294038500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 2566 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 2566 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1098 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1098 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4685 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 4685 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 2559 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 2559 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1099 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1099 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4678 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 4678 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 712 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 4685 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1810 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 6495 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 4685 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 115186000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 254787500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139601500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 115186000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 254787500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992714 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.460832 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.460832 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.867978 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.867978 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.460832 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.595381 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.460832 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.595381 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66447.247706 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66447.247706 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64660.259379 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64660.259379 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69188.511327 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69188.511327 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64660.259379 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67439.110070 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65887.638997 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64660.259379 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67439.110070 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65887.638997 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 72569000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 72569000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 138134000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 138134000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 43490000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 43490000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138134000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 116059000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 254193000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138134000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 116059000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 254193000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992721 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992721 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.461522 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.461522 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.866573 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.866573 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461522 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.595932 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461522 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.595932 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66516.040330 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66516.040330 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63980.546549 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63980.546549 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70486.223663 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70486.223663 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63980.546549 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67950.234192 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65733.902250 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63980.546549 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67950.234192 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65733.902250 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 9425 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 3064 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 9412 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 3057 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 328 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 5396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5389 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2888 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2881 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 26 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 4685 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1099 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1099 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 4678 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 712 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12257 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3662 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 15919 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 484608 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 601472 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12236 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3664 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 15900 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 483712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 600640 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6495 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.071132 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.257064 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 6489 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.071197 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.257174 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 6033 92.89% 92.89% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 462 7.11% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 6027 92.88% 92.88% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 462 7.12% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6495 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7616500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 6489 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7603000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7026998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7016498 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2721986 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2723486 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 2776 # Transaction distribution -system.membus.trans_dist::ReadExReq 1090 # Transaction distribution -system.membus.trans_dist::ReadExResp 1090 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 2776 # Transaction distribution +system.membus.trans_dist::ReadResp 2775 # Transaction distribution +system.membus.trans_dist::ReadExReq 1091 # Transaction distribution +system.membus.trans_dist::ReadExResp 1091 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 2775 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7732 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 7732 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247424 # Cumulative packet size per connected master and slave (bytes) @@ -844,9 +883,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 3866 # Request fanout histogram -system.membus.reqLayer0.occupancy 4535500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4516500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 20543250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20548250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 03798f86c..7b9f789c6 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,65 +1,65 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.085490 # Number of seconds simulated -sim_ticks 85490431000 # Number of ticks simulated -final_tick 85490431000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.084938 # Number of seconds simulated +sim_ticks 84937723500 # Number of ticks simulated +final_tick 84937723500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61561 # Simulator instruction rate (inst/s) -host_op_rate 64896 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 30544518 # Simulator tick rate (ticks/s) -host_mem_usage 301600 # Number of bytes of host memory used -host_seconds 2798.88 # Real time elapsed on the host +host_inst_rate 146803 # Simulator instruction rate (inst/s) +host_op_rate 154755 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 72367413 # Simulator tick rate (ticks/s) +host_mem_usage 271624 # Number of bytes of host memory used +host_seconds 1173.70 # Real time elapsed on the host sim_insts 172303022 # Number of instructions simulated sim_ops 181635954 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 587136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 132032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 70784 # Number of bytes read from this memory -system.physmem.bytes_read::total 789952 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 587136 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 587136 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 9174 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2063 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 1106 # Number of read requests responded to by this memory -system.physmem.num_reads::total 12343 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 6867856 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1544407 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 827976 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9240239 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6867856 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6867856 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6867856 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1544407 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 827976 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9240239 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 12344 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 587328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 132096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 70976 # Number of bytes read from this memory +system.physmem.bytes_read::total 790400 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 587328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 587328 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 9177 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2064 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 1109 # Number of read requests responded to by this memory +system.physmem.num_reads::total 12350 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 6914807 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1555210 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 835624 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9305641 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6914807 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6914807 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6914807 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1555210 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 835624 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9305641 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 12351 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 12344 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 12351 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 790016 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 790464 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 790016 # Total read bytes from the system interface side +system.physmem.bytesReadSys 790464 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1112 # Per bank write bursts -system.physmem.perBankRdBursts::1 371 # Per bank write bursts -system.physmem.perBankRdBursts::2 5091 # Per bank write bursts -system.physmem.perBankRdBursts::3 435 # Per bank write bursts -system.physmem.perBankRdBursts::4 1954 # Per bank write bursts -system.physmem.perBankRdBursts::5 426 # Per bank write bursts -system.physmem.perBankRdBursts::6 266 # Per bank write bursts -system.physmem.perBankRdBursts::7 369 # Per bank write bursts -system.physmem.perBankRdBursts::8 265 # Per bank write bursts -system.physmem.perBankRdBursts::9 221 # Per bank write bursts +system.physmem.perBankRdBursts::0 1113 # Per bank write bursts +system.physmem.perBankRdBursts::1 381 # Per bank write bursts +system.physmem.perBankRdBursts::2 5089 # Per bank write bursts +system.physmem.perBankRdBursts::3 423 # Per bank write bursts +system.physmem.perBankRdBursts::4 1959 # Per bank write bursts +system.physmem.perBankRdBursts::5 424 # Per bank write bursts +system.physmem.perBankRdBursts::6 265 # Per bank write bursts +system.physmem.perBankRdBursts::7 373 # Per bank write bursts +system.physmem.perBankRdBursts::8 266 # Per bank write bursts +system.physmem.perBankRdBursts::9 219 # Per bank write bursts system.physmem.perBankRdBursts::10 295 # Per bank write bursts -system.physmem.perBankRdBursts::11 323 # Per bank write bursts -system.physmem.perBankRdBursts::12 197 # Per bank write bursts +system.physmem.perBankRdBursts::11 324 # Per bank write bursts +system.physmem.perBankRdBursts::12 199 # Per bank write bursts system.physmem.perBankRdBursts::13 249 # Per bank write bursts -system.physmem.perBankRdBursts::14 227 # Per bank write bursts +system.physmem.perBankRdBursts::14 229 # Per bank write bursts system.physmem.perBankRdBursts::15 543 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 85490422000 # Total gap between requests +system.physmem.totGap 84937714500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 12344 # Read request sizes (log2) +system.physmem.readPktSize::6 12351 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,15 +94,15 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 10928 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 977 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 10935 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 975 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 83 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 37 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 85 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see @@ -190,29 +190,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 7242 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 108.822977 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 85.142878 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 132.567115 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 5271 72.78% 72.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 1523 21.03% 93.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 185 2.55% 96.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 87 1.20% 97.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 38 0.52% 98.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 26 0.36% 98.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 17 0.23% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 18 0.25% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 77 1.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 7242 # Bytes accessed per row activation -system.physmem.totQLat 167084529 # Total ticks spent queuing -system.physmem.totMemAccLat 398534529 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 61720000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13535.69 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 7250 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 108.738207 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 85.269087 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 131.624325 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 5249 72.40% 72.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 1564 21.57% 93.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 167 2.30% 96.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 93 1.28% 97.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 42 0.58% 98.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 24 0.33% 98.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 18 0.25% 98.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 21 0.29% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 72 0.99% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 7250 # Bytes accessed per row activation +system.physmem.totQLat 171430514 # Total ticks spent queuing +system.physmem.totMemAccLat 403011764 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 61755000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13879.89 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32285.69 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 9.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 32629.89 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 9.31 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 9.24 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 9.31 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.07 # Data bus utilization in percentage @@ -220,49 +220,53 @@ system.physmem.busUtilRead 0.07 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 5095 # Number of row buffer hits during reads +system.physmem.readRowHits 5094 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 41.28 # Row buffer hit rate for reads +system.physmem.readRowHitRate 41.24 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 6925666.07 # Average gap between requests -system.physmem.pageHitRate 41.28 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 48527640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 26478375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 78156000 # Energy for read commands per rank (pJ) +system.physmem.avgGap 6876990.89 # Average gap between requests +system.physmem.pageHitRate 41.24 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 48452040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 26437125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 78179400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5583480240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 17009559810 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 36370632750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 59116834815 # Total energy per rank (pJ) -system.physmem_0.averagePower 691.542258 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 60400646468 # Time in different power states -system.physmem_0.memoryStateTime::REF 2854540000 # Time in different power states +system.physmem_0.refreshEnergy 5547372480 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 16645874445 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 36357960750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 58704276240 # Total energy per rank (pJ) +system.physmem_0.averagePower 691.186004 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 60381088491 # Time in different power states +system.physmem_0.memoryStateTime::REF 2836080000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 22233687032 # Time in different power states +system.physmem_0.memoryStateTime::ACT 21718991509 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6199200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3382500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 17869800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 6335280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3456750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 17877600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5583480240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3325437855 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 48374248500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 57310618095 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.413332 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 80466021414 # Time in different power states -system.physmem_1.memoryStateTime::REF 2854540000 # Time in different power states +system.physmem_1.refreshEnergy 5547372480 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3295031490 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 48069226500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 56939300100 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.405119 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 79958437412 # Time in different power states +system.physmem_1.memoryStateTime::REF 2836080000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2165082586 # Time in different power states +system.physmem_1.memoryStateTime::ACT 2138239588 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 85927149 # Number of BP lookups -system.cpu.branchPred.condPredicted 68408695 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6018080 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 40104766 # Number of BTB lookups -system.cpu.branchPred.BTBHits 39018080 # Number of BTB hits +system.cpu.branchPred.lookups 85626366 # Number of BP lookups +system.cpu.branchPred.condPredicted 68177013 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5935452 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 39946926 # Number of BTB lookups +system.cpu.branchPred.BTBHits 38187698 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.290382 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3702096 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 81897 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 95.596087 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3683716 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 81912 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 681689 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 653746 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 27943 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 40316 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -381,233 +385,233 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 170980863 # number of cpu cycles simulated +system.cpu.numCycles 169875448 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5755157 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 349305240 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85927149 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42720176 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 158448180 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 12049937 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 2618 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 5671940 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 347162762 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85626366 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42525160 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 157499775 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11884731 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2609 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 3916 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 78960236 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 19348 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 170234862 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.146650 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.050166 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3808 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 78326624 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 18246 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 169120520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.147875 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.049260 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 17669518 10.38% 10.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30211265 17.75% 28.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31838913 18.70% 46.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 90515166 53.17% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 17456404 10.32% 10.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30071791 17.78% 28.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31598997 18.68% 46.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 89993328 53.21% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 170234862 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.502554 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.042949 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17700032 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 17289472 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 122672401 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6722857 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5850100 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11135652 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 190021 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 306632940 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27644957 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5850100 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37887834 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8551246 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 582035 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 108933106 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8430541 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 278671233 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13418761 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3051568 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 841704 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2280860 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 35921 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 27095 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 483139430 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1196998780 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 297599206 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3005965 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 169120520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.504054 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.043631 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17509987 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 17244874 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 121866560 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6731455 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5767644 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11064434 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 189777 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 304997911 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27240618 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5767644 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37477523 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8502539 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 578983 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 108355768 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8438063 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 277420851 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13180734 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3058487 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 843003 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2280960 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 36243 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 27083 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 481449871 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1191735135 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 296461789 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3004325 # Number of floating rename lookups system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 190162501 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 23526 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23429 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13338905 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 34139598 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14476816 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2548575 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1784456 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 264827834 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 45856 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 214914585 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5192491 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 83237736 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 219939522 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 640 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 170234862 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.262459 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.017804 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 188472942 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 23603 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23603 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13353784 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 33915046 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14407100 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2540378 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1803003 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 263798584 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 45955 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 214411803 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5187874 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 82208585 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 217092419 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 739 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 169120520 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.267805 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.017994 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 53140673 31.22% 31.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 36118420 21.22% 52.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 65796647 38.65% 91.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 13561298 7.97% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1570362 0.92% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 47243 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 219 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52408217 30.99% 30.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 35940187 21.25% 52.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 65510990 38.74% 90.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13642635 8.07% 99.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1570936 0.93% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 47343 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 212 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 170234862 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 169120520 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35603971 66.12% 66.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 152944 0.28% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 1066 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 35746 0.07% 66.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 240 0.00% 66.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 952 0.00% 66.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 34296 0.06% 66.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.54% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 14072260 26.13% 92.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3948482 7.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35659439 66.16% 66.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 153265 0.28% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 1066 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 35730 0.07% 66.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 240 0.00% 66.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 958 0.00% 66.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 34286 0.06% 66.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 14056522 26.08% 92.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3955910 7.34% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 167357330 77.87% 77.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 918980 0.43% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33017 0.02% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 165190 0.08% 78.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 245699 0.11% 78.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 460522 0.21% 78.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206694 0.10% 78.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 32005177 14.89% 93.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13374016 6.22% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 166992897 77.88% 77.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 919175 0.43% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33015 0.02% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 165179 0.08% 78.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 245702 0.11% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 460499 0.21% 78.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206683 0.10% 78.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 31868874 14.86% 93.76% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13371819 6.24% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 214914585 # Type of FU issued -system.cpu.iq.rate 1.256951 # Inst issue rate -system.cpu.iq.fu_busy_cnt 53850162 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.250565 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 655153476 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 346106935 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 204606292 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3953209 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2011310 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1806290 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266630626 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2134121 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1600828 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 214411803 # Type of FU issued +system.cpu.iq.rate 1.262171 # Inst issue rate +system.cpu.iq.fu_busy_cnt 53897621 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.251374 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 653076785 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 344050437 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 204251594 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3952836 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2009578 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1806333 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266175663 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2133761 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1598827 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6243454 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7546 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6949 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1832182 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6018902 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7447 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7034 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1762466 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 25935 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 794 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 25527 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 769 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5850100 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5682962 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 61282 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 264889651 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 5767644 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5618767 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 62916 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 263864756 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 34139598 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14476816 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23448 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3916 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 54251 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6949 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3234598 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3248118 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6482716 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 207529725 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 30719767 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7384860 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 33915046 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14407100 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23547 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3855 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 55872 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 7034 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3149041 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3246654 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6395695 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 207125960 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 30633355 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7285843 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 15961 # number of nop insts executed -system.cpu.iew.exec_refs 43859608 # number of memory reference insts executed -system.cpu.iew.exec_branches 44936158 # Number of branches executed -system.cpu.iew.exec_stores 13139841 # Number of stores executed -system.cpu.iew.exec_rate 1.213760 # Inst execution rate -system.cpu.iew.wb_sent 206746993 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 206412582 # cumulative count of insts written-back -system.cpu.iew.wb_producers 129474820 # num instructions producing a value -system.cpu.iew.wb_consumers 221691878 # num instructions consuming a value -system.cpu.iew.wb_rate 1.207226 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.584031 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 69543013 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 20217 # number of nop insts executed +system.cpu.iew.exec_refs 43771495 # number of memory reference insts executed +system.cpu.iew.exec_branches 44852998 # Number of branches executed +system.cpu.iew.exec_stores 13138140 # Number of stores executed +system.cpu.iew.exec_rate 1.219281 # Inst execution rate +system.cpu.iew.wb_sent 206368045 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 206057927 # cumulative count of insts written-back +system.cpu.iew.wb_producers 129397136 # num instructions producing a value +system.cpu.iew.wb_consumers 221651580 # num instructions consuming a value +system.cpu.iew.wb_rate 1.212994 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.583786 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 68672645 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5843212 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158791205 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.143957 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.645227 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5760731 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 157823719 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.150970 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.652577 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 73988497 46.59% 46.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 41295308 26.01% 72.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 22556711 14.21% 86.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9630949 6.07% 92.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3552216 2.24% 95.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2148211 1.35% 96.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1284578 0.81% 97.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 986502 0.62% 97.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3348233 2.11% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 73232232 46.40% 46.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 41142749 26.07% 72.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 22534270 14.28% 86.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9514853 6.03% 92.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3552076 2.25% 95.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2143258 1.36% 96.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1327703 0.84% 97.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1008942 0.64% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3367636 2.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158791205 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 157823719 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317410 # Number of instructions committed system.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -653,382 +657,383 @@ system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 181650342 # Class of committed instruction -system.cpu.commit.bw_lim_events 3348233 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 406631126 # The number of ROB reads -system.cpu.rob.rob_writes 513844376 # The number of ROB writes -system.cpu.timesIdled 8957 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 746001 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3367636 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 404773869 # The number of ROB reads +system.cpu.rob.rob_writes 511956769 # The number of ROB writes +system.cpu.timesIdled 9030 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 754928 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303022 # Number of Instructions Simulated system.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.992327 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.992327 # CPI: Total CPI of All Threads -system.cpu.ipc 1.007733 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.007733 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 218966992 # number of integer regfile reads -system.cpu.int_regfile_writes 114516229 # number of integer regfile writes -system.cpu.fp_regfile_reads 2904204 # number of floating regfile reads -system.cpu.fp_regfile_writes 2441504 # number of floating regfile writes -system.cpu.cc_regfile_reads 709589080 # number of cc regfile reads -system.cpu.cc_regfile_writes 229556340 # number of cc regfile writes -system.cpu.misc_regfile_reads 59312089 # number of misc regfile reads +system.cpu.cpi 0.985911 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.985911 # CPI: Total CPI of All Threads +system.cpu.ipc 1.014290 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.014290 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 218725741 # number of integer regfile reads +system.cpu.int_regfile_writes 114168991 # number of integer regfile writes +system.cpu.fp_regfile_reads 2904222 # number of floating regfile reads +system.cpu.fp_regfile_writes 2441435 # number of floating regfile writes +system.cpu.cc_regfile_reads 708194084 # number of cc regfile reads +system.cpu.cc_regfile_writes 229512691 # number of cc regfile writes +system.cpu.misc_regfile_reads 59249211 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.dcache.tags.replacements 72854 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.416253 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 41114439 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 73366 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 560.401807 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 507537500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.416253 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998860 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998860 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 72581 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.413915 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 41031177 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 73093 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 561.355766 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 508221500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.413915 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998855 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998855 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 231 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 42 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 229 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 44 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 82527906 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 82527906 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 28728233 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28728233 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12341290 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12341290 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 361 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 361 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 82360603 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 82360603 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28644947 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28644947 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12341311 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12341311 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 364 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 364 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22148 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22148 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41069523 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41069523 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41069884 # number of overall hits -system.cpu.dcache.overall_hits::total 41069884 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89457 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89457 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 22997 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 22997 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 118 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 118 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 40986258 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40986258 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40986622 # number of overall hits +system.cpu.dcache.overall_hits::total 40986622 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89227 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89227 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 22976 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22976 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 116 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 116 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 259 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 259 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 112454 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 112454 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 112572 # number of overall misses -system.cpu.dcache.overall_misses::total 112572 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1065753500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1065753500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 241354499 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 241354499 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2315500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 2315500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1307107999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1307107999 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1307107999 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1307107999 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28817690 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28817690 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 112203 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 112203 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 112319 # number of overall misses +system.cpu.dcache.overall_misses::total 112319 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1066843000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1066843000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 241030499 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 241030499 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2297500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 2297500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1307873499 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1307873499 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1307873499 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1307873499 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28734174 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28734174 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 479 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 479 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 480 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 480 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41181977 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41181977 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41182456 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41182456 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003104 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003104 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001860 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001860 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.246347 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.246347 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 41098461 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41098461 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41098941 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41098941 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003105 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003105 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001858 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001858 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.241667 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.241667 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011559 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011559 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002731 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002731 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002730 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002730 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002733 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002733 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11913.584180 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11913.584180 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10495.042788 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10495.042788 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8940.154440 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8940.154440 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 11623.490485 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 11623.490485 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 11611.306533 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 11611.306533 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11956.504197 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11956.504197 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10490.533557 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10490.533557 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8870.656371 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8870.656371 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 11656.314885 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 11656.314885 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 11644.276561 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 11644.276561 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 166 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 10450 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 10738 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 866 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 864 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 83 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 12.066975 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 12.428241 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 72854 # number of writebacks -system.cpu.dcache.writebacks::total 72854 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24777 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 24777 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14426 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 14426 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 72581 # number of writebacks +system.cpu.dcache.writebacks::total 72581 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24802 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 24802 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14421 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 14421 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 259 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 259 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 39203 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 39203 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 39203 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 39203 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64680 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64680 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8571 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 8571 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 115 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 115 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 73251 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 73251 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 73366 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 73366 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 654439000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 654439000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86279999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 86279999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 978000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 978000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 740718999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 740718999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 741696999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 741696999 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002244 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002244 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000693 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000693 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.240084 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.240084 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001779 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001779 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001781 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001781 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10118.104515 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10118.104515 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10066.503208 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10066.503208 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8504.347826 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8504.347826 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10112.066716 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 10112.066716 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10109.546643 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 10109.546643 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 39223 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 39223 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 39223 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 39223 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64425 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 64425 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8555 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 8555 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 113 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 113 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 72980 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 72980 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 73093 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 73093 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 653903000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 653903000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85317499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85317499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 962000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 962000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 739220499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 739220499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 740182499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 740182499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002242 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002242 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000692 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000692 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.235417 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.235417 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001776 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001776 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001778 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001778 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10149.833139 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10149.833139 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9972.822794 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9972.822794 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8513.274336 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8513.274336 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10129.083297 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 10129.083297 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10126.585295 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 10126.585295 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # 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Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 54135 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1445.812413 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 84183071500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.594536 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997255 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997255 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 48 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 51 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 157975329 # Number of tag accesses -system.cpu.icache.tags.data_accesses 157975329 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 78901806 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78901806 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78901806 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78901806 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78901806 # number of overall hits -system.cpu.icache.overall_hits::total 78901806 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 58402 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 58402 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 58402 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 58402 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 58402 # number of overall misses -system.cpu.icache.overall_misses::total 58402 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1157058425 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1157058425 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1157058425 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1157058425 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1157058425 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1157058425 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78960208 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78960208 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78960208 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78960208 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78960208 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78960208 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000740 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000740 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000740 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000740 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000740 # 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number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1155198430 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1155198430 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1155198430 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 78326590 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 78326590 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 78326590 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 78326590 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 78326590 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 78326590 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000735 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000735 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000735 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000735 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000735 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000735 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20078.185974 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20078.185974 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20078.185974 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20078.185974 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20078.185974 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20078.185974 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 73195 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 27 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3397 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3246 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 21.313218 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 22.549291 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 13.500000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 54401 # number of writebacks -system.cpu.icache.writebacks::total 54401 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3488 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3488 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3488 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3488 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3488 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3488 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54914 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 54914 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 54914 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 54914 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 54914 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 54914 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1043630451 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1043630451 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1043630451 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1043630451 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1043630451 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1043630451 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000695 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000695 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000695 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000695 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000695 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000695 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19004.815730 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19004.815730 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19004.815730 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19004.815730 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19004.815730 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19004.815730 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 53623 # number of writebacks +system.cpu.icache.writebacks::total 53623 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3399 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3399 # 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number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1039886452 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1039886452 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1039886452 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1039886452 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000691 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000691 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000691 # 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Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1654 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 2944 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 24 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 87 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 141 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 856 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 162 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1653 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1022 0.015503 # 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average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77647.906471 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75124.142437 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77577.627772 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75576.174825 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75124.142437 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77577.627772 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75576.174825 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1041,136 +1046,136 @@ system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1 system.cpu.l2cache.ReadExReq_mshr_hits::total 1 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 851088649 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027315 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027315 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167079 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.167079 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.028227 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.028227 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167079 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.028119 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.087605 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167079 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.028119 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027140 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027140 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.169536 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.169536 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.028385 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.028385 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.169536 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.028238 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.088360 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.169536 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.028238 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.103555 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 32702.175464 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 32702.175464 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73817.796610 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73817.796610 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68928.283379 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68928.283379 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70928.845101 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70928.845101 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68928.283379 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71259.331071 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69356.202171 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68928.283379 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71259.331071 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 32702.175464 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63710.753613 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.104135 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34294.294469 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 34294.294469 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70476.495726 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70476.495726 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69132.327304 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69132.327304 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71733.333333 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71733.333333 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69132.327304 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71590.843023 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69583.703967 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69132.327304 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71590.843023 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34294.294469 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64237.953732 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 255535 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 127274 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10474 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 11941 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3419 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 8522 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 119639 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 64840 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 62415 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 11001 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 2383 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 8640 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 8640 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 54914 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 64726 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 164228 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 219586 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 383814 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6996096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9358080 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 16354176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 13384 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 141664 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.218517 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.539520 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 253433 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 126224 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10473 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 11905 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3377 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 8528 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 118606 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 64698 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 61506 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 11007 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 2350 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 8622 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 8622 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 54136 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 64471 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 161894 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218767 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 380661 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6896512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9323136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 16219648 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 13357 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 140586 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.219979 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.541213 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 119230 84.16% 84.16% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 13912 9.82% 93.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 8522 6.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 118188 84.07% 84.07% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 13870 9.87% 93.93% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 8528 6.07% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 141664 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 255022500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 140586 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 252920500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 82377983 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 81207989 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 110053990 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 109644490 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 12107 # Transaction distribution -system.membus.trans_dist::ReadExReq 236 # Transaction distribution -system.membus.trans_dist::ReadExResp 236 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 12108 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 24687 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 24687 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 789952 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 789952 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 12116 # Transaction distribution +system.membus.trans_dist::ReadExReq 234 # Transaction distribution +system.membus.trans_dist::ReadExResp 234 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 12117 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 24701 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 24701 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 790400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 790400 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 12344 # Request fanout histogram +system.membus.snoop_fanout::samples 12351 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 12344 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 12351 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 12344 # Request fanout histogram -system.membus.reqLayer0.occupancy 15598659 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 12351 # Request fanout histogram +system.membus.reqLayer0.occupancy 15618188 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 66476550 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 66520835 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index ed3dbc17c..f0a8cbf5a 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.079141 # Number of seconds simulated -sim_ticks 79140979500 # Number of ticks simulated -final_tick 79140979500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.103324 # Number of seconds simulated +sim_ticks 103324153500 # Number of ticks simulated +final_tick 103324153500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 47467 # Simulator instruction rate (inst/s) -host_op_rate 79560 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28443866 # Simulator tick rate (ticks/s) -host_mem_usage 336904 # Number of bytes of host memory used -host_seconds 2782.36 # Real time elapsed on the host +host_inst_rate 72241 # Simulator instruction rate (inst/s) +host_op_rate 121082 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56516511 # Simulator tick rate (ticks/s) +host_mem_usage 307592 # Number of bytes of host memory used +host_seconds 1828.21 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 221376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125056 # Number of bytes read from this memory -system.physmem.bytes_read::total 346432 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 221376 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 221376 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3459 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1954 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5413 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2797236 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1580167 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4377403 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2797236 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2797236 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2797236 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1580167 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4377403 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5413 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 231488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 130496 # Number of bytes read from this memory +system.physmem.bytes_read::total 361984 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 231488 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 231488 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3617 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2039 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5656 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2240405 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1262977 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3503382 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2240405 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2240405 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2240405 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1262977 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3503382 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5656 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5413 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5656 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 346432 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 361984 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 346432 # Total read bytes from the system interface side +system.physmem.bytesReadSys 361984 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 298 # Per bank write bursts -system.physmem.perBankRdBursts::1 346 # Per bank write bursts -system.physmem.perBankRdBursts::2 461 # Per bank write bursts -system.physmem.perBankRdBursts::3 349 # Per bank write bursts -system.physmem.perBankRdBursts::4 340 # Per bank write bursts -system.physmem.perBankRdBursts::5 326 # Per bank write bursts -system.physmem.perBankRdBursts::6 402 # Per bank write bursts -system.physmem.perBankRdBursts::7 384 # Per bank write bursts -system.physmem.perBankRdBursts::8 341 # Per bank write bursts -system.physmem.perBankRdBursts::9 281 # Per bank write bursts -system.physmem.perBankRdBursts::10 239 # Per bank write bursts -system.physmem.perBankRdBursts::11 285 # Per bank write bursts -system.physmem.perBankRdBursts::12 220 # Per bank write bursts -system.physmem.perBankRdBursts::13 466 # Per bank write bursts -system.physmem.perBankRdBursts::14 389 # Per bank write bursts -system.physmem.perBankRdBursts::15 286 # Per bank write bursts +system.physmem.perBankRdBursts::0 310 # Per bank write bursts +system.physmem.perBankRdBursts::1 382 # Per bank write bursts +system.physmem.perBankRdBursts::2 476 # Per bank write bursts +system.physmem.perBankRdBursts::3 358 # Per bank write bursts +system.physmem.perBankRdBursts::4 362 # Per bank write bursts +system.physmem.perBankRdBursts::5 335 # Per bank write bursts +system.physmem.perBankRdBursts::6 419 # Per bank write bursts +system.physmem.perBankRdBursts::7 385 # Per bank write bursts +system.physmem.perBankRdBursts::8 389 # Per bank write bursts +system.physmem.perBankRdBursts::9 295 # Per bank write bursts +system.physmem.perBankRdBursts::10 260 # Per bank write bursts +system.physmem.perBankRdBursts::11 270 # Per bank write bursts +system.physmem.perBankRdBursts::12 228 # Per bank write bursts +system.physmem.perBankRdBursts::13 484 # Per bank write bursts +system.physmem.perBankRdBursts::14 420 # Per bank write bursts +system.physmem.perBankRdBursts::15 283 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 79140890500 # Total gap between requests +system.physmem.totGap 103323899000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5413 # Read request sizes (log2) +system.physmem.readPktSize::6 5656 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 904 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 176 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4508 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 949 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,311 +186,316 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1107 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 311.790425 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 180.924163 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.273428 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 441 39.84% 39.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 229 20.69% 60.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 106 9.58% 70.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 59 5.33% 75.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 51 4.61% 80.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 54 4.88% 84.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 23 2.08% 86.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 18 1.63% 88.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 126 11.38% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1107 # Bytes accessed per row activation -system.physmem.totQLat 40702000 # Total ticks spent queuing -system.physmem.totMemAccLat 142195750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 27065000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7519.31 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1264 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 286.278481 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 164.439317 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 318.670037 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 554 43.83% 43.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 264 20.89% 64.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 105 8.31% 73.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 69 5.46% 78.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 45 3.56% 82.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 57 4.51% 86.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 28 2.22% 88.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 17 1.34% 90.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 125 9.89% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1264 # Bytes accessed per row activation +system.physmem.totQLat 43672750 # Total ticks spent queuing +system.physmem.totMemAccLat 149722750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 28280000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7721.49 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26269.31 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.38 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26471.49 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.50 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.38 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.50 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4302 # Number of row buffer hits during reads +system.physmem.readRowHits 4391 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.48 # Row buffer hit rate for reads +system.physmem.readRowHitRate 77.63 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 14620522.91 # Average gap between requests -system.physmem.pageHitRate 79.48 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4898880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2673000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 22659000 # Energy for read commands per rank (pJ) +system.physmem.avgGap 18268016.09 # Average gap between requests +system.physmem.pageHitRate 77.63 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5624640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3069000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 23610600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5169003840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2477527515 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 45310553250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 52987315485 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.541483 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 75375284000 # Time in different power states -system.physmem_0.memoryStateTime::REF 2642640000 # Time in different power states +system.physmem_0.refreshEnergy 6748591200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3147948405 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 59232949500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 69161793345 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.369133 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 98535205500 # Time in different power states +system.physmem_0.memoryStateTime::REF 3450200000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1122708000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1338454000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3470040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1893375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 19406400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3931200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2145000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 20490600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5169003840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2315256210 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 45452899500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 52961929365 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.220665 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 75612477000 # Time in different power states -system.physmem_1.memoryStateTime::REF 2642640000 # Time in different power states +system.physmem_1.refreshEnergy 6748591200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2964574845 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 59393774250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 69133507095 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.095685 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 98803806250 # Time in different power states +system.physmem_1.memoryStateTime::REF 3450200000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 884606250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1069805000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 20604101 # Number of BP lookups -system.cpu.branchPred.condPredicted 20604101 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1328804 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12707128 # Number of BTB lookups -system.cpu.branchPred.BTBHits 12016946 # Number of BTB hits +system.cpu.branchPred.lookups 40908032 # Number of BP lookups +system.cpu.branchPred.condPredicted 40908032 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6741329 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 35316490 # Number of BTB lookups +system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.568545 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1442846 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 16873 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3206071 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 604531 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 35316490 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 9869044 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 25447446 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 5035252 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 158281960 # number of cpu cycles simulated +system.cpu.numCycles 206648308 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 25261178 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 227540211 # Number of instructions fetch has processed -system.cpu.fetch.Branches 20604101 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13459792 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 131194128 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3196201 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 20 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 1974 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 21216 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 47 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 24267790 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 266999 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 158076676 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.380152 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.324972 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 46351281 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 420030465 # Number of instructions fetch has processed +system.cpu.fetch.Branches 40908032 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13075115 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 152558958 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14935189 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 126 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 5881 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 68758 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 764 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 179 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 41261989 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1525874 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 8 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 206453541 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.416062 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.660543 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 95737541 60.56% 60.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4758449 3.01% 63.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3804662 2.41% 65.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4365114 2.76% 68.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4234763 2.68% 71.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4816060 3.05% 74.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4706873 2.98% 77.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3702906 2.34% 79.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 31950308 20.21% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 99211398 48.06% 48.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5135847 2.49% 50.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5374620 2.60% 53.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5328555 2.58% 55.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 6013612 2.91% 58.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5856529 2.84% 61.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5733209 2.78% 64.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4747222 2.30% 66.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 69052549 33.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 158076676 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.130173 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.437563 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15410588 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96165480 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 23286258 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 21616250 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1598100 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 336629357 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1598100 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 23294906 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 31785653 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 30420 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 36005070 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 65362527 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 328266704 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1575 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 57713164 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7745606 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 167786 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 380441390 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 910027714 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 600617838 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4182134 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 206453541 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.197960 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.032586 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32305475 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 86547165 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 62440790 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 17692517 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 7467594 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 591140753 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 7467594 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 42099614 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 46622929 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 29580 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 68917298 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 41316526 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 552365156 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1615 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 36415427 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4818042 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 146051 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 629691896 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1486514399 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 974943820 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 15152274 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 121011940 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1942 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1920 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 120996238 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 82787388 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 29790681 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 59618218 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 20385333 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 317847098 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5129 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 259397684 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 74444 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 96488843 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 197170698 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3884 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 158076676 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.640961 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.524821 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 370262446 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2381 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2386 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 89347483 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 128815998 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 45923960 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 77358410 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 25275137 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 490566423 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 62065 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 338414549 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1099553 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 269265104 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 527048763 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 60820 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 206453541 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.639180 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.804126 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 40037945 25.33% 25.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 47502914 30.05% 55.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 33077309 20.92% 76.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17993682 11.38% 87.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10964082 6.94% 94.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4766949 3.02% 97.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2459936 1.56% 99.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 882455 0.56% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 391404 0.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 73345677 35.53% 35.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 46646037 22.59% 58.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 32854801 15.91% 74.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20905072 10.13% 84.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 15063521 7.30% 91.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8409386 4.07% 95.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5213188 2.53% 98.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2363320 1.14% 99.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1652539 0.80% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 158076676 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 206453541 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 232294 7.31% 7.31% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.31% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.31% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2560752 80.62% 87.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 383461 12.07% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 758238 19.31% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2733075 69.60% 88.91% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 435620 11.09% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1212757 0.47% 0.47% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 161810976 62.38% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 789695 0.30% 63.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7037932 2.71% 65.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1186383 0.46% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 64896241 25.02% 91.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 22463700 8.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1211810 0.36% 0.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 216608884 64.01% 64.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 799973 0.24% 64.60% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7048329 2.08% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1813849 0.54% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 84312637 24.91% 92.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 26619067 7.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 259397684 # Type of FU issued -system.cpu.iq.rate 1.638833 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3176507 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012246 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 675268326 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 410944101 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 253662317 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4854669 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 3693735 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2339703 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 258916823 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2444611 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18724072 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 338414549 # Type of FU issued +system.cpu.iq.rate 1.637635 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3926933 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011604 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 880106724 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 745207821 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 316030450 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 8202401 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 15512263 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 3567674 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 337013730 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 4115942 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18154732 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 26137801 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13130 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 303242 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 9274964 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 72166411 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 54986 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 863760 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 25408243 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 49887 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 39 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 50543 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 53 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1598100 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 12496395 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 489060 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 317852227 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 92568 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 82787388 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 29790681 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2962 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 383739 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 63074 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 303242 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 551670 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 826736 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1378406 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 257339859 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 64084689 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2057825 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 7467594 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 35770303 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 592137 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 490628488 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1259959 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 128815998 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 45923960 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 22654 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 545800 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 38626 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 863760 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1294864 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 6880130 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8174994 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 326485130 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 80685795 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 11929419 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 86369700 # number of memory reference insts executed -system.cpu.iew.exec_branches 14330688 # Number of branches executed -system.cpu.iew.exec_stores 22285011 # Number of stores executed -system.cpu.iew.exec_rate 1.625832 # Inst execution rate -system.cpu.iew.wb_sent 256690834 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 256002020 # cumulative count of insts written-back -system.cpu.iew.wb_producers 204396152 # num instructions producing a value -system.cpu.iew.wb_consumers 369708063 # num instructions consuming a value -system.cpu.iew.wb_rate 1.617380 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.552858 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 96496520 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 106318426 # number of memory reference insts executed +system.cpu.iew.exec_branches 18939296 # Number of branches executed +system.cpu.iew.exec_stores 25632631 # Number of stores executed +system.cpu.iew.exec_rate 1.579907 # Inst execution rate +system.cpu.iew.wb_sent 322610085 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 319598124 # cumulative count of insts written-back +system.cpu.iew.wb_producers 256503247 # num instructions producing a value +system.cpu.iew.wb_consumers 435667509 # num instructions consuming a value +system.cpu.iew.wb_rate 1.546580 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.588759 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 269290512 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1330625 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 144920750 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.527479 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.956907 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6746174 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 163890954 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.350675 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.933271 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 45508635 31.40% 31.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57312379 39.55% 70.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14158343 9.77% 80.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11991163 8.27% 88.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4086516 2.82% 91.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2858052 1.97% 93.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 923800 0.64% 94.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1073190 0.74% 95.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7008672 4.84% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 67206524 41.01% 41.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 54940140 33.52% 74.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13261155 8.09% 82.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 10687834 6.52% 89.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5446779 3.32% 92.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3132108 1.91% 94.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1092307 0.67% 95.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1156922 0.71% 95.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6967185 4.25% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 144920750 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 163890954 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -536,347 +541,347 @@ system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction -system.cpu.commit.bw_lim_events 7008672 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 455771982 # The number of ROB reads -system.cpu.rob.rob_writes 648913279 # The number of ROB writes -system.cpu.timesIdled 2665 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 205284 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 6967185 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 647577665 # The number of ROB reads +system.cpu.rob.rob_writes 1024269930 # The number of ROB writes +system.cpu.timesIdled 2819 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 194767 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.198459 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.198459 # CPI: Total CPI of All Threads -system.cpu.ipc 0.834405 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.834405 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 448575240 # number of integer regfile reads -system.cpu.int_regfile_writes 232602901 # number of integer regfile writes -system.cpu.fp_regfile_reads 3212636 # number of floating regfile reads -system.cpu.fp_regfile_writes 1997796 # number of floating regfile writes -system.cpu.cc_regfile_reads 102540235 # number of cc regfile reads -system.cpu.cc_regfile_writes 59516419 # number of cc regfile writes -system.cpu.misc_regfile_reads 132474842 # number of misc regfile reads +system.cpu.cpi 1.564674 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.564674 # CPI: Total CPI of All Threads +system.cpu.ipc 0.639111 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.639111 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 524516370 # number of integer regfile reads +system.cpu.int_regfile_writes 289029189 # number of integer regfile writes +system.cpu.fp_regfile_reads 4536413 # number of floating regfile reads +system.cpu.fp_regfile_writes 3331836 # number of floating regfile writes +system.cpu.cc_regfile_reads 107017358 # number of cc regfile reads +system.cpu.cc_regfile_writes 65774990 # number of cc regfile writes +system.cpu.misc_regfile_reads 176892429 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.dcache.tags.replacements 51 # number of replacements -system.cpu.dcache.tags.tagsinuse 1429.115986 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 65747319 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1995 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 32956.049624 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 72 # number of replacements +system.cpu.dcache.tags.tagsinuse 1525.498489 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 82766316 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2113 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 39170.050166 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1429.115986 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.348905 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.348905 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1944 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1525.498489 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.372436 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.372436 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2041 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 34 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 498 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1394 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.474609 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 131501477 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 131501477 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 45233030 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 45233030 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513912 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513912 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 65746942 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 65746942 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 65746942 # number of overall hits -system.cpu.dcache.overall_hits::total 65746942 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 980 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 980 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1819 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1819 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2799 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2799 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2799 # number of overall misses -system.cpu.dcache.overall_misses::total 2799 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 65149000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 65149000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 128515000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 128515000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 193664000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 193664000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 193664000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 193664000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 45234010 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 45234010 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 101 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 409 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1484 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.498291 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 165539971 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 165539971 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 62251936 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 62251936 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513707 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513707 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 82765643 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 82765643 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 82765643 # number of overall hits +system.cpu.dcache.overall_hits::total 82765643 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1262 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1262 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2024 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2024 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3286 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3286 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3286 # number of overall misses +system.cpu.dcache.overall_misses::total 3286 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 84231000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 84231000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 131983500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 131983500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 216214500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 216214500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 216214500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 216214500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 62253198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 62253198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 65749741 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 65749741 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 65749741 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 65749741 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66478.571429 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66478.571429 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70651.456844 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70651.456844 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 69190.425152 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69190.425152 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 69190.425152 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69190.425152 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 656 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 70 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 93.714286 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 70 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 82768929 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 82768929 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 82768929 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 82768929 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000099 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000099 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000040 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000040 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000040 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000040 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66744.057052 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66744.057052 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65209.239130 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65209.239130 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65798.691418 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65798.691418 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65798.691418 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65798.691418 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 369 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 73 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.125000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 36.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 10 # number of writebacks -system.cpu.dcache.writebacks::total 10 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 526 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 526 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 528 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 528 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 528 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 528 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 454 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 454 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1817 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1817 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2271 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2271 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2271 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2271 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36063500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36063500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 126552000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 126552000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 162615500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 162615500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 162615500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 162615500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 18 # number of writebacks +system.cpu.dcache.writebacks::total 18 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 661 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 661 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 7 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 7 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 668 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 668 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 668 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 668 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 601 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 601 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2017 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2017 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2618 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2618 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2618 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2618 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47710000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 47710000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 129636500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 129636500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 177346500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 177346500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 177346500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 177346500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000035 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000035 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79435.022026 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79435.022026 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69648.871767 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69648.871767 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71605.239982 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71605.239982 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71605.239982 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71605.239982 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000098 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000098 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79384.359401 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79384.359401 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64271.938523 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64271.938523 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67741.214668 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67741.214668 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67741.214668 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67741.214668 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 5017 # number of replacements -system.cpu.icache.tags.tagsinuse 1636.805094 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 24258360 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6993 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3468.948949 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 6515 # number of replacements +system.cpu.icache.tags.tagsinuse 1663.291735 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 41248897 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8499 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 4853.382398 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1636.805094 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.799221 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.799221 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1976 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 869 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 788 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.964844 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 48542846 # Number of tag accesses -system.cpu.icache.tags.data_accesses 48542846 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 24258361 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 24258361 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 24258361 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 24258361 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 24258361 # number of overall hits -system.cpu.icache.overall_hits::total 24258361 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 9428 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 9428 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 9428 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 9428 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 9428 # number of overall misses -system.cpu.icache.overall_misses::total 9428 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 409015499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 409015499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 409015499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 409015499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 409015499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 409015499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 24267789 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 24267789 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 24267789 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 24267789 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 24267789 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 24267789 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000388 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000388 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000388 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000388 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000388 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000388 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43383.060989 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 43383.060989 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 43383.060989 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 43383.060989 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 43383.060989 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 43383.060989 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 793 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 61 # 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average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 37114.447246 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 37114.447246 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 37114.447246 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2090 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 305 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 30 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 69.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 305 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 5017 # 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average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65842.774566 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67155.578301 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66316.586627 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65842.774566 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67155.578301 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66316.586627 # average overall mshr miss latency +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 500 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 500 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1507 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1507 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 238858000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137619000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 376477000 # number of overall MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990099 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990099 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996034 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996034 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.425830 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.425830 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.886667 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.886667 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.425830 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964979 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.533233 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.425830 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964979 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.533233 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19007 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19007 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64357.000664 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64357.000664 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66037.600221 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66037.600221 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76377.819549 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76377.819549 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66037.600221 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67493.379107 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66562.411598 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66037.600221 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67493.379107 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66562.411598 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 14608 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 5367 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 376 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 18206 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 7138 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 549 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 7722 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 5017 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 41 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 276 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 276 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1541 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1541 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 7269 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 454 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19276 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4593 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 23869 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 768448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128320 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 896768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 278 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 9540 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.070650 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.256253 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 9600 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 18 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 6515 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 54 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 505 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 505 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1513 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1513 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 9001 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 600 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24009 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5308 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 29317 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 960512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 136384 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1096896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 507 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 11619 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.094328 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.292297 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 8866 92.94% 92.94% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 674 7.06% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 10523 90.57% 90.57% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1096 9.43% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 9540 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12331000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11619 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 15636499 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 10902000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 13500000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3131498 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3422499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3878 # Transaction distribution -system.membus.trans_dist::UpgradeReq 275 # Transaction distribution -system.membus.trans_dist::ReadExReq 1535 # Transaction distribution -system.membus.trans_dist::ReadExResp 1535 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3878 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11101 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11101 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11101 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 346432 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 346432 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 346432 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 4149 # Transaction distribution +system.membus.trans_dist::UpgradeReq 500 # Transaction distribution +system.membus.trans_dist::ReadExReq 1507 # Transaction distribution +system.membus.trans_dist::ReadExResp 1507 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 4149 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11812 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11812 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11812 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 361984 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 361984 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 361984 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5688 # Request fanout histogram +system.membus.snoop_fanout::samples 6156 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5688 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 6156 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5688 # Request fanout histogram -system.membus.reqLayer0.occupancy 6954000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 6156 # Request fanout histogram +system.membus.reqLayer0.occupancy 7649501 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 28681250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 30011250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |